diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-23 09:50:39 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-23 15:18:44 +0200 |
commit | 8f8ccee0d9e1c3adfb1de484f26f6d9f6ff08708 (patch) | |
tree | 5dc76f7a4527b0a500fbf5ee91486b2780e47a1a /bsps/arm/gdbarmsim | |
parent | bsps: Move SPI drivers to bsps (diff) | |
download | rtems-8f8ccee0d9e1c3adfb1de484f26f6d9f6ff08708.tar.bz2 |
bsps: Move interrupt controller support to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/arm/gdbarmsim')
-rw-r--r-- | bsps/arm/gdbarmsim/irq/irq-dispatch.c | 50 | ||||
-rw-r--r-- | bsps/arm/gdbarmsim/irq/irq.c | 71 |
2 files changed, 121 insertions, 0 deletions
diff --git a/bsps/arm/gdbarmsim/irq/irq-dispatch.c b/bsps/arm/gdbarmsim/irq/irq-dispatch.c new file mode 100644 index 0000000000..f045fb8149 --- /dev/null +++ b/bsps/arm/gdbarmsim/irq/irq-dispatch.c @@ -0,0 +1,50 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief GDB ARM Simulator interrupt support. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems/score/armv4.h> + +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/irq-generic.h> + +#ifdef ARM_MULTILIB_ARCH_V4 + +void bsp_interrupt_dispatch(void) +{ + /* Read current vector number */ + /* rtems_vector_number vector = VICVectAddr; */ + rtems_vector_number vector = 0; + + /* Enable interrupts in program status register */ + uint32_t psr = _ARMV4_Status_irq_enable(); + + /* Dispatch interrupt handlers */ + bsp_interrupt_handler_dispatch(vector); + + /* Restore program status register */ + _ARMV4_Status_restore(psr); + + /* Acknowledge interrupt */ + //VICVectAddr = 0; +} + +#endif /* ARM_MULTILIB_ARCH_V4 */ diff --git a/bsps/arm/gdbarmsim/irq/irq.c b/bsps/arm/gdbarmsim/irq/irq.c new file mode 100644 index 0000000000..886f928d2d --- /dev/null +++ b/bsps/arm/gdbarmsim/irq/irq.c @@ -0,0 +1,71 @@ +/** + * @file + * + * @ingroup bsp_interrupt + * + * @brief GDB ARM Simulator interrupt support. + */ + +/* + * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems/score/armv4.h> +#include <rtems/score/armv7m.h> + +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/irq-generic.h> +#include <bsp/linker-symbols.h> + +/* + * Prototypes + */ +void lpc24xx_irq_set_priority(rtems_vector_number, unsigned); +unsigned lpc24xx_irq_get_priority(rtems_vector_number); + +static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector) +{ + return vector <= BSP_INTERRUPT_VECTOR_MAX; +} + +void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority) +{ +} + +unsigned lpc24xx_irq_get_priority(rtems_vector_number vector) +{ + return 0; /* bogus value to avoid warning */ +} + +#ifdef ARM_MULTILIB_ARCH_V4 + +void bsp_interrupt_vector_enable(rtems_vector_number vector) +{ + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); +} + +void bsp_interrupt_vector_disable(rtems_vector_number vector) +{ + bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); +} + +rtems_status_code bsp_interrupt_facility_initialize(void) +{ + /* Install the IRQ exception handler */ + _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL); + + return RTEMS_SUCCESSFUL; +} + +#endif /* ARM_MULTILIB_ARCH_V4 */ |