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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 10:19:28 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 13:08:36 +0200 |
commit | fbcd7c8fa65eb695e96a62ea1c1ac7a024fa9dfc (patch) | |
tree | a17e285cf22cd49cd42e8b3ad562febc3987d566 /bsps/arm/csb336 | |
parent | bsps: Move console drivers to bsps (diff) | |
download | rtems-fbcd7c8fa65eb695e96a62ea1c1ac7a024fa9dfc.tar.bz2 |
bsps: Move start files to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/arm/csb336')
-rw-r--r-- | bsps/arm/csb336/start/start.S | 166 |
1 files changed, 166 insertions, 0 deletions
diff --git a/bsps/arm/csb336/start/start.S b/bsps/arm/csb336/start/start.S new file mode 100644 index 0000000000..ce452f52a2 --- /dev/null +++ b/bsps/arm/csb336/start/start.S @@ -0,0 +1,166 @@ +/* + * Cogent CSB336 startup code + * + * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp/linker-symbols.h> + +/* Some standard definitions...*/ +.equ PSR_MODE_USR, 0x10 +.equ PSR_MODE_FIQ, 0x11 +.equ PSR_MODE_IRQ, 0x12 +.equ PSR_MODE_SVC, 0x13 +.equ PSR_MODE_ABT, 0x17 +.equ PSR_MODE_UNDEF, 0x1B +.equ PSR_MODE_SYS, 0x1F + +.equ PSR_I, 0x80 +.equ PSR_F, 0x40 +.equ PSR_T, 0x20 + +.section .bsp_start_text,"ax" + .code 32 +_start_jump_at_origin: + ldr pc, _start_address +_start_address: + .word _start + +.text +.globl _start +_start: + /* + * Since I don't plan to return to the bootloader, + * I don't have to save the registers. + * + * I'll just set the CPSR for SVC mode, interrupts + * off, and ARM instructions. + */ + mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) + msr cpsr, r0 + + /* zero the bss */ + ldr r1, =bsp_section_bss_end + ldr r0, =bsp_section_bss_begin + +_bss_init: + mov r2, #0 + cmp r0, r1 + strlot r2, [r0], #4 + blo _bss_init /* loop while r0 < r1 */ + + + /* --- Initialize stack pointer registers */ + /* Enter IRQ mode and set up the IRQ stack pointer */ + mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ + msr cpsr, r0 + ldr r1, =bsp_stack_irq_size + ldr sp, =bsp_stack_irq_begin + add sp, sp, r1 + + /* Enter FIQ mode and set up the FIQ stack pointer */ + mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ + msr cpsr, r0 + ldr r1, =bsp_stack_fiq_size + ldr sp, =bsp_stack_fiq_begin + add sp, sp, r1 + + /* Enter ABT mode and set up the ABT stack pointer */ + mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ + msr cpsr, r0 + ldr r1, =bsp_stack_abt_size + ldr sp, =bsp_stack_abt_begin + add sp, sp, r1 + + /* Enter UNDEF mode and set up the UNDEF stack pointer */ + mov r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F) /* No interrupts */ + msr cpsr, r0 + ldr r1, =bsp_stack_und_size + ldr sp, =bsp_stack_und_begin + add sp, sp, r1 + + /* Set up the SVC stack pointer last and stay in SVC mode */ + mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ + msr cpsr, r0 + ldr r1, =bsp_stack_svc_size + ldr sp, =bsp_stack_svc_begin + add sp, sp, r1 + sub sp, sp, #0x64 + + /* + * Initialize the MMU. After we return, the MMU is enabled, + * and memory may be remapped. I hope we don't remap this + * memory away. + */ + ldr r0, =mem_map + bl mmu_init + + /* + * Initialize the exception vectors. This includes the + * exceptions vectors (0x00000000-0x0000001c), and the + * pointers to the exception handlers (0x00000020-0x0000003c). + */ + mov r0, #0 + adr r1, vector_block + ldmia r1!, {r2-r9} + stmia r0!, {r2-r9} + ldmia r1!, {r2-r9} + stmia r0!, {r2-r9} + + /* Now we are prepared to start the BSP's C code */ + mov r0, #0 + bl boot_card + + /* + * Theoretically, we could return to what started us up, + * but we'd have to have saved the registers and stacks. + * Instead, we'll just reset. + */ + bl bsp_reset + + /* We shouldn't get here. If we do, hang */ +_hang: b _hang + + +/* + * This is the exception vector table and the pointers to + * the functions that handle the exceptions. It's a total + * of 16 words (64 bytes) + */ +vector_block: + ldr pc, handler_addr_reset + ldr pc, handler_addr_undef + ldr pc, handler_addr_swi + ldr pc, handler_addr_prefetch + ldr pc, handler_addr_abort + nop + ldr pc, handler_addr_irq + ldr pc, handler_addr_fiq + +handler_addr_reset: + .word bsp_reset + +handler_addr_undef: + .word _ARMV4_Exception_undef_default + +handler_addr_swi: + .word _ARMV4_Exception_swi_default + +handler_addr_prefetch: + .word _ARMV4_Exception_pref_abort_default + +handler_addr_abort: + .word _ARMV4_Exception_data_abort_default + +handler_addr_reserved: + .word _ARMV4_Exception_reserved_default + +handler_addr_irq: + .word _ARMV4_Exception_interrupt + +handler_addr_fiq: + .word _ARMV4_Exception_fiq_default |