bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

11 files changed, 561 insertions, 0 deletions

diff --git a/bsps/arm/altera-cyclone-v/start/bsp_specs b/bsps/arm/altera-cyclone-v/start/bsp_specs
new file mode 100644
index 0000000000..47dd31d46b
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/arm/altera-cyclone-v/start/bspclean.c b/bsps/arm/altera-cyclone-v/start/bspclean.c
new file mode 100644
index 0000000000..8b95deb801
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bspclean.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <rtems/bspIo.h>
+#include <rtems/score/smpimpl.h>
+
+void bsp_fatal_extension(
+  rtems_fatal_source src,
+  bool always_set_to_false,
+  rtems_fatal_code code
+)
+{
+#ifdef RTEMS_SMP
+  if (src == RTEMS_FATAL_SOURCE_SMP && code == SMP_FATAL_SHUTDOWN_RESPONSE) {
+    while (true) {
+      _ARM_Wait_for_event();
+    }
+  }
+#endif
+
+#if BSP_PRINT_EXCEPTION_CONTEXT
+  if (src == RTEMS_FATAL_SOURCE_EXCEPTION) {
+    rtems_exception_frame_print((const rtems_exception_frame *) code);
+  }
+#endif
+
+#if BSP_RESET_BOARD_AT_EXIT
+  bsp_reset();
+#endif
+}
diff --git a/bsps/arm/altera-cyclone-v/start/bspgetworkarea.c b/bsps/arm/altera-cyclone-v/start/bspgetworkarea.c
new file mode 100644
index 0000000000..a3c702de98
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bspgetworkarea.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2017 embedded brains GmbH
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/bootcard.h>
+#include <bsp/arm-cp15-start.h>
+#include <bsp/fdt.h>
+#include <bsp/linker-symbols.h>
+
+#include <libcpu/arm-cp15.h>
+
+#include <libfdt.h>
+
+#define AREA_COUNT_MAX 16
+
+static const char memory_path[] = "/memory";
+
+static const char reserved_memory_path[] = "/reserved-memory";
+
+static void adjust_memory_size(const void *fdt, Heap_Area *area)
+{
+  int node;
+
+  node = fdt_path_offset_namelen(
+    fdt,
+    memory_path,
+    (int) sizeof(memory_path) - 1
+  );
+
+  if (node >= 0) {
+    int len;
+    const void *val;
+    uintptr_t begin;
+    uintptr_t size;
+    uintptr_t a_bit;
+
+    val = fdt_getprop(fdt, node, "reg", &len);
+    if (len == 8) {
+      begin = fdt32_to_cpu(((fdt32_t *) val)[0]);
+      size = fdt32_to_cpu(((fdt32_t *) val)[1]);
+    } else {
+      begin = 0;
+      size = 0;
+    }
+
+    /*
+     * Remove a bit to avoid problems with speculative memory accesses beyond
+     * the valid memory area.
+     */
+    a_bit = 0x100000;
+    if (size >= a_bit) {
+      size -= a_bit;
+    }
+
+    if (
+      begin == 0
+        && size > (uintptr_t) bsp_section_work_end
+        && (uintptr_t) bsp_section_nocache_end
+          < (uintptr_t) bsp_section_work_end
+    ) {
+      area->size += size - (uintptr_t) bsp_section_work_end;
+    }
+  }
+}
+
+static Heap_Area *find_area(
+  Heap_Area *areas,
+  size_t area_count,
+  uint32_t begin
+)
+{
+  size_t i;
+
+  for (i = 0; i < area_count; ++i) {
+    uintptr_t b;
+    uintptr_t e;
+
+    b = (uintptr_t) areas[i].begin;
+    e = b + (uintptr_t) areas[i].size;
+
+    if (b <= begin && begin < e) {
+      return &areas[i];
+    }
+  }
+
+  return NULL;
+}
+
+static size_t remove_reserved_memory(
+  const void *fdt,
+  Heap_Area *areas,
+  size_t area_count
+)
+{
+  int node;
+
+  node = fdt_path_offset_namelen(
+    fdt,
+    reserved_memory_path,
+    (int) sizeof(reserved_memory_path) - 1
+  );
+
+  if (node >= 0) {
+    node = fdt_first_subnode(fdt, node);
+
+    while (node >= 0) {
+      int len;
+      const void *val;
+      uintptr_t area_begin;
+      uintptr_t area_end;
+      uintptr_t hole_begin;
+      uintptr_t hole_end;
+      Heap_Area *area;
+
+      val = fdt_getprop(fdt, node, "reg", &len);
+      if (len == 8) {
+        hole_begin = fdt32_to_cpu(((fdt32_t *) val)[0]);
+        hole_end = hole_begin + fdt32_to_cpu(((fdt32_t *) val)[1]);
+      } else {
+        rtems_panic("unexpected reserved memory area");
+      }
+
+      area = find_area(areas, area_count, hole_begin);
+      area_begin = (uintptr_t) area->begin;
+      area_end = area_begin + (uintptr_t) area->size;
+      area->size = hole_begin - area_begin;
+
+      if (hole_end <= area_end) {
+        if (area_count >= AREA_COUNT_MAX) {
+          rtems_panic("too many reserved memory areas");
+        }
+
+        area = &areas[area_count];
+        ++area_count;
+        area->begin = (void *) hole_end;
+        area->size = area_end - hole_end;
+      }
+
+      node = fdt_next_subnode(fdt, node);
+    }
+  }
+
+  return area_count;
+}
+
+void bsp_work_area_initialize(void)
+{
+  const void *fdt;
+  Heap_Area areas[AREA_COUNT_MAX];
+  size_t area_count;
+  size_t i;
+
+  areas[0].begin = bsp_section_work_begin;
+  areas[0].size = (uintptr_t) bsp_section_work_size;
+  area_count = 1;
+
+  fdt = bsp_fdt_get();
+
+  adjust_memory_size(fdt, &areas[0]);
+  area_count = remove_reserved_memory(fdt, areas, area_count);
+
+  for (i = 0; i < area_count; ++i) {
+    arm_cp15_set_translation_table_entries(
+      areas[i].begin,
+      (void *) ((uintptr_t) areas[i].begin + areas[i].size),
+      ARMV7_MMU_READ_WRITE_CACHED
+    );
+  }
+
+  bsp_work_area_initialize_with_table(areas, area_count);
+}
diff --git a/bsps/arm/altera-cyclone-v/start/bspreset.c b/bsps/arm/altera-cyclone-v/start/bspreset.c
new file mode 100644
index 0000000000..c4af106fed
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bspreset.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/bootcard.h>
+#include <bsp/alt_reset_manager.h>
+
+void bsp_reset(void)
+{
+  alt_reset_cold_reset();
+}
diff --git a/bsps/arm/altera-cyclone-v/start/bspsmp.c b/bsps/arm/altera-cyclone-v/start/bspsmp.c
new file mode 100644
index 0000000000..9c3c9dcffe
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bspsmp.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/score/smpimpl.h>
+
+#include <bsp/start.h>
+
+#include <bsp/socal/alt_rstmgr.h>
+#include <bsp/socal/alt_sysmgr.h>
+#include <bsp/socal/hps.h>
+#include <bsp/socal/socal.h>
+
+bool _CPU_SMP_Start_processor(uint32_t cpu_index)
+{
+  bool started;
+
+  if (cpu_index == 1) {
+    alt_write_word(
+      ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST,
+      ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET((uint32_t) _start)
+    );
+
+    alt_clrbits_word(
+      ALT_RSTMGR_MPUMODRST_ADDR,
+      ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
+    );
+
+    /*
+     * Wait for secondary processor to complete its basic initialization so
+     * that we can enable the unified L2 cache.
+     */
+    started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
+  } else {
+    started = false;
+  }
+
+  return started;
+}
diff --git a/bsps/arm/altera-cyclone-v/start/bspstart.c b/bsps/arm/altera-cyclone-v/start/bspstart.c
new file mode 100644
index 0000000000..0345a4c0a7
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bspstart.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/bootcard.h>
+#include <bsp/arm-a9mpcore-clock.h>
+#include <bsp/fdt.h>
+#include <bsp/irq-generic.h>
+#include <bsp/linker-symbols.h>
+
+#include <bsp/alt_clock_manager.h>
+
+#include <libfdt.h>
+
+uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
+{
+  return intr[1] + 32;
+}
+
+static void set_clock(
+  const void *fdt,
+  int parent,
+  ALT_CLK_t clk,
+  const char *name
+)
+{
+  int node;
+  int len;
+  const uint32_t *val;
+
+  node = fdt_subnode_offset(fdt, parent, name);
+  val = fdt_getprop(fdt, node, "clock-frequency", &len);
+
+  if (val != NULL && len >= 4) {
+    alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
+  }
+}
+
+static void set_clock_by_output_name(
+  const void *fdt,
+  ALT_CLK_t clk,
+  const char *clock_output_name
+)
+{
+  int node;
+  int len;
+  const uint32_t *val;
+
+  node = fdt_node_offset_by_prop_value(
+    fdt,
+    -1,
+    "clock-output-names",
+    clock_output_name,
+    strlen(clock_output_name) + 1
+  );
+  val = fdt_getprop(fdt, node, "clock-frequency", &len);
+
+  if (val != NULL && len >= 4) {
+    alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0]));
+  }
+}
+
+static void update_clocks(void)
+{
+  const void *fdt;
+  int parent;
+
+  fdt = bsp_fdt_get();
+
+  /* Try to set by node name */
+  parent = fdt_node_offset_by_compatible(fdt, -1, "altr,clk-mgr");
+  parent = fdt_subnode_offset(fdt, parent, "clocks");
+  set_clock(fdt, parent, ALT_CLK_OSC1, "osc1");
+  set_clock(fdt, parent, ALT_CLK_IN_PIN_OSC2, "osc2");
+  set_clock(fdt, parent, ALT_CLK_F2H_PERIPH_REF, "f2s_periph_ref_clk");
+  set_clock(fdt, parent, ALT_CLK_F2H_SDRAM_REF, "f2s_sdram_ref_clk");
+
+  /* Try to set by "clock-output-names" property value */
+  set_clock_by_output_name(fdt, ALT_CLK_OSC1, "hps_0_eosc1-clk");
+  set_clock_by_output_name(fdt, ALT_CLK_IN_PIN_OSC2, "hps_0_eosc2-clk");
+  set_clock_by_output_name(fdt, ALT_CLK_F2H_PERIPH_REF, "hps_0_f2s_periph_ref_clk-clk");
+  set_clock_by_output_name(fdt, ALT_CLK_F2H_SDRAM_REF, "hps_0_f2s_sdram_ref_clk-clk");
+}
+
+void bsp_start(void)
+{
+  update_clocks();
+  a9mpcore_clock_initialize_early();
+  bsp_interrupt_initialize();
+  rtems_cache_coherent_add_area(
+    bsp_section_nocacheheap_begin,
+    (uintptr_t) bsp_section_nocacheheap_size
+  );
+}
diff --git a/bsps/arm/altera-cyclone-v/start/bspstarthooks.c b/bsps/arm/altera-cyclone-v/start/bspstarthooks.c
new file mode 100644
index 0000000000..69a178e3ad
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/bspstarthooks.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/arm-cp15-start.h>
+#include <bsp/arm-a9mpcore-start.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/alt_address_space.h>
+#include <bsp/socal/socal.h>
+#include <bsp/socal/alt_sdr.h>
+#include <bsp/socal/hps.h>
+
+/* 1 MB reset default value for address filtering start */
+#define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
+{
+  arm_cp15_instruction_cache_invalidate();
+  arm_cp15_data_cache_invalidate_all_levels();
+  arm_a9mpcore_start_hook_0();
+}
+
+BSP_START_TEXT_SECTION static void setup_mmu_and_cache(void)
+{
+  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
+    ARM_CP15_CTRL_A | ARM_CP15_CTRL_M,
+    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
+  );
+
+  arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
+    ctrl,
+    (uint32_t *) bsp_translation_table_base,
+    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
+    &arm_cp15_start_mmu_config_table[0],
+    arm_cp15_start_mmu_config_table_size
+  );
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
+{
+  uint32_t addr_filt_start;
+  uint32_t addr_filt_end;
+
+  /* Disable ECC. Preloader respectively UBoot enable ECC.
+     But they do run without interrupts. Our BSP will enable interrupts
+     and get spurious ECC error interrupts. Thus we disasable ECC
+     until we either know about a better handling or Altera has modified
+     it's SDRAM settings to not create possibly false ECC errors */
+  uint32_t ctlcfg = alt_read_word( ALT_SDR_CTL_CTLCFG_ADDR );
+  ctlcfg &= ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK;
+  alt_write_word( ALT_SDR_CTL_CTLCFG_ADDR, ctlcfg );
+
+  /* Perform L3 remap register programming first by setting the desired new MPU
+     address space 0 mapping. Assume BOOTROM in order to be able to boot the
+     second core. */
+  alt_addr_space_remap(
+    ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,
+    ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM,
+    ALT_ADDR_SPACE_H2F_ACCESSIBLE,
+    ALT_ADDR_SPACE_LWH2F_ACCESSIBLE );
+
+  /* Next, adjust the L2 cache address filtering range. Set the start address
+   * to the default reset value and retain the existing end address
+   * configuration. */
+  alt_l2_addr_filter_cfg_get( &addr_filt_start, &addr_filt_end );
+
+  if ( addr_filt_start != BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET ) {
+    alt_l2_addr_filter_cfg_set( BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET,
+                                addr_filt_end );
+  }
+
+  arm_a9mpcore_start_hook_1();
+  bsp_start_copy_sections();
+  setup_mmu_and_cache();
+#ifndef RTEMS_SMP
+  /* Enable unified L2 cache */
+  rtems_cache_enable_data();
+#endif
+  bsp_start_clear_bss();
+}
diff --git a/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv
new file mode 100644
index 0000000000..810c4eb1b8
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv
@@ -0,0 +1,29 @@
+REGION_ALIAS ("REGION_START",          RAM);
+REGION_ALIAS ("REGION_VECTOR",         RAM);
+REGION_ALIAS ("REGION_TEXT",           RAM);
+REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);
+REGION_ALIAS ("REGION_RODATA",         RAM);
+REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);
+REGION_ALIAS ("REGION_DATA",           RAM);
+REGION_ALIAS ("REGION_DATA_LOAD",      RAM);
+REGION_ALIAS ("REGION_FAST_TEXT",      RAM);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+REGION_ALIAS ("REGION_FAST_DATA",      RAM);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+REGION_ALIAS ("REGION_BSS",            RAM);
+REGION_ALIAS ("REGION_WORK",           RAM);
+REGION_ALIAS ("REGION_STACK",          RAM);
+REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
+REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
+bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
+
+bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
+
+bsp_vector_table_in_start_section = 1;
+
+bsp_translation_table_base = ORIGIN (RAM_MMU);
+bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit
new file mode 100644
index 0000000000..546db0e123
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit
@@ -0,0 +1,7 @@
+MEMORY {
+   RAM_MMU : ORIGIN = 0x00100000, LENGTH = 16k
+   NOCACHE : ORIGIN = 0x00200000, LENGTH = 1M
+   RAM     : ORIGIN = 0x00300000, LENGTH = 256M - 1M - 1M - 1M
+}
+
+INCLUDE linkcmds.altcycv
diff --git a/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp
new file mode 100644
index 0000000000..2da086579f
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/linkcmds.altcycv_devkit_smp
@@ -0,0 +1,3 @@
+bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 2;
+
+INCLUDE linkcmds.altcycv_devkit
diff --git a/bsps/arm/altera-cyclone-v/start/mmu-config.c b/bsps/arm/altera-cyclone-v/start/mmu-config.c
new file mode 100644
index 0000000000..9d56e5c8f5
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/start/mmu-config.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/arm-cp15-start.h>
+
+const arm_cp15_start_section_config arm_cp15_start_mmu_config_table[] = {
+  ARMV7_CP15_START_DEFAULT_SECTIONS,
+  { /* Periphery area */
+    .begin = 0xFC000000U,
+    .end   = 0x00000000U,
+    .flags = ARMV7_MMU_DEVICE
+  }
+};
+
+const size_t arm_cp15_start_mmu_config_table_size =
+  RTEMS_ARRAY_SIZE(arm_cp15_start_mmu_config_table);