diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-12-28 13:13:38 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2023-01-04 13:11:29 -0600 |
| commit | f65bbb405910df12f5482792fb09f9105e7cec6d (patch) | |
| tree | 238e6cc22cbf26ecf07454cb2184e219a35fd1b4 /bsps/aarch64/xilinx-zynqmp/include/bsp.h | |
| parent | arm: Enable thread ID register for ARMv6 (diff) | |
| download | rtems-f65bbb405910df12f5482792fb09f9105e7cec6d.tar.bz2 | |
bsps: Move ZynqMP-specific info into the BSP
The address of the nandpsu peripheral is specific to the ZynqMP SoC and
not relevant to other devices that might have one or more instances of
this peripheral.
Diffstat (limited to 'bsps/aarch64/xilinx-zynqmp/include/bsp.h')
| -rw-r--r-- | bsps/aarch64/xilinx-zynqmp/include/bsp.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h b/bsps/aarch64/xilinx-zynqmp/include/bsp.h index bb7df94fd1..572963af4c 100644 --- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h +++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h @@ -67,6 +67,8 @@ extern "C" { extern unsigned int zynqmp_dtb_len; extern unsigned char zynqmp_dtb[]; +#define NANDPSU_BASEADDR 0xFF100000 + /** * @brief Zynq UltraScale+ MPSoC specific set up of the MMU. * |