diff options
author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-07-26 15:43:00 -0500 |
---|---|---|
committer | Joel Sherrill <joel@rtems.org> | 2021-09-21 08:58:32 -0500 |
commit | 5f652cb27e0134362e0160135124352539315845 (patch) | |
tree | a370df31b31472331566975319b8fc9fa950d4d4 /bsps/aarch64/shared/start/aarch64-smp.c | |
parent | bsps/gicv2: Allow BSPs to define IRQ attributes (diff) | |
download | rtems-5f652cb27e0134362e0160135124352539315845.tar.bz2 |
cpukit: Add AArch64 SMP Support
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
Diffstat (limited to 'bsps/aarch64/shared/start/aarch64-smp.c')
-rw-r--r-- | bsps/aarch64/shared/start/aarch64-smp.c | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/bsps/aarch64/shared/start/aarch64-smp.c b/bsps/aarch64/shared/start/aarch64-smp.c new file mode 100644 index 0000000000..5ec7babce7 --- /dev/null +++ b/bsps/aarch64/shared/start/aarch64-smp.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Shared + * + * @brief SMP startup and interop code. + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * Written by Kinsey Moore <kinsey.moore@oarcorp.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/score/smpimpl.h> + +#include <bsp/irq.h> + +static void bsp_inter_processor_interrupt( void *arg ) +{ + _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() ); +} + +uint32_t _CPU_SMP_Initialize( void ) +{ + return arm_gic_irq_processor_count(); +} + +void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ) +{ + if ( cpu_count > 0 ) { + rtems_status_code sc; + + sc = rtems_interrupt_handler_install( + ARM_GIC_IRQ_SGI_0, + "IPI", + RTEMS_INTERRUPT_UNIQUE, + bsp_inter_processor_interrupt, + NULL + ); + _Assert( sc == RTEMS_SUCCESSFUL ); + (void) sc; + +#if defined( BSP_DATA_CACHE_ENABLED ) || \ + defined( BSP_INSTRUCTION_CACHE_ENABLED ) + /* Enable unified L2 cache */ + rtems_cache_enable_data(); +#endif + } +} + +void _CPU_SMP_Prepare_start_multitasking( void ) +{ + /* Do nothing */ +} + +void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ) +{ + arm_gic_irq_generate_software_irq( + ARM_GIC_IRQ_SGI_0, + 1U << target_processor_index + ); +} |