diff options
| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2014-05-28 14:47:01 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-05-28 14:59:01 +0200 |
| commit | dda78f43d532e44151afff2684ea24f0f47f35d7 (patch) | |
| tree | 897bb014cf661024e57a9cf0404173c89c00660e | |
| parent | bsp/arm: Broadcast cache maintenances (diff) | |
| download | rtems-dda78f43d532e44151afff2684ea24f0f47f35d7.tar.bz2 | |
bsp/altera-vyclone-v: Broadcast cache maintenances
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c index 140156c916..18c65b4bfc 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c @@ -132,16 +132,16 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) #ifdef RTEMS_SMP /* Enable cache coherency support for this processor */ uint32_t actlr = arm_cp15_get_auxiliary_control(); - actlr |= ARM_CORTEX_A9_ACTL_SMP; + actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; arm_cp15_set_auxiliary_control(actlr); #endif if (cpu_id == 0) { arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF); } - + setup_mmu_and_cache( cpu_id ); - + #ifdef RTEMS_SMP if (cpu_id != 0) { arm_a9mpcore_start_set_vector_base(); |