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authorGedare Bloom <gedare@rtems.org>2021-06-22 19:55:39 -0600
committerGedare Bloom <gedare@rtems.org>2021-06-24 09:37:31 -0600
commitbcad0aaee635d75be9c27b8792f0f69dedd03a57 (patch)
tree3b91fbb8e161763701529994360bbf54179bd09f
parentfedd279f80dd1e7067bd291ac7b8ac8315afbf1b (diff)
downloadrtems-bcad0aaee635d75be9c27b8792f0f69dedd03a57.tar.bz2
bsps/aarch64: add mnemonic for ICC_IGRPEN1_EL3
-rw-r--r--bsps/shared/dev/irq/arm-gicv3.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 113b840068..7a0d42b27b 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -112,6 +112,7 @@
/* AArch64 GICv3 registers are not named in GCC */
#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
+#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
#define ICC_PMR "S3_0_C4_C6_0, %0"
#define ICC_EOIR1 "S3_0_C12_C12_1, %0"
#define ICC_SRE "S3_0_C12_C12_5, %0"