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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-10-27 10:18:45 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-10-28 13:06:17 +0100 |
| commit | ac4f1718db41ef0550c9faf3188f3c7a54c9f024 (patch) | |
| tree | c858145d90dbf7e71296545fa5367f42301b24cb | |
| parent | bsp/qoriq: Map intercom area only if necessary (diff) | |
| download | rtems-ac4f1718db41ef0550c9faf3188f3c7a54c9f024.tar.bz2 | |
bsp/qoriq: Invalidate L1 cache on boot processor
| -rw-r--r-- | c/src/lib/libbsp/powerpc/qoriq/start/start.S | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/qoriq/start/start.S b/c/src/lib/libbsp/powerpc/qoriq/start/start.S index 4499850b5b..10daf32c8a 100644 --- a/c/src/lib/libbsp/powerpc/qoriq/start/start.S +++ b/c/src/lib/libbsp/powerpc/qoriq/start/start.S @@ -60,6 +60,26 @@ _start: bl bsp_fdt_copy #endif /* U_BOOT_USE_FDT */ + /* Invalidate L1 data cache */ + mfspr r3, FSL_EIS_L1CSR0 + ori r3, r3, FSL_EIS_L1CSR0_CFI + mtspr FSL_EIS_L1CSR0, r3 +1: + mfspr r3, FSL_EIS_L1CSR0 + andi. r3, r3, FSL_EIS_L1CSR0_CFI + bne 1b + isync + + /* Invalidate L1 instruction cache */ + mfspr r3, FSL_EIS_L1CSR1 + ori r3, r3, FSL_EIS_L1CSR1_ICFI + mtspr FSL_EIS_L1CSR1, r3 +1: + mfspr r3, FSL_EIS_L1CSR1 + andi. r3, r3, FSL_EIS_L1CSR1_ICFI + bne 1b + isync + /* Get start stack */ LWI START_STACK, start_stack_end |