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authorPavel Pisa <pisa@cmp.felk.cvut.cz>2016-07-03 09:30:20 +0200
committerPavel Pisa <pisa@cmp.felk.cvut.cz>2016-10-02 10:40:33 +0200
commit886b962e7b8c7c15f7d849925d7ca48482a05bca (patch)
tree3df5ec7dddbfb186c1f6af4cdfc1257689227346
parenteb3af275ead2a9f5972fa1a7b69a4017a8cdf606 (diff)
downloadrtems-886b962e7b8c7c15f7d849925d7ca48482a05bca.tar.bz2
bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.
Updates #2782 Updates #2783
-rw-r--r--c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 35c80026d4..e83b55cfa6 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
@@ -72,6 +72,10 @@ extern "C" {
/* These two defines also ensure that the rtems_cache_* functions have bodies */
#define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
+#if defined(__ARM_ARCH_7A__)
+/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
+#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS