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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-11-27 23:38:03 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-11-27 23:38:03 +0000
commit5e2dce08b0fe548f3b06b7f8eeba3f3d15fd4918 (patch)
treeebd57d33dd1db9e4b0b65b26261dbf05e7508bf2
parentdda8f5dc30edd49de25d2c1ab1ec0fbc5981c1dd (diff)
downloadrtems-5e2dce08b0fe548f3b06b7f8eeba3f3d15fd4918.tar.bz2
2001-11-27 Joel Sherrill <joel@OARcorp.com>,
This was tracked as PR39. * include/bsp.h, start/cpuboot.c, start/reset.S, startup/debugger, startup/linkcmds, startup/rom: Eliminated required definition of macros in the custom file for the BSP to compile. The ROM and ROM address and size settings are now linker script items.
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/ChangeLog8
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/include/bsp.h3
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/start/cpuboot.c16
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/start/reset.S9
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c16
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/startup/debugger6
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/startup/linkcmds5
-rw-r--r--c/src/lib/libbsp/m68k/ods68302/startup/rom5
-rw-r--r--make/ChangeLog8
9 files changed, 67 insertions, 9 deletions
diff --git a/c/src/lib/libbsp/m68k/ods68302/ChangeLog b/c/src/lib/libbsp/m68k/ods68302/ChangeLog
index 0c32d776e7..908411ff7a 100644
--- a/c/src/lib/libbsp/m68k/ods68302/ChangeLog
+++ b/c/src/lib/libbsp/m68k/ods68302/ChangeLog
@@ -1,3 +1,11 @@
+2001-11-27 Joel Sherrill <joel@OARcorp.com>,
+
+ This was tracked as PR39.
+ * include/bsp.h, start/cpuboot.c, start/reset.S, startup/debugger,
+ startup/linkcmds, startup/rom: Eliminated required definition of
+ macros in the custom file for the BSP to compile. The ROM and ROM
+ address and size settings are now linker script items.
+
2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Add autom4te.cache for autoconf > 2.52.
diff --git a/c/src/lib/libbsp/m68k/ods68302/include/bsp.h b/c/src/lib/libbsp/m68k/ods68302/include/bsp.h
index b80142aed8..8ece648cca 100644
--- a/c/src/lib/libbsp/m68k/ods68302/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/ods68302/include/bsp.h
@@ -38,6 +38,9 @@ extern "C" {
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
+#ifndef VARIANT
+#define VARIANT bare
+#endif
#if defined(VARIANT)
#define __bsp_cat(x, y) x ## y
diff --git a/c/src/lib/libbsp/m68k/ods68302/start/cpuboot.c b/c/src/lib/libbsp/m68k/ods68302/start/cpuboot.c
index fd8a4146de..95b205d6fc 100644
--- a/c/src/lib/libbsp/m68k/ods68302/start/cpuboot.c
+++ b/c/src/lib/libbsp/m68k/ods68302/start/cpuboot.c
@@ -41,14 +41,22 @@
Open the address, reset all registers
*/
+extern int ROM_SIZE, ROM_BASE;
+extern int RAM_SIZE, RAM_BASE;
+
+#define _ROM_SIZE ((unsigned int)&ROM_SIZE)
+#define _ROM_BASE ((unsigned int)&ROM_BASE)
+#define _RAM_SIZE ((unsigned int)&RAM_SIZE)
+#define _RAM_BASE ((unsigned int)&RAM_BASE)
+
void boot_phase_1()
{
M302_SCR = SCR_DEFAULT;
- WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
- WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
- WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
- WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
+ WRITE_OR(CSEL_ROM, _ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
+ WRITE_BR(CSEL_ROM, _RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
+ WRITE_OR(CSEL_RAM, _RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
+ WRITE_BR(CSEL_RAM, _ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#if defined(CSEL_1)
WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
diff --git a/c/src/lib/libbsp/m68k/ods68302/start/reset.S b/c/src/lib/libbsp/m68k/ods68302/start/reset.S
index 1ed00d2401..c31a7a4faf 100644
--- a/c/src/lib/libbsp/m68k/ods68302/start/reset.S
+++ b/c/src/lib/libbsp/m68k/ods68302/start/reset.S
@@ -357,7 +357,14 @@ start:
|
moveq #0,%d0
- move.w #(MC68302_BASE >> 12),%d0
+ | Joel: With the change of MC68302_BASE from a #define to a linker
+ | symbol, the following 4 instructions replace this one:
+ | move.w #(MC68302_BASE >> 12),%d0
+ move.l #MC68302_BASE,%d0
+ moveq.l #12,%d1
+ lsr.l %d1,%d0
+ and.l #0xFFFF,%d0
+
or.w #(MC68302_BAR_FC_CFC << 12),%d0
move.l #MC68302_BAR,%a0
move.w %d0,%a0@(0)
diff --git a/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c b/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
index fd8a4146de..95b205d6fc 100644
--- a/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
+++ b/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c
@@ -41,14 +41,22 @@
Open the address, reset all registers
*/
+extern int ROM_SIZE, ROM_BASE;
+extern int RAM_SIZE, RAM_BASE;
+
+#define _ROM_SIZE ((unsigned int)&ROM_SIZE)
+#define _ROM_BASE ((unsigned int)&ROM_BASE)
+#define _RAM_SIZE ((unsigned int)&RAM_SIZE)
+#define _RAM_BASE ((unsigned int)&RAM_BASE)
+
void boot_phase_1()
{
M302_SCR = SCR_DEFAULT;
- WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
- WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
- WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
- WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
+ WRITE_OR(CSEL_ROM, _ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
+ WRITE_BR(CSEL_ROM, _RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
+ WRITE_OR(CSEL_RAM, _RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
+ WRITE_BR(CSEL_RAM, _ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#if defined(CSEL_1)
WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
diff --git a/c/src/lib/libbsp/m68k/ods68302/startup/debugger b/c/src/lib/libbsp/m68k/ods68302/startup/debugger
index 6009868468..57d0c3c475 100644
--- a/c/src/lib/libbsp/m68k/ods68302/startup/debugger
+++ b/c/src/lib/libbsp/m68k/ods68302/startup/debugger
@@ -48,6 +48,12 @@ SECTIONS
}
}
+
+RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
+RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
+ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00010000;
+ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
+MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
m302 = MC68302_BASE;
_VBR = 0; /* location of the VBR table (in RAM) */
diff --git a/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds b/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
index d5c518e841..4f5d7cb043 100644
--- a/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
+++ b/c/src/lib/libbsp/m68k/ods68302/startup/linkcmds
@@ -170,6 +170,11 @@ SECTIONS
/* These must appear regardless of . */
}
+RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
+RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
+ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00C00000;
+ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
+MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
m302 = MC68302_BASE;
_VBR = ADDR(.vtable); /* location of the VBR table (in RAM) */
diff --git a/c/src/lib/libbsp/m68k/ods68302/startup/rom b/c/src/lib/libbsp/m68k/ods68302/startup/rom
index a8533e08b0..e74a2a0bd6 100644
--- a/c/src/lib/libbsp/m68k/ods68302/startup/rom
+++ b/c/src/lib/libbsp/m68k/ods68302/startup/rom
@@ -50,6 +50,11 @@ SECTIONS
}
}
+RAM_BASE = DEFINED(RAM_BASE) ? RAM_BASE : 0x00000000;
+RAM_SIZE = DEFINED(RAM_SIZE) ? RAM_SIZE : 0x00100000;
+ROM_BASE = DEFINED(ROM_BASE) ? ROM_BASE : 0x00C00000;
+ROM_SIZE = DEFINED(ROM_SIZE) ? ROM_SIZE : 0x00100000;
+MC68302_BASE = DEFINED(MC68302_BASE) ? MC68302_BASE : 0x00700000;
m302 = MC68302_BASE;
_VBR = 0; /* location of the VBR table (in RAM) */
diff --git a/make/ChangeLog b/make/ChangeLog
index 3106069a5d..5078ca3fe0 100644
--- a/make/ChangeLog
+++ b/make/ChangeLog
@@ -1,6 +1,14 @@
2001-11-27 Joel Sherrill <joel@OARcorp.com>,
This was tracked as PR39.
+ * include/bsp.h, start/cpuboot.c, start/reset.S, startup/debugger,
+ startup/linkcmds, startup/rom: Eliminated required definition of
+ macros in the custom file for the BSP to compile. The ROM and ROM
+ address and size settings are now linker script items.
+
+2001-11-27 Joel Sherrill <joel@OARcorp.com>,
+
+ This was tracked as PR39.
* custom/ods68302.cfg: Eliminated required definition of macros in this
file for the BSP to compile. The ROM and ROM address and size settings
are now linker script items.