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authorJoel Sherrill <joel.sherrill@oarcorp.com>2012-06-11 12:29:38 -0500
committerJoel Sherrill <joel.sherrill@oarcorp.com>2012-06-11 12:40:10 -0500
commit562cadfaa52c6237c780a4a8dcd585f12429d1f5 (patch)
tree7f4cee1e324abd33da245f8c1df7b6667e8ecedb
parentdea1050312e1ea7d00cdaa8c6f434e56fd7a1caa (diff)
downloadrtems-562cadfaa52c6237c780a4a8dcd585f12429d1f5.tar.bz2
i386/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Initialize
-rw-r--r--cpukit/score/cpu/i386/rtems/score/cpu.h16
1 files changed, 14 insertions, 2 deletions
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h
index 46d5c04fdb..a8d23f955c 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -39,6 +39,20 @@ extern "C" {
#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
/*
+ * Does the CPU follow the simple vectored interrupt model?
+ *
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
+ *
+ * PowerPC Specific Information:
+ *
+ * The PowerPC and x86 were the first to use the PIC interrupt model.
+ * They do not use the simple vectored interrupt model.
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
+
+/*
* i386 has an RTEMS allocated and managed interrupt stack.
*/
@@ -342,8 +356,6 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
* + set a particular level
*/
-#define _CPU_Initialize_vectors()
-
#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )