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author | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2018-05-25 08:21:18 +0200 |
---|---|---|
committer | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2018-05-30 08:45:57 +0200 |
commit | 4b3c8b82a9c2b0bb0219bb638521a22ec1cfd3aa (patch) | |
tree | 303b9a620ff8a608eaf60f0faa955d12b8779e4a | |
parent | build: Really fix RTEMS_ENABLE_RTEMSBSP() (diff) | |
download | rtems-4b3c8b82a9c2b0bb0219bb638521a22ec1cfd3aa.tar.bz2 |
bsp/atsam: Remove side effect from gmac functions.
Quite a number of GMAC_... functions had a side effect of enabling the
transmit and receive. During the initialization of the ethernet driver,
that lead to the situation that the receive has been already enabled
while the DMA isn't set up correctly. Therefore the DMA interpreted the
values at address 0 as an DMA descriptor. When a packet is received
during that time, the behaviour is quite undefined.
-rw-r--r-- | bsps/arm/atsam/contrib/libraries/libchip/source/gmac.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/bsps/arm/atsam/contrib/libraries/libchip/source/gmac.c b/bsps/arm/atsam/contrib/libraries/libchip/source/gmac.c index d7ce4f166d..9f498b2b45 100644 --- a/bsps/arm/atsam/contrib/libraries/libchip/source/gmac.c +++ b/bsps/arm/atsam/contrib/libraries/libchip/source/gmac.c @@ -99,7 +99,11 @@ uint16_t GMAC_PHYData(Gmac *pGmac) uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck) { uint32_t clock_dividor; +#ifndef __rtems__ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#else /* __rtems__ */ + assert((pGmac->GMAC_NCR & (GMAC_NCR_RXEN | GMAC_NCR_TXEN)) == 0); +#endif /* __rtems__ */ if (mck <= 20000000) { clock_dividor = GMAC_NCFGR_CLK_MCK_8; // MDC clock = MCK/8 @@ -117,7 +121,9 @@ uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck) } pGmac->GMAC_NCFGR = (pGmac->GMAC_NCFGR & (~GMAC_NCFGR_CLK_Msk)) | clock_dividor; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ return 1; } @@ -127,9 +133,15 @@ uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck) */ void GMAC_EnableMdio(Gmac *pGmac) { +#ifndef __rtems__ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#else /* __rtems__ */ + assert((pGmac->GMAC_NCR & (GMAC_NCR_RXEN | GMAC_NCR_TXEN)) == 0); +#endif /* __rtems__ */ pGmac->GMAC_NCR |= GMAC_NCR_MPE; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ } /** @@ -138,9 +150,15 @@ void GMAC_EnableMdio(Gmac *pGmac) */ void GMAC_DisableMdio(Gmac *pGmac) { +#ifndef __rtems__ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#else /* __rtems__ */ + assert((pGmac->GMAC_NCR & (GMAC_NCR_RXEN | GMAC_NCR_TXEN)) == 0); +#endif /* __rtems__ */ pGmac->GMAC_NCR &= ~GMAC_NCR_MPE; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ } /** @@ -149,9 +167,15 @@ void GMAC_DisableMdio(Gmac *pGmac) */ void GMAC_EnableMII(Gmac *pGmac) { +#ifndef __rtems__ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#else /* __rtems__ */ + assert((pGmac->GMAC_NCR & (GMAC_NCR_RXEN | GMAC_NCR_TXEN)) == 0); +#endif /* __rtems__ */ pGmac->GMAC_UR &= ~GMAC_UR_RMII; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ } /** @@ -160,10 +184,16 @@ void GMAC_EnableMII(Gmac *pGmac) */ void GMAC_EnableGMII(Gmac *pGmac) { +#ifndef __rtems__ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#else /* __rtems__ */ + assert((pGmac->GMAC_NCR & (GMAC_NCR_RXEN | GMAC_NCR_TXEN)) == 0); +#endif /* __rtems__ */ /* RGMII disable */ pGmac->GMAC_UR &= ~GMAC_UR_RMII; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ } #define GMAC_NCFGR_GBE (0x1u << 10) @@ -175,7 +205,11 @@ void GMAC_EnableGMII(Gmac *pGmac) */ void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed) { +#ifndef __rtems__ pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#else /* __rtems__ */ + assert((pGmac->GMAC_NCR & (GMAC_NCR_RXEN | GMAC_NCR_TXEN)) == 0); +#endif /* __rtems__ */ if (duplex == GMAC_DUPLEX_HALF) pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; @@ -193,7 +227,9 @@ void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed) /* RGMII enable */ pGmac->GMAC_UR = 0; pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ return; } @@ -216,7 +252,9 @@ void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex) ncfgr |= GMAC_NCFGR_FD; pGmac->GMAC_NCFGR = ncfgr; +#ifndef __rtems__ pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +#endif /* __rtems__ */ } /** |