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author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-10-30 19:28:46 +0000 |
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committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-10-30 19:28:46 +0000 |
commit | 3fcc78aef99863b91fa3c32f4ca72bfc6d03b056 (patch) | |
tree | 2b663cb4403cbc2e81c59007ebfb181fb4acee11 | |
parent | 2009-10-30 Glenn Humphrey <glenn.humphrey@oarcorp.com> (diff) | |
download | rtems-3fcc78aef99863b91fa3c32f4ca72bfc6d03b056.tar.bz2 |
move timebase access functions from cpukit to libcpu
-rw-r--r-- | c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog | 4 | ||||
-rw-r--r-- | c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c | 2 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/ChangeLog | 5 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c | 2 | ||||
-rw-r--r-- | c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h | 110 | ||||
-rw-r--r-- | cpukit/score/cpu/powerpc/ChangeLog | 5 | ||||
-rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpu.h | 106 |
7 files changed, 127 insertions, 107 deletions
diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog b/c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog index b2cf2997fa..f080c18408 100644 --- a/c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog +++ b/c/src/lib/libbsp/powerpc/tqm8xx/ChangeLog @@ -1,3 +1,7 @@ +2009-10-28 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * startup/bspstart.s: correct clock tick init + 2009-10-23 Ralf Corsépius <ralf.corsepius@rtems.org> * console/console.c: Include <rtems/error.h>. diff --git a/c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c index fa1c5e94a1..d701ed7291 100644 --- a/c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/tqm8xx/startup/bspstart.c @@ -173,7 +173,7 @@ void bsp_start( void) BSP_panic("Cannot determine BUS frequency\n"); } - bsp_clicks_per_usec = 0; /* force to zero to control + bsp_clicks_per_usec = BSP_bus_frequency/16; /* force to zero to control * PIT clock driver from EXTCLK */ bsp_timer_least_valid = 3; diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index 80ccbcff23..6a234984d4 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,8 @@ +2009-10-23 Thomas Doerfler <Thomas.Doerfler@imd-systems.de> + + * shared/include/powerpc-utility.h, mpc6xx/timer/timer.c: + moved timebase/decrementer access from cpukit to libcpu + 2009-10-23 Sebastian Huber <sebastian.huber@embedded-brains.de> * new-exceptions/e500_raw_exc_init.c, new-exceptions/raw_exception.c, diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c index 0a72553b1d..bc9ed1e7b2 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc6xx/timer/timer.c @@ -18,6 +18,8 @@ #include <assert.h> #include <rtems.h> #include <bsp.h> +#include <libcpu/powerpc-utility.h> + uint64_t Timer_driver_Start_time; diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h index ca615060fa..05d663e457 100644 --- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h +++ b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h @@ -242,6 +242,116 @@ static inline void ppc_external_exceptions_disable(uint32_t msr) RTEMS_COMPILER_MEMORY_BARRIER(); } +#ifndef ASM +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) +/* Wonderful bookE doesn't have mftb/mftbu; they only + * define the TBRU/TBRL SPRs so we use these. Luckily, + * we run in supervisory mode so that should work on + * all CPUs. In user mode we'd have a problem... + * 2007/11/30, T.S. + * + * OTOH, PSIM currently lacks support for reading + * SPRs 268/269. You need GDB patch sim/2376 to avoid + * a crash... + * OTOH, the MPC8xx do not allow to read the timebase registers via mfspr. + * we NEED a mftb to access the time base. + * 2009/10/30 Th. D. + */ +#define CPU_Get_timebase_low( _value ) \ + asm volatile( "mftb %0" : "=r" (_value) ) +#else +#define CPU_Get_timebase_low( _value ) \ + asm volatile( "mfspr %0,268" : "=r" (_value) ) +#endif + +/* Must be provided for rtems_bsp_delay to work */ +extern uint32_t bsp_clicks_per_usec; + +#define rtems_bsp_delay( _microseconds ) \ + do { \ + uint32_t start, ticks, now; \ + CPU_Get_timebase_low( start ) ; \ + ticks = (_microseconds) * bsp_clicks_per_usec; \ + do \ + CPU_Get_timebase_low( now ) ; \ + while (now - start < ticks); \ + } while (0) + +#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ + do { \ + uint32_t start, now; \ + CPU_Get_timebase_low( start ); \ + do \ + CPU_Get_timebase_low( now ); \ + while (now - start < (_cycles)); \ + } while (0) + +#endif /* ASM */ + +#ifndef ASM +/* + * Routines to access the decrementer register + */ + +#define PPC_Set_decrementer( _clicks ) \ + do { \ + asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ + } while (0) + +#define PPC_Get_decrementer( _clicks ) \ + asm volatile( "mfdec %0" : "=r" (_clicks) ) + +#endif /* ASM */ + +#ifndef ASM +/* + * Routines to access the time base register + */ + +static inline uint64_t PPC_Get_timebase_register( void ) +{ + uint32_t tbr_low; + uint32_t tbr_high; + uint32_t tbr_high_old; + uint64_t tbr; + + do { +#if defined(mpx8xx) || defined(mpc860) || defined(mpc821) +/* See comment above (CPU_Get_timebase_low) */ + asm volatile( "mftbu %0" : "=r" (tbr_high_old)); + asm volatile( "mftb %0" : "=r" (tbr_low)); + asm volatile( "mftbu %0" : "=r" (tbr_high)); +#else + asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); + asm volatile( "mfspr %0, 268" : "=r" (tbr_low)); + asm volatile( "mfspr %0, 269" : "=r" (tbr_high)); +#endif + } while ( tbr_high_old != tbr_high ); + + tbr = tbr_high; + tbr <<= 32; + tbr |= tbr_low; + return tbr; +} + +static inline void PPC_Set_timebase_register (uint64_t tbr) +{ + uint32_t tbr_low; + uint32_t tbr_high; + + tbr_low = (uint32_t) tbr; + tbr_high = (uint32_t) (tbr >> 32); + asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); + asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); + +} +#endif /* ASM */ + static inline uint32_t ppc_decrementer_register(void) { uint32_t dec; diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index 16192b2ab0..21257e6740 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,8 @@ +2009-10-21 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * score/cpu/powerpc/rtems/score/cpu.h: moved timebase/decrementer + access from cpukit to libcpu + 2009-10-21 Sebastian Huber <sebastian.huber@embedded-brains.de> * rtems/powerpc/registers.h: Added defines DEAR_BOOKE and DEAR_405. diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h index 0d006c4a9d..2ee1c255fa 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h @@ -402,112 +402,6 @@ static inline uint32_t CPU_swap_u32( #endif /* ASM */ -#ifndef ASM -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#if 0 -/* Wonderful bookE doesn't have mftb/mftbu; they only - * define the TBRU/TBRL SPRs so we use these. Luckily, - * we run in supervisory mode so that should work on - * all CPUs. In user mode we'd have a problem... - * 2007/11/30, T.S. - * - * OTOH, PSIM currently lacks support for reading - * SPRs 268/269. You need GDB patch sim/2376 to avoid - * a crash... - */ -#define CPU_Get_timebase_low( _value ) \ - asm volatile( "mftb %0" : "=r" (_value) ) -#else -#define CPU_Get_timebase_low( _value ) \ - asm volatile( "mfspr %0,268" : "=r" (_value) ) -#endif - -/* Must be provided for rtems_bsp_delay to work */ -extern uint32_t bsp_clicks_per_usec; - -#define rtems_bsp_delay( _microseconds ) \ - do { \ - uint32_t start, ticks, now; \ - CPU_Get_timebase_low( start ) ; \ - ticks = (_microseconds) * bsp_clicks_per_usec; \ - do \ - CPU_Get_timebase_low( now ) ; \ - while (now - start < ticks); \ - } while (0) - -#define rtems_bsp_delay_in_bus_cycles( _cycles ) \ - do { \ - uint32_t start, now; \ - CPU_Get_timebase_low( start ); \ - do \ - CPU_Get_timebase_low( now ); \ - while (now - start < (_cycles)); \ - } while (0) - -#endif /* ASM */ - -#ifndef ASM -/* - * Routines to access the decrementer register - */ - -#define PPC_Set_decrementer( _clicks ) \ - do { \ - asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ - } while (0) - -#define PPC_Get_decrementer( _clicks ) \ - asm volatile( "mfdec %0" : "=r" (_clicks) ) - -#endif /* ASM */ - -#ifndef ASM -/* - * Routines to access the time base register - */ - -static inline uint64_t PPC_Get_timebase_register( void ) -{ - uint32_t tbr_low; - uint32_t tbr_high; - uint32_t tbr_high_old; - uint64_t tbr; - - do { -#if 0 -/* See comment above (CPU_Get_timebase_low) */ - asm volatile( "mftbu %0" : "=r" (tbr_high_old)); - asm volatile( "mftb %0" : "=r" (tbr_low)); - asm volatile( "mftbu %0" : "=r" (tbr_high)); -#else - asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); - asm volatile( "mfspr %0, 268" : "=r" (tbr_low)); - asm volatile( "mfspr %0, 269" : "=r" (tbr_high)); -#endif - } while ( tbr_high_old != tbr_high ); - - tbr = tbr_high; - tbr <<= 32; - tbr |= tbr_low; - return tbr; -} - -static inline void PPC_Set_timebase_register (uint64_t tbr) -{ - uint32_t tbr_low; - uint32_t tbr_high; - - tbr_low = (uint32_t) tbr; - tbr_high = (uint32_t) (tbr >> 32); - asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); - asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); - -} -#endif /* ASM */ #ifndef ASM /* Context handler macros */ |