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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-11-01 21:55:52 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-11-01 21:55:52 +0000
commit18a1f5a9f9970bf6ea23139a9f9118e6b2d0d262 (patch)
tree26a5504253643051acc57d68d3f7cdec9daa3ae9
parent3d1c0aa2d7f5375e42d780799c2e173ff72ec446 (diff)
downloadrtems-18a1f5a9f9970bf6ea23139a9f9118e6b2d0d262.tar.bz2
2002-11-01 Joel Sherrill <joel@OARcorp.com>
* cpu.c: Currently only the mpc8260 BSP supports interrupt nesting. NOTE: These needs to be generalized as the patch is applied to other BSPs.
-rw-r--r--c/src/lib/libbsp/powerpc/support/new_exception_processing/ChangeLog6
-rw-r--r--c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c8
-rw-r--r--c/src/lib/libcpu/powerpc/new-exceptions/ChangeLog6
-rw-r--r--c/src/lib/libcpu/powerpc/new-exceptions/cpu.c8
4 files changed, 28 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/powerpc/support/new_exception_processing/ChangeLog b/c/src/lib/libbsp/powerpc/support/new_exception_processing/ChangeLog
index 3cd28ea5af..fedc3b9b4a 100644
--- a/c/src/lib/libbsp/powerpc/support/new_exception_processing/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/support/new_exception_processing/ChangeLog
@@ -1,3 +1,9 @@
+2002-11-01 Joel Sherrill <joel@OARcorp.com>
+
+ * cpu.c: Currently only the mpc8260 BSP supports interrupt nesting.
+ NOTE: These needs to be generalized as the patch is applied to other
+ BSPs.
+
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Reformat.
diff --git a/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c b/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c
index 01c5a31e37..32589213ae 100644
--- a/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c
+++ b/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c
@@ -130,11 +130,19 @@ void _CPU_Install_interrupt_stack( void )
boolean _ISR_Is_in_progress( void )
{
+ /*
+ * Until the patch on PR288 is in all new exception BSPs, this is
+ * the safest thing to do.
+ */
+#ifdef mpc8260
+ return (_ISR_Nest_level != 0);
+#else
register unsigned int isr_nesting_level;
/*
* Move from special purpose register 0 (mfspr SPRG0, r3)
*/
asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level));
return isr_nesting_level;
+#endif
}
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/ChangeLog b/c/src/lib/libcpu/powerpc/new-exceptions/ChangeLog
index 3cd28ea5af..fedc3b9b4a 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/ChangeLog
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/ChangeLog
@@ -1,3 +1,9 @@
+2002-11-01 Joel Sherrill <joel@OARcorp.com>
+
+ * cpu.c: Currently only the mpc8260 BSP supports interrupt nesting.
+ NOTE: These needs to be generalized as the patch is applied to other
+ BSPs.
+
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Reformat.
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
index 01c5a31e37..32589213ae 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
@@ -130,11 +130,19 @@ void _CPU_Install_interrupt_stack( void )
boolean _ISR_Is_in_progress( void )
{
+ /*
+ * Until the patch on PR288 is in all new exception BSPs, this is
+ * the safest thing to do.
+ */
+#ifdef mpc8260
+ return (_ISR_Nest_level != 0);
+#else
register unsigned int isr_nesting_level;
/*
* Move from special purpose register 0 (mfspr SPRG0, r3)
*/
asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level));
return isr_nesting_level;
+#endif
}