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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-02-04 20:05:30 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-02-04 20:05:30 +0000
commit0bc5329df83cb538a64604cd4f4e48b4c97e05c8 (patch)
tree60297d25a2da6e63833ff906d3e9608ed1b36fa4
parent96ecd879f86e6a189ee1acd29622453e4d303a13 (diff)
downloadrtems-0bc5329df83cb538a64604cd4f4e48b4c97e05c8.tar.bz2
2001-02-04 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: IDLE task should not be FP. This was a mistake in the previous patch that has now been confirmed.
-rw-r--r--c/src/exec/score/cpu/mips/ChangeLog5
-rw-r--r--c/src/exec/score/cpu/mips/rtems/score/cpu.h2
-rw-r--r--cpukit/score/cpu/mips/ChangeLog5
-rw-r--r--cpukit/score/cpu/mips/rtems/score/cpu.h2
4 files changed, 12 insertions, 2 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog
index ff63919afb..7c88656444 100644
--- a/c/src/exec/score/cpu/mips/ChangeLog
+++ b/c/src/exec/score/cpu/mips/ChangeLog
@@ -1,3 +1,8 @@
+2001-02-04 Joel Sherrill <joel@OARcorp.com>
+
+ * rtems/score/cpu.h: IDLE task should not be FP. This was a mistake
+ in the previous patch that has now been confirmed.
+
2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu.c: Enhancements and fixes for modifying the SR when changing
diff --git a/c/src/exec/score/cpu/mips/rtems/score/cpu.h b/c/src/exec/score/cpu/mips/rtems/score/cpu.h
index 1ece7ebbe5..1f013d4121 100644
--- a/c/src/exec/score/cpu/mips/rtems/score/cpu.h
+++ b/c/src/exec/score/cpu/mips/rtems/score/cpu.h
@@ -207,7 +207,7 @@ extern "C" {
* must be saved as part of the preemption.
*/
-#define CPU_IDLE_TASK_IS_FP TRUE
+#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index ff63919afb..7c88656444 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,8 @@
+2001-02-04 Joel Sherrill <joel@OARcorp.com>
+
+ * rtems/score/cpu.h: IDLE task should not be FP. This was a mistake
+ in the previous patch that has now been confirmed.
+
2001-02-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu.c: Enhancements and fixes for modifying the SR when changing
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index 1ece7ebbe5..1f013d4121 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -207,7 +207,7 @@ extern "C" {
* must be saved as part of the preemption.
*/
-#define CPU_IDLE_TASK_IS_FP TRUE
+#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred