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authorRalf Corsepius <ralf.corsepius@rtems.org>2011-02-11 09:13:08 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2011-02-11 09:13:08 +0000
commit01850cde141bac3b4b4e6337d0515b84f8fb2636 (patch)
treeb32d420e3d38d07f00b6830789bc7c478df0977f
parent566fa34827ac7c6438926e3c36797c41d7c7c90f (diff)
downloadrtems-01850cde141bac3b4b4e6337d0515b84f8fb2636.tar.bz2
2011-02-11 Ralf Cors├ępius <ralf.corsepius@rtems.org>
* cpu.c, rtems/asm.h, rtems/score/cpu.h: Use "__asm__" instead of "asm" for improved c99-compliance.
-rw-r--r--cpukit/score/cpu/h8300/ChangeLog5
-rw-r--r--cpukit/score/cpu/h8300/cpu.c4
-rw-r--r--cpukit/score/cpu/h8300/rtems/asm.h2
-rw-r--r--cpukit/score/cpu/h8300/rtems/score/cpu.h16
4 files changed, 16 insertions, 11 deletions
diff --git a/cpukit/score/cpu/h8300/ChangeLog b/cpukit/score/cpu/h8300/ChangeLog
index 85182b48c2..624846949f 100644
--- a/cpukit/score/cpu/h8300/ChangeLog
+++ b/cpukit/score/cpu/h8300/ChangeLog
@@ -1,3 +1,8 @@
+2011-02-11 Ralf Cors├ępius <ralf.corsepius@rtems.org>
+
+ * cpu.c, rtems/asm.h, rtems/score/cpu.h:
+ Use "__asm__" instead of "asm" for improved c99-compliance.
+
2010-10-21 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
diff --git a/cpukit/score/cpu/h8300/cpu.c b/cpukit/score/cpu/h8300/cpu.c
index 98ebf71563..1c82ee4880 100644
--- a/cpukit/score/cpu/h8300/cpu.c
+++ b/cpukit/score/cpu/h8300/cpu.c
@@ -53,7 +53,7 @@ uint32_t _CPU_ISR_Get_level( void )
#if defined(__H8300__)
#warning "How do we get ccr on base CPU models"
#else
- asm volatile ( "stc ccr, %0" : "=m" (_ccr) : );
+ __asm__ volatile ( "stc ccr, %0" : "=m" (_ccr) : );
#endif
if ( _ccr & 0x80 )
@@ -152,7 +152,7 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
for( ; ; )
IDLE_Monitor();
- /*asm(" sleep \n"); */
+ /* __asm__ (" sleep \n"); */
/* insert your "halt" instruction here */ ;
}
#endif
diff --git a/cpukit/score/cpu/h8300/rtems/asm.h b/cpukit/score/cpu/h8300/rtems/asm.h
index 02919d8241..4322bf6ec0 100644
--- a/cpukit/score/cpu/h8300/rtems/asm.h
+++ b/cpukit/score/cpu/h8300/rtems/asm.h
@@ -98,7 +98,7 @@
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
-#define BEGIN_CODE asm ( ".text
+#define BEGIN_CODE __asm__ ( ".text
#define END_CODE ");
#define BEGIN_DATA
#define END_DATA
diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h
index 1a5a66afa6..cf8a880f32 100644
--- a/cpukit/score/cpu/h8300/rtems/score/cpu.h
+++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h
@@ -583,7 +583,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
- asm volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \
+ __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \
} while (0)
@@ -596,7 +596,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
- asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \
+ __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \
} while (0)
@@ -610,7 +610,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
- asm volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \
+ __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \
} while (0)
/* end of ISR handler macros */
@@ -630,7 +630,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Disable( _isr_cookie ) \
do { \
unsigned char __ccr; \
- asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \
+ __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \
: "=m" (__ccr) /* : "0" (__ccr) */ ); \
(_isr_cookie) = __ccr; \
} while (0)
@@ -653,7 +653,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Enable( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
- asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
+ __asm__ volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Enable( _isr_cookie )
@@ -674,7 +674,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Flash( _isr_cookie ) \
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
- asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
+ __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
} while (0)
#else
#define _CPU_ISR_Flash( _isr_cookie )
@@ -700,8 +700,8 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Set_level( _new_level ) \
{ \
- if ( _new_level ) asm volatile ( "orc #0x80,ccr\n" ); \
- else asm volatile ( "andc #0x7f,ccr\n" ); \
+ if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \
+ else __asm__ volatile ( "andc #0x7f,ccr\n" ); \
}
#ifndef ASM