SIS - SPARC/RISCV instruction simulator 2.30, copyright Jiri Gaisler 2020
Bug-reports to jiri@gaisler.se
GR740/LEON4 emulation enabled, 4 cpus online, delta 50 clocks
Loaded build/sparc/gr740/testsuites/tmtests/tmtimer01.exe, entry 0x00000000
*** BEGIN OF TEST TMTIMER 1 ***
*** TEST VERSION: 6.0.0.76c91ee7793fc70b92e2f87e601c3fdc2d2b7f3f
*** TEST STATE: EXPECTED_PASS
*** TEST BUILD: RTEMS_SMP
*** TEST TOOLS: 13.2.0 20230727 (RTEMS 6, RSB d3d738c35a71ca05f675b188539225099401ac79, Newlib a021448)
*** BEGIN OF JSON DATA ***
{
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}
]
}
*** END OF JSON DATA ***
*** END OF TEST TMTIMER 1 ***
cpu 0 in error mode (tt = 0x80)
522750200 00009b40: 91d02000 ta 0x0
