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The MVME2100 is a Motorola VMEbus board which is similar to the other
Motorola PowerPC boards supported by this BSP. But it does not support
the Motorola CPU Configuration Register. This makes it impossible to
dynamically probe and determine that you are executing on this board
variant. So this BSP variant must be explicitly built to only support
the MVME2100. The complete list of differences found so far is:
* No CPU Configuration Register
* one COM port
* COM port is on PCI IRQ not ISA IRQ
* limited on RAM (32 or 64 MB)
* uses the EPIC interrupt controller on the MPC8240
* does not have an ISA bus but has an ISA I/O address space
* cannot set DBAT2 in bspstart like other variants because
there are PCI/ISA Interrupt Acknowledge registers at this space
This BSP may have left some PCI memory uncovered
* PPCBug starts programs with vectors still in ROM
Supported Features:
- Interrupt driven console using termios
- Network device driver
- Real-Time Clock driver
- Clock Tick Device Driver
Things to address:
- Does not return to monitor
- Level 1 cache is disabled for now
- Check on trying to read CPU Configuration Register for CHRP/Prep for PCI
and report a failure if in the wrong mode. May be able to set the model
but it may be hard to test if we break PPCBug.
- Use NVRAM for network configuration information
BSP Features Not Implemented:
- VMEbus mapped in but untested
- OpenPIC features not required for BSP are not supported
Memory Map
==========
BAT Mapping
ffff ffff |------------------------------------| ----- ffff ffff
| ROM/FLASH Bank 0 | |
fff0 0000 |------------------------------------| |
| System I/O | |
ffe0 0000 |------------------------------------| |
| Replicated ROM/FLASH Bank 0 | |
| Replicated System I/O | |
ff80 0000 |------------------------------------| |
| ROM/FLASH Bank 1 | DBAT3
ff00 0000 |------------------------------------| - Supervisor R/W
| PCI Interrupt Acknowledge | - Cache Inhibited
fef0 0000 |------------------------------------| - Guarded
| PCI Configuration Data Register | |
fee0 0000 |------------------------------------| |
| PCI Configuration Address Register | |
fec0 0000 |------------------------------------| |
| PCI I/O Space | |
fe80 0000 |------------------------------------| |
| PCI/ISA I/O Space | |
fe00 0000 |------------------------------------| |
| PCI/ISA Memory Space | |
fd00 0000 |------------------------------------| |
| | |
| xxxxxxxxxxxxxx| ----- f000 0000
| x not mapped | |
| xxxxxxxxxxxxxx| ----- a000 0000
| | |
| | |
| | DBAT0
| | - Supervisor R/W
| | - Cache Inhibited
| | - Guarded
| | |
| | |
| | ----- 9000 0000
| | |
| | |
| PCI Memory Space | DBAT2
| | - Supervisor R/W
| | - Cache Inhibited
| | - Guarded
| | |
| | |
| | |
8000 0000 |------------------------------------| ----- 8000 0000
| x |
| x not mapped |
| Reserved xxxxxxxxxxxxxx| ----- 1000 0000
| | |
| | |
0200 0000 |------------------------------------| |
| | |
| | |
| | |
| | |
| DRAM (32MB) | DBAT1/IBAT1
| | - Supervisor R/W
| | |
| | |
| | |
| | |
0000 0000 |------------------------------------| ----- 0000 0000
TTCP Performance on First Day Run
=================================
Fedora Core 1 on (according to /proc/cpuinfo) a 300 Mhz P3 using Netgear
10/100 CardBus NIC on a dedicated 10BaseT LAN.
ON MVME2100: ttcp -t -s 192.168.2.107
REPORTED ON MVME2100:
ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5001 tcp -> 192.168.2.107
ttcp-t: socket
ttcp-t: connect
ttcp-t: 16777216 bytes in 20.80 real seconds = 787.69 KB/sec +++
ttcp-t: 2048 I/O calls, msec/call = 10.40, calls/sec = 98.46
ttcp-t: 0.0user 20.8sys 0:20real 100% 0i+0d 0maxrss 0+0pf 0+0csw
ON MVME2100: ttcp -t -s 192.168.2.107
REPORTED ON MVME2100:
ttcp -r -s
ttcp-r: buflen=8192, nbuf=2048, align=16384/0, port=5001 tcp
ttcp-r: socket
ttcp-r: accept from 192.168.2.107
ttcp-r: 16777216 bytes in 15.41 real seconds = 1063.21 KB/sec +++
ttcp-r: 11588 I/O calls, msec/call = 1.36, calls/sec = 751.98
ttcp-r: 0.0user 15.4sys 0:15real 100% 0i+0d 0maxrss 0+0pf 0+0csw
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