;
; $Id$
;
;#{
;# SCCS INFORMATION:
;# SID = @(#)sa29200.lnk 4.1; DLU=95/09/14-11:05:57
;# Q = @(#) Copyright (C) 1995 Advanced Micro Devices, Inc.
;# Module Type = @(#) OSBOOT/DBG_CORE absolute liker file (AMD-EPD-29K, AMIR)
;# SCCS Path = %P\%
;# SCCS File = %F\%
;# FileName = sa29200.lnk
;# SCCS ID = 4.1
;# Date Update = 14 Sep 1995, (DLU=95/09/14-11:05:57)
;# Date Extract = 12 Oct 1995, (DLE=95/10/12-16:27:31)
;#}
; @(#)sa29200.lnk 3.6 94/08/22 11:58:54, Srini, AMD.
; This is the linker command file used to bind the inrementally linked
; osboot.o module to a memory map. This also defines some link-time constants
; used in the code. These constants are genral for all 29K family members.
; You only need to customize, if necessary, the definitions that affect
; your target processor, and leave the rest alone.
; The default values in this file are for binding osboot.o for use with
; SA29200 stand-alone board with the -29200/-29205 option.
;
; Order the code segments according to the memory map structure.
; The defaul OSBOOT has only .text and .bss sections. You need to ORDER
; other sections of your applications that are not included below.
; We use separate ORDER statements below to distinguish the two memory
; regions used. The text section is bound to ROM memory region, and the
; data region to RAM memory space.
; MAKE SURE to order the BSS section at the very end. This is because the
; BSS section size could get adjusted after linking with raminit.o (produced
; by romcoff utility) or other initialization routines. This change in size
; could affect the offsets used by the program to refer to the remaining data
; sections that follow BSS.
ALIGN ProcInit=16
ORDER Reset=0x0
ORDER ProcInit,OsbText,.text,!text
ORDER .lit,!lit
ORDER vectable=0x40000000
ORDER msg_data=0x40000400
ORDER .data,!data
ORDER OsbBss,dbg_030,dbg_bss,cfg_bss,.bss,!bss
ORDER HeapBase
ORDER .comment
; For Stand-Alone application out of ROM use the ORDER statements below:
; For Stand-Alone application out of RAM use the ORDER statement below:
;ORDER Reset=0x40010000,ProcInit,OsbText,.text,!text,.lit,!lit,.data,!data,msg_data,dbg_dat,.bss,!bss,HeapBase,.comment
;
; definitions of link time constants used in code.
;
; Definition of the initial value of CPS register.
; The value below is for an Am29200 processor. It sets TU, SM,DI, DA,IM fields
; bits in the register. You may modify it to suit your target environment.
; Like, changing the IM field for instance. IM is 0x11 by default enabling
; all INTR[0-3] lines.
;public _init_CPS=0x87F
public _init_CPS=0x20813
;public _init_CPS=0x2081F
;public _init_CPS=0x081F
; Define the memory map in general values. The code - except for simulators -
; configures the external RAM at run-time and updates the DMemSize value.
; DMemStart and DMemSize are the most important values below. DMemStart is
; used to initialize the vector base address register (VAB). And DMemSize
; is used to find the highest addressable data memory to place the register
; and memory stacks. Remember, DMemSize is configured at run-time for hardware
; targets and updated.
public VectorBaseAddress=0x40000000
public IMemStart=0x0000000
public IMemSize=0xfffff
public DMemStart=0x40000000
#public DMemStart=0x100000
public DMemSize=0xfffff
#public DMemSize=0x17ffff
#public DMemSize=0x3fffffff
public RMemStart=0x0
public RMemSize=0xfffff
public EnableDRAMSizing=1
;
; For the 29K Microcontrollers, you need to define the ROM Control register
; value (RMCT_VALUE), the ROM Configuration register value (RMCF_VALUE), and
; the DRAM Control register value (DRCT_VALUE) based on DMemSize specified
; above. This could be overwritten in software targets such as the simulator.
; ROM and RAM Control registers. ROM COnfiguration. (not valid for Am2900X,
; Am29050, and Am2903X processors)
; The DRAM REFRATE value (in DRCT) must be specified here. To disable
; DRAM refreshing (on a system with no DRAM), set REFRATE field in DRCT
; to zero. Otherwise, set it to the desired frequency. The default is 0xFF
; The default values in this file are for Am2920X processors.
;public RMCT_VALUE=0x03030303
;public DRCT_VALUE=0x888800FF
;public RMCF_VALUE=0x00f8f8f8
;
public RMCT_VALUE=0x4a424300
public DRCT_VALUE=0xccc000f0
public RMCF_VALUE=0x011121ff
;
;
; Execute trap handlers from ROM? If your trap handlers are in ROM space,
; then set _TRAPINROM to TWO (0x2). It is used to modify the tarp vector
; address installed to set the R bit when fetched. If the trap handlers in
; ROM or if there is no ROM-space (no RE bit in CPS), set _TRAPINROM to ZERO.
; The default in this file is for SA29200 board and _TRAPINROM is set to ZERO.
public _TRAPINROM=0
;
; Define the processor clock frequencies. These values are used by the HIF
; kernel to provide some HIF services.
public TicksPerMillisecond=16000
public ClockFrequency=16000000
;
; There are some C functions which are not leaf functions. However, they are
; no expected to spill or fill registers. We ensure that by setting up a
; pseudo register stack before calling those functions. The code generated
; for those functions however do have the prologue and epilogue which refer
; to the symbols V_SPILL and V_FILL. The linker does not know about these
; symbols. So we define it here so that it does not complain.
; If you use the hc29 compiler driver to link the objects it will warn that
; the definitions here are already internally defined. You
; can use hc29 with -nocrt0 option to do the linking for linear memory spaces.
; public V_SPILL=64
; public V_FILL=65
;
; Set the UART debug/monitor port serial communications baud rate.
;
public UCLK=32000000
; INITBAUD defines the cold start baud rate. This is the baud rate
; the monitor would use when powered up. This can be overridden by
; defining BAUDRATE on the assembler/compiler command line.
public INITBAUD=9600
;
; Is there a SCC 8530 on the target?
; If there is an 8530 SC on target, define the symbols below appropriately.
; The routines in scc8530.s use these values to access the registers of
; SCC and program it. The default values are for EZ030 target.
; Baudrate can be specified on the command-line to override the default
; baud rate defined in scc8530.s.
; scc channel A control
;public SCC8530_CHA_CONTROL=0xC0000007
; scc channel B control
;public SCC8530_CHB_CONTROL=0xC0000003
; scc channel A data
;public SCC8530_CHA_DATA=0xC000000F
; scc channel B data
;public SCC8530_CHB_DATA=0xC000000B
; scc baud clock generator
;public SCC8530_BAUD_CLK_ENBL=3
