/*
* HP PA-RISC Dependent Source
*
* COPYRIGHT (c) 1994 by Division Incorporated
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Division Incorporated not be
* used in advertising or publicity pertaining to distribution
* of the software without specific, written prior permission.
* Division Incorporated makes no representations about the
* suitability of this software for any purpose.
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/isr.h>
void hppa_external_interrupt_initialize(void);
void hppa_external_interrupt_enable(unsigned32);
void hppa_external_interrupt_disable(unsigned32);
void hppa_external_interrupt(unsigned32, CPU_Interrupt_frame *);
void hppa_cpu_halt(unsigned32);
/*
* The first level interrupt handler for first 32 interrupts/traps.
* Indexed by vector; generally each entry is _Generic_ISR_Handler.
* Some TLB traps may have their own first level handler.
*/
extern void _Generic_ISR_Handler(void);
unsigned32 HPPA_first_level_interrupt_handler[HPPA_INTERNAL_INTERRUPTS];
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS:
* cpu_table - CPU table to initialize
* thread_dispatch - address of disptaching routine
*
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch) /* ignored on this CPU */
)
{
register unsigned8 *fp_context;
unsigned32 iva;
unsigned32 iva_table;
int i;
extern void IVA_Table(void);
/*
* XXX; need to setup fpsr smarter perhaps
*/
fp_context = (unsigned8*) &_CPU_Null_fp_context;
for (i=0 ; i<sizeof(Context_Control_fp); i++)
*fp_context++ = 0;
/*
* Set _CPU_Default_gr27 here so it will hopefully be the correct
* global data pointer for the entire system.
*/
asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): );
/*
* Init the first level interrupt handlers
*/
for (i=0; i <= HPPA_INTERNAL_INTERRUPTS; i++)
HPPA_first_level_interrupt_handler[i] = (unsigned32) _Generic_ISR_Handler;
/*
* Init the 2nd level interrupt handlers
*/
for (i=0; i <= CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
_ISR_Vector_table[i] = (ISR_Handler_entry) hppa_cpu_halt;
/*
* Stabilize the interrupt stuff
*/
(void) hppa_external_interrupt_initialize();
/*
* Set the IVA to point to physical address of the IVA_Table
*/
iva_table = (unsigned32) IVA_Table;
#if defined(hppa1_1)
/*
* HACK: (from PA72000 TRM, page 4-19)
* "The hardware TLB miss handler will never attempt to service
* a non-access TLB miss or a TLB protection violation. It
* will only attempt to service TLB accesses that would cause
* Trap Numbers 6 (Instruction TLB miss) and 15 (Data TLB miss)."
*
* The LPA instruction is used to translate a virtual address to
* a physical address, however, if the requested virtual address
* is not currently resident in the TLB, the hardware TLB miss
* handler will NOT insert it. In this situation Trap Number
* #17 is invoked (Non-access Data TLB miss fault).
*
* To work around this, a dummy data access is first performed
* to the virtual address prior to the LPA. The dummy access
* causes the TLB entry to be inserted (if not already present)
* and then the following LPA instruction will not generate
* a non-access data TLB miss fault.
*
* It is unclear whether or not this behaves the same way for
* the PA8000.
*
*/
iva = *(volatile unsigned32 *)iva_table; /* dummy access */
#endif
HPPA_ASM_LPA(0, iva_table, iva);
set_iva(iva);
_CPU_Table = *cpu_table;
}
/*PAGE
*
* _CPU_ISR_Get_level
*/
unsigned32 _CPU_ISR_Get_level(void)
{
int level;
HPPA_ASM_SSM(0, level); /* change no bits; just get copy */
if (level & HPPA_PSW_I)
return 0;
return 1;
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/*
* This is unsupported.
*/
_CPU_Fatal_halt( 0xdeaddead );
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*/
/*
* HPPA has 8w for each vector instead of an address to jump to.
* We put the actual ISR address in '_ISR_vector_table'. This will
* be pulled by the code in the vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
*old_handler = _ISR_Vector_table[vector];
_ISR_Vector_table[vector] = new_handler;
if (vector >= HPPA_INTERRUPT_EXTERNAL_BASE)
{
unsigned32 external_vector;
external_vector = vector - HPPA_INTERRUPT_EXTERNAL_BASE;
if (new_handler)
hppa_external_interrupt_enable(external_vector);
else
/* XXX this can never happen due to _ISR_Is_valid_user_handler */
hppa_external_interrupt_disable(external_vector);
}
}
/*
* Support for external and spurious interrupts on HPPA
*
* TODO:
* Count interrupts
* make sure interrupts disabled properly
*/
#define DISMISS(mask) set_eirr(mask)
#define DISABLE(mask) set_eiem(get_eiem() & ~(mask))
#define ENABLE(mask) set_eiem(get_eiem() | (mask))
#define VECTOR_TO_MASK(v) (1 << (31 - (v)))
/*
* Init the external interrupt scheme
* called by bsp_start()
*/
void
hppa_external_interrupt_initialize(void)
{
proc_ptr ignore;
/* mark them all unused */
DISABLE(~0);
DISMISS(~0);
/* install the external interrupt handler */
_CPU_ISR_install_vector(
HPPA_INTERRUPT_EXTERNAL_INTERRUPT,
(proc_ptr)hppa_external_interrupt, &ignore
);
}
/*
* Enable a specific external interrupt
*/
void
hppa_external_interrupt_enable(unsigned32 v)
{
unsigned32 isrlevel;
_CPU_ISR_Disable(isrlevel);
ENABLE(VECTOR_TO_MASK(v));
_CPU_ISR_Enable(isrlevel);
}
/*
* Does not clear or otherwise affect any pending requests
*/
void
hppa_external_interrupt_disable(unsigned32 v)
{
unsigned32 isrlevel;
_CPU_ISR_Disable(isrlevel);
DISABLE(VECTOR_TO_MASK(v));
_CPU_ISR_Enable(isrlevel);
}
void
hppa_external_interrupt_spurious_handler(unsigned32 vector,
CPU_Interrupt_frame *iframe)
{
/* XXX should not be printing :)
printf("spurious external interrupt: %d at pc 0x%x; disabling\n",
vector, iframe->Interrupt.pcoqfront);
*/
}
void
hppa_external_interrupt_report_spurious(unsigned32 spurious_mask,
CPU_Interrupt_frame *iframe)
{
int v;
for (v=0; v < HPPA_EXTERNAL_INTERRUPTS; v++)
if (VECTOR_TO_MASK(v) & spurious_mask)
{
DISMISS(VECTOR_TO_MASK(v));
DISABLE(VECTOR_TO_MASK(v));
hppa_external_interrupt_spurious_handler(v, iframe);
}
DISMISS(spurious_mask);
}
/*
* External interrupt handler.
* This is installed as cpu interrupt handler for
* HPPA_INTERRUPT_EXTERNAL_INTERRUPT. It vectors out to
* specific external interrupt handlers.
*/
void
hppa_external_interrupt(unsigned32 vector,
CPU_Interrupt_frame *iframe)
{
unsigned32 mask;
unsigned32 *vp, *max_vp;
unsigned32 external_vector;
unsigned32 global_vector;
hppa_rtems_isr_entry handler;
max_vp = &_CPU_Table.external_interrupt[_CPU_Table.external_interrupts];
while ( (mask = (get_eirr() & get_eiem())) )
{
for (vp = _CPU_Table.external_interrupt; (vp < max_vp) && mask; vp++)
{
unsigned32 m;
external_vector = *vp;
global_vector = external_vector + HPPA_INTERRUPT_EXTERNAL_BASE;
m = VECTOR_TO_MASK(external_vector);
handler = (hppa_rtems_isr_entry) _ISR_Vector_table[global_vector];
if ((m & mask) && handler)
{
DISMISS(m);
mask &= ~m;
handler(global_vector, iframe);
}
}
if (mask != 0) {
if ( _CPU_Table.spurious_handler )
{
handler = (hppa_rtems_isr_entry) _CPU_Table.spurious_handler;
handler(mask, iframe);
}
else
hppa_external_interrupt_report_spurious(mask, iframe);
}
}
}
/*
* Halt the system.
* Called by the _CPU_Fatal_halt macro
*
* XXX
* Later on, this will allow us to return to the prom.
* For now, we just ignore 'type_of_halt'
*/
void
hppa_cpu_halt(unsigned32 the_error)
{
unsigned32 isrlevel;
_CPU_ISR_Disable(isrlevel);
HPPA_ASM_LABEL("_hppa_cpu_halt");
HPPA_ASM_BREAK(1, 0);
}
