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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-23 07:13:50 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-23 15:00:13 +0200 |
| commit | d33c1519f2502db9ff6c9ce87ed9aba7d6c8467f (patch) | |
| tree | ca85744ebf18c323c3bf56d34655e2c648944c39 /rtems/config/5/rtems-riscv.bset | |
| parent | 5: Update Newlib (diff) | |
| download | rtems-source-builder-d33c1519f2502db9ff6c9ce87ed9aba7d6c8467f.tar.bz2 | |
5: Merge riscv32 and riscv64 into riscv
After several upstream updates in Binutils, GCC, Newlib, and GDB it is
now possible to use a common riscv tool chain for the 32-bit and 64-bit
RISC-V.
Update GDB to ce73f310150418a9a1625ab60a527d959096a9e2 Git commit.
Close #3452.
Diffstat (limited to 'rtems/config/5/rtems-riscv.bset')
| -rw-r--r-- | rtems/config/5/rtems-riscv.bset | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/rtems/config/5/rtems-riscv.bset b/rtems/config/5/rtems-riscv.bset new file mode 100644 index 0000000..1622fee --- /dev/null +++ b/rtems/config/5/rtems-riscv.bset @@ -0,0 +1,17 @@ +# +# RISC-V architecture +# +%define release 1 +%define rtems_arch riscv +%define with_libgomp + +%include rtems-base.bset + +5/rtems-autotools + +devel/expat-2.1.0-1 +tools/rtems-binutils-2.31.1 +tools/rtems-gcc-62cab5089882f91865e9040672f7932ae8d09db1-newlib-3.0.0.20180720 +tools/rtems-gdb-ce73f310150418a9a1625ab60a527d959096a9e2 +tools/rtems-tools-5-1 +tools/rtems-kernel-5 |