diff options
Diffstat (limited to 'freebsd/sys/powerpc/include/machine/psl.h')
| -rw-r--r-- | freebsd/sys/powerpc/include/machine/psl.h | 85 |
1 files changed, 30 insertions, 55 deletions
diff --git a/freebsd/sys/powerpc/include/machine/psl.h b/freebsd/sys/powerpc/include/machine/psl.h index 92bfa6ca..f0a0fa4c 100644 --- a/freebsd/sys/powerpc/include/machine/psl.h +++ b/freebsd/sys/powerpc/include/machine/psl.h @@ -35,74 +35,45 @@ #ifndef _MACHINE_PSL_H_ #define _MACHINE_PSL_H_ -#if defined(E500) /* - * Machine State Register (MSR) - e500 core - * - * The PowerPC e500 does not implement the following bits: - * - * FP, FE0, FE1 - reserved, always cleared, setting has no effect. - * + * Machine State Register (MSR) - All cores */ +#define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */ +#define PSL_VSX 0x00800000UL /* Vector-Scalar unit available */ +#define PSL_EE 0x00008000UL /* external interrupt enable */ +#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */ +#define PSL_FP 0x00002000UL /* floating point enable */ +#define PSL_ME 0x00001000UL /* machine check enable */ +#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ +#define PSL_BE 0x00000200UL /* branch trace enable */ +#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ +#define PSL_PMM 0x00000004UL /* performance monitor mark */ + +/* Machine State Register - Book-E cores */ #define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ -#define PSL_SPE 0x02000000UL /* SPE enable */ #define PSL_WE 0x00040000UL /* Wait state enable */ #define PSL_CE 0x00020000UL /* Critical interrupt enable */ -#define PSL_EE 0x00008000UL /* External interrupt enable */ -#define PSL_PR 0x00004000UL /* User mode */ -#define PSL_FP 0x00002000UL /* Floating point available */ -#define PSL_ME 0x00001000UL /* Machine check interrupt enable */ -#define PSL_FE0 0x00000800UL /* Floating point exception mode 0 */ -#define PSL_UBLE 0x00000400UL /* BTB lock enable */ +#define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */ +#define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/ #define PSL_DE 0x00000200UL /* Debug interrupt enable */ -#define PSL_FE1 0x00000100UL /* Floating point exception mode 1 */ #define PSL_IS 0x00000020UL /* Instruction address space */ #define PSL_DS 0x00000010UL /* Data address space */ -#define PSL_PMM 0x00000004UL /* Performance monitor mark */ - -#define PSL_FE_DFLT 0x00000000UL /* default == none */ - -/* Initial kernel MSR, use IS=1 ad DS=1. */ -#define PSL_KERNSET_INIT (PSL_IS | PSL_DS) -#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) -#define PSL_USERSET (PSL_KERNSET | PSL_PR) - -#else /* if defined(E500) */ -/* - * Machine State Register (MSR) - * - * The PowerPC 601 does not implement the following bits: - * - * VEC, POW, ILE, BE, RI, LE[*] - * - * [*] Little-endian mode on the 601 is implemented in the HID0 register. - */ +/* Machine State Register (MSR) - AIM cores */ #ifdef __powerpc64__ #define PSL_SF 0x8000000000000000UL /* 64-bit addressing */ #define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */ #endif -#define PSL_VEC 0x02000000UL /* AltiVec vector unit available */ #define PSL_POW 0x00040000UL /* power management */ #define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */ -#define PSL_EE 0x00008000UL /* external interrupt enable */ -#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */ -#define PSL_FP 0x00002000UL /* floating point enable */ -#define PSL_ME 0x00001000UL /* machine check enable */ -#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ #define PSL_SE 0x00000400UL /* single-step trace enable */ -#define PSL_BE 0x00000200UL /* branch trace enable */ -#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ -#define PSL_IP 0x00000040UL /* interrupt prefix */ +#define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */ #define PSL_IR 0x00000020UL /* instruction address relocation */ #define PSL_DR 0x00000010UL /* data address relocation */ -#define PSL_PMM 0x00000004UL /* performance monitor mark */ #define PSL_RI 0x00000002UL /* recoverable interrupt */ #define PSL_LE 0x00000001UL /* endian mode (1 == le) */ -#define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE) - /* * Floating-point exception modes: */ @@ -112,20 +83,24 @@ #define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */ #define PSL_FE_DFLT PSL_FE_DIS /* default == none */ -/* - * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR - */ -#define PSL_MBO 0 -#define PSL_MBZ 0 - +#if defined(BOOKE_E500) +/* Initial kernel MSR, use IS=1 ad DS=1. */ +#define PSL_KERNSET_INIT (PSL_IS | PSL_DS) +#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) +#define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */ +#elif defined(BOOKE_PPC4XX) +#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP) +#define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */ +#elif defined(AIM) #ifdef __powerpc64__ #define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) #else #define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) #endif -#define PSL_USERSET (PSL_KERNSET | PSL_PR) +#define PSL_SRR1_MASK 0x783f0000UL /* Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) */ +#endif -#define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c) +#define PSL_USERSET (PSL_KERNSET | PSL_PR) +#define PSL_USERSTATIC (~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1) & ~PSL_SRR1_MASK) -#endif /* if defined(E500) */ #endif /* _MACHINE_PSL_H_ */ |