diff options
Diffstat (limited to 'freebsd/sys/pci/if_rlreg.h')
| -rw-r--r-- | freebsd/sys/pci/if_rlreg.h | 126 |
1 files changed, 84 insertions, 42 deletions
diff --git a/freebsd/sys/pci/if_rlreg.h b/freebsd/sys/pci/if_rlreg.h index 9de72170..be89c4f5 100644 --- a/freebsd/sys/pci/if_rlreg.h +++ b/freebsd/sys/pci/if_rlreg.h @@ -74,6 +74,14 @@ #define RL_TIMERCNT 0x0048 /* timer count register */ #define RL_MISSEDPKT 0x004C /* missed packet counter */ #define RL_EECMD 0x0050 /* EEPROM command register */ + +/* RTL8139/RTL8139C+ only */ +#define RL_8139_CFG0 0x0051 /* config register #0 */ +#define RL_8139_CFG1 0x0052 /* config register #1 */ +#define RL_8139_CFG3 0x0059 /* config register #3 */ +#define RL_8139_CFG4 0x005A /* config register #4 */ +#define RL_8139_CFG5 0x00D8 /* config register #5 */ + #define RL_CFG0 0x0051 /* config register #0 */ #define RL_CFG1 0x0052 /* config register #1 */ #define RL_CFG2 0x0053 /* config register #2 */ @@ -143,6 +151,7 @@ */ #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ +#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ @@ -160,21 +169,28 @@ #define RL_HWREV_8110S 0x04000000 #define RL_HWREV_8169_8110SB 0x10000000 #define RL_HWREV_8169_8110SC 0x18000000 +#define RL_HWREV_8401E 0x24000000 #define RL_HWREV_8102EL 0x24800000 #define RL_HWREV_8102EL_SPIN1 0x24C00000 #define RL_HWREV_8168D 0x28000000 #define RL_HWREV_8168DP 0x28800000 #define RL_HWREV_8168E 0x2C000000 -#define RL_HWREV_8168_SPIN1 0x30000000 +#define RL_HWREV_8168E_VL 0x2C800000 +#define RL_HWREV_8168B_SPIN1 0x30000000 #define RL_HWREV_8100E 0x30800000 #define RL_HWREV_8101E 0x34000000 #define RL_HWREV_8102E 0x34800000 #define RL_HWREV_8103E 0x34C00000 -#define RL_HWREV_8168_SPIN2 0x38000000 -#define RL_HWREV_8168_SPIN3 0x38400000 +#define RL_HWREV_8168B_SPIN2 0x38000000 +#define RL_HWREV_8168B_SPIN3 0x38400000 #define RL_HWREV_8168C 0x3C000000 #define RL_HWREV_8168C_SPIN2 0x3C400000 #define RL_HWREV_8168CP 0x3C800000 +#define RL_HWREV_8105E 0x40800000 +#define RL_HWREV_8105E_SPIN1 0x40C00000 +#define RL_HWREV_8402 0x44000000 +#define RL_HWREV_8168F 0x48000000 +#define RL_HWREV_8411 0x48800000 #define RL_HWREV_8139 0x60000000 #define RL_HWREV_8139A 0x70000000 #define RL_HWREV_8139AG 0x70800000 @@ -428,6 +444,7 @@ #define RL_CFG3_GRANTSEL 0x80 #define RL_CFG3_WOL_MAGIC 0x20 #define RL_CFG3_WOL_LINK 0x10 +#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ #define RL_CFG3_FAST_B2B 0x01 /* @@ -435,6 +452,7 @@ */ #define RL_CFG4_LWPTN 0x04 #define RL_CFG4_LWPME 0x10 +#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ /* * Config 5 register @@ -494,6 +512,14 @@ #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ +/* Timer interrupt register */ +#define RL_TIMERINT_8169_VAL 0x00001FFF +#define RL_TIMER_MIN 0 +#define RL_TIMER_MAX 65 /* 65.528us */ +#define RL_TIMER_DEFAULT RL_TIMER_MAX +#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ +#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) + /* * Gigabit PHY access register (8169 only) */ @@ -584,32 +610,16 @@ struct rl_type { uint16_t rl_vid; uint16_t rl_did; int rl_basetype; - char *rl_name; + const char *rl_name; }; struct rl_hwrev { uint32_t rl_rev; int rl_type; - char *rl_desc; + const char *rl_desc; + int rl_max_mtu; }; -struct rl_mii_frame { - uint8_t mii_stdelim; - uint8_t mii_opcode; - uint8_t mii_phyaddr; - uint8_t mii_regaddr; - uint8_t mii_turnaround; - uint16_t mii_data; -}; - -/* - * MII constants - */ -#define RL_MII_STARTDELIM 0x01 -#define RL_MII_READOP 0x02 -#define RL_MII_WRITEOP 0x01 -#define RL_MII_TURNAROUND 0x02 - #define RL_8129 1 #define RL_8139 2 #define RL_8139CPLUS 3 @@ -657,6 +667,8 @@ struct rl_desc { #define RL_TDESC_CMD_UDPCSUMV2 0x80000000 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000 #define RL_TDESC_CMD_IPCSUMV2 0x20000000 +#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 +#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 /* * Error bits are valid only on the last descriptor of a frame @@ -764,6 +776,7 @@ struct rl_stats { #define RL_8139_RX_DESC_CNT 64 #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT +#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT #define RL_NTXSEGS 32 #define RL_RING_ALIGN 256 @@ -798,8 +811,13 @@ struct rl_stats { /* see comment in dev/re/if_re.c */ #define RL_JUMBO_FRAMELEN 7440 -#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) -#define RL_MAX_FRAMELEN \ +#define RL_JUMBO_MTU \ + (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) +#define RL_JUMBO_MTU_6K \ + ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) +#define RL_JUMBO_MTU_9K \ + ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) +#define RL_MTU \ (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) struct rl_txdesc { @@ -816,6 +834,7 @@ struct rl_rxdesc { struct rl_list_data { struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; + struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; int rl_tx_desc_cnt; int rl_rx_desc_cnt; int rl_tx_prodidx; @@ -824,7 +843,9 @@ struct rl_list_data { int rl_tx_free; bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ + bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ bus_dmamap_t rl_rx_sparemap; + bus_dmamap_t rl_jrx_sparemap; bus_dma_tag_t rl_stag; /* stats mapping tag */ bus_dmamap_t rl_smap; /* stats map */ struct rl_stats *rl_stats; @@ -849,15 +870,23 @@ struct rl_softc { struct resource *rl_res; int rl_res_id; int rl_res_type; + struct resource *rl_res_pba; struct resource *rl_irq[RL_MSI_MESSAGES]; void *rl_intrhand[RL_MSI_MESSAGES]; device_t rl_miibus; bus_dma_tag_t rl_parent_tag; uint8_t rl_type; + const struct rl_hwrev *rl_hwrev; int rl_eecmd_read; int rl_eewidth; - uint8_t rl_stats_no_timeout; + int rl_expcap; int rl_txthresh; + bus_size_t rl_cfg0; + bus_size_t rl_cfg1; + bus_size_t rl_cfg2; + bus_size_t rl_cfg3; + bus_size_t rl_cfg4; + bus_size_t rl_cfg5; struct rl_chain_data rl_cdata; struct rl_list_data rl_ldata; struct callout rl_stat_callout; @@ -865,7 +894,6 @@ struct rl_softc { struct mtx rl_mtx; struct mbuf *rl_head; struct mbuf *rl_tail; - uint32_t rl_hwrev; uint32_t rl_rxlenmask; int rl_testmode; int rl_if_flags; @@ -878,26 +906,31 @@ struct rl_softc { int rxcycles; #endif - struct task rl_txtask; struct task rl_inttask; int rl_txstart; + int rl_int_rx_act; + int rl_int_rx_mod; uint32_t rl_flags; -#define RL_FLAG_MSI 0x0001 -#define RL_FLAG_AUTOPAD 0x0002 -#define RL_FLAG_PHYWAKE_PM 0x0004 -#define RL_FLAG_PHYWAKE 0x0008 -#define RL_FLAG_NOJUMBO 0x0010 -#define RL_FLAG_PAR 0x0020 -#define RL_FLAG_DESCV2 0x0040 -#define RL_FLAG_MACSTAT 0x0080 -#define RL_FLAG_FASTETHER 0x0100 -#define RL_FLAG_CMDSTOP 0x0200 -#define RL_FLAG_MACRESET 0x0400 -#define RL_FLAG_WOLRXENB 0x1000 -#define RL_FLAG_MACSLEEP 0x2000 -#define RL_FLAG_PCIE 0x4000 -#define RL_FLAG_LINK 0x8000 +#define RL_FLAG_MSI 0x00000001 +#define RL_FLAG_AUTOPAD 0x00000002 +#define RL_FLAG_PHYWAKE_PM 0x00000004 +#define RL_FLAG_PHYWAKE 0x00000008 +#define RL_FLAG_JUMBOV2 0x00000010 +#define RL_FLAG_PAR 0x00000020 +#define RL_FLAG_DESCV2 0x00000040 +#define RL_FLAG_MACSTAT 0x00000080 +#define RL_FLAG_FASTETHER 0x00000100 +#define RL_FLAG_CMDSTOP 0x00000200 +#define RL_FLAG_MACRESET 0x00000400 +#define RL_FLAG_MSIX 0x00000800 +#define RL_FLAG_WOLRXENB 0x00001000 +#define RL_FLAG_MACSLEEP 0x00002000 +#define RL_FLAG_WAIT_TXPOLL 0x00004000 +#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 +#define RL_FLAG_WOL_MANLINK 0x00010000 +#define RL_FLAG_PCIE 0x40000000 +#define RL_FLAG_LINK 0x80000000 }; #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) @@ -923,6 +956,9 @@ struct rl_softc { #define CSR_READ_1(sc, reg) \ bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) +#define CSR_BARRIER(sc, reg, length, flags) \ + bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) + #define CSR_SETBIT_1(sc, offset, val) \ CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) @@ -1012,9 +1048,15 @@ struct rl_softc { #define DLINK_DEVICEID_530TXPLUS 0x1300 /* + * D-Link DFE-520TX rev. C1 device ID + */ +#define DLINK_DEVICEID_520TX_REVC1 0x4200 + +/* * D-Link DFE-5280T device ID */ #define DLINK_DEVICEID_528T 0x4300 +#define DLINK_DEVICEID_530T_REVC 0x4302 /* * D-Link DFE-690TXD device ID |