diff options
Diffstat (limited to 'freebsd/sys/dev/pci/pci.c')
| -rw-r--r-- | freebsd/sys/dev/pci/pci.c | 1806 |
1 files changed, 1508 insertions, 298 deletions
diff --git a/freebsd/sys/dev/pci/pci.c b/freebsd/sys/dev/pci/pci.c index e76b6b9e..789825dc 100644 --- a/freebsd/sys/dev/pci/pci.c +++ b/freebsd/sys/dev/pci/pci.c @@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$"); #include <sys/systm.h> #include <sys/malloc.h> #include <sys/module.h> +#include <sys/limits.h> #include <sys/linker.h> #include <sys/fcntl.h> #include <sys/conf.h> @@ -64,6 +65,11 @@ __FBSDID("$FreeBSD$"); #include <dev/pci/pcivar.h> #include <dev/pci/pci_private.h> +#ifdef PCI_IOV +#include <sys/nv.h> +#include <dev/pci/pci_iov_private.h> +#endif + #include <dev/usb/controller/xhcireg.h> #include <dev/usb/controller/ehcireg.h> #include <dev/usb/controller/ohcireg.h> @@ -72,21 +78,6 @@ __FBSDID("$FreeBSD$"); #include <rtems/bsd/local/pcib_if.h> #include <rtems/bsd/local/pci_if.h> -/* - * XXX: Due to a limitation of the bus_dma_tag_create() API, we cannot - * specify a 4GB boundary on 32-bit targets. Usually this does not - * matter as it is ok to use a boundary of 0 on these systems. - * However, in the case of PAE, DMA addresses can cross a 4GB - * boundary, so as a workaround use a 2GB boundary. - */ -#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) -#ifdef PAE -#define PCI_DMA_BOUNDARY 0x80000000 -#else -#define PCI_DMA_BOUNDARY 0x100000000 -#endif -#endif - #define PCIR_IS_BIOS(cfg, reg) \ (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) @@ -94,7 +85,6 @@ __FBSDID("$FreeBSD$"); static int pci_has_quirk(uint32_t devid, int quirk); static pci_addr_t pci_mapbase(uint64_t mapreg); static const char *pci_maptype(uint64_t mapreg); -static int pci_mapsize(uint64_t testval); static int pci_maprange(uint64_t mapreg); static pci_addr_t pci_rombase(uint64_t mapreg); static int pci_romsize(uint64_t testval); @@ -109,11 +99,11 @@ static int pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, int force, int prefetch); static int pci_probe(device_t dev); static int pci_attach(device_t dev); +static int pci_detach(device_t dev); static void pci_load_vendor_data(void); static int pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc); static char *pci_describe_device(device_t dev); -static bus_dma_tag_t pci_get_dma_tag(device_t bus, device_t dev); static int pci_modevent(module_t mod, int what, void *arg); static void pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg); @@ -125,11 +115,6 @@ static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data); #endif static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); -static void pci_disable_msi(device_t dev); -static void pci_enable_msi(device_t dev, uint64_t address, - uint16_t data); -static void pci_enable_msix(device_t dev, u_int index, - uint64_t address, uint32_t data); static void pci_mask_msix(device_t dev, u_int index); static void pci_unmask_msix(device_t dev, u_int index); static int pci_msi_blacklisted(void); @@ -139,13 +124,19 @@ static void pci_resume_msix(device_t dev); static int pci_remap_intr_method(device_t bus, device_t dev, u_int irq); +static int pci_get_id_method(device_t dev, device_t child, + enum pci_id_type type, uintptr_t *rid); + +static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, + int b, int s, int f, uint16_t vid, uint16_t did); + static device_method_t pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, pci_probe), DEVMETHOD(device_attach, pci_attach), - DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_detach, pci_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, pci_suspend), + DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, pci_resume), /* Bus interface */ @@ -167,9 +158,14 @@ static device_method_t pci_methods[] = { DEVMETHOD(bus_release_resource, pci_release_resource), DEVMETHOD(bus_activate_resource, pci_activate_resource), DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), + DEVMETHOD(bus_child_deleted, pci_child_deleted), + DEVMETHOD(bus_child_detached, pci_child_detached), DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), DEVMETHOD(bus_child_location_str, pci_child_location_str_method), DEVMETHOD(bus_remap_intr, pci_remap_intr_method), + DEVMETHOD(bus_suspend_child, pci_suspend_child), + DEVMETHOD(bus_resume_child, pci_resume_child), + DEVMETHOD(bus_rescan, pci_rescan_method), /* PCI interface */ DEVMETHOD(pci_read_config, pci_read_config_method), @@ -183,13 +179,28 @@ static device_method_t pci_methods[] = { DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), + DEVMETHOD(pci_find_cap, pci_find_cap_method), DEVMETHOD(pci_find_extcap, pci_find_extcap_method), + DEVMETHOD(pci_find_htcap, pci_find_htcap_method), DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), + DEVMETHOD(pci_enable_msi, pci_enable_msi_method), + DEVMETHOD(pci_enable_msix, pci_enable_msix_method), + DEVMETHOD(pci_disable_msi, pci_disable_msi_method), DEVMETHOD(pci_remap_msix, pci_remap_msix_method), DEVMETHOD(pci_release_msi, pci_release_msi_method), DEVMETHOD(pci_msi_count, pci_msi_count_method), DEVMETHOD(pci_msix_count, pci_msix_count_method), + DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), + DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), + DEVMETHOD(pci_get_id, pci_get_id_method), + DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), + DEVMETHOD(pci_child_added, pci_child_added_method), +#ifdef PCI_IOV + DEVMETHOD(pci_iov_attach, pci_iov_attach_method), + DEVMETHOD(pci_iov_detach, pci_iov_detach_method), + DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), +#endif DEVMETHOD_END }; @@ -272,12 +283,13 @@ static const struct pci_quirk pci_quirks[] = { { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, /* - * Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that - * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the - * command register is set. + * Atheros AR8161/AR8162/E2200/E2400 Ethernet controllers have a + * bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit + * of the command register is set. */ { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, + { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* @@ -308,53 +320,46 @@ static int pcie_chipset, pcix_chipset; SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); static int pci_enable_io_modes = 1; -TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); -SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, +SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, &pci_enable_io_modes, 1, "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ enable these bits correctly. We'd like to do this all the time, but there\n\ are some peripherals that this causes problems with."); static int pci_do_realloc_bars = 0; -TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars); -SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW, +SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, &pci_do_realloc_bars, 0, - "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan."); + "Attempt to allocate a new range for any BARs whose original " + "firmware-assigned ranges fail to allocate during the initial device scan."); static int pci_do_power_nodriver = 0; -TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); -SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, +SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, &pci_do_power_nodriver, 0, "Place a function into D3 state when no driver attaches to it. 0 means\n\ disable. 1 means conservatively place devices into D3 state. 2 means\n\ -agressively place devices into D3 state. 3 means put absolutely everything\n\ +aggressively place devices into D3 state. 3 means put absolutely everything\n\ in D3 state."); int pci_do_power_resume = 1; -TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); -SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, +SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, &pci_do_power_resume, 1, "Transition from D3 -> D0 on resume."); int pci_do_power_suspend = 1; -TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend); -SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW, +SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, &pci_do_power_suspend, 1, "Transition from D0 -> D3 on suspend."); static int pci_do_msi = 1; -TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); -SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, +SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, "Enable support for MSI interrupts"); static int pci_do_msix = 1; -TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); -SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, +SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, "Enable support for MSI-X interrupts"); static int pci_honor_msi_blacklist = 1; -TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); -SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, +SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); #if defined(__i386__) || defined(__amd64__) @@ -362,17 +367,25 @@ static int pci_usb_takeover = 1; #else static int pci_usb_takeover = 0; #endif -TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover); SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\ Disable this if you depend on BIOS emulation of USB devices, that is\n\ you use USB devices (like keyboard or mouse) but do not load USB drivers"); static int pci_clear_bars; -TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars); SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, "Ignore firmware-assigned resources for BARs."); +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) +static int pci_clear_buses; +SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, + "Ignore firmware-assigned bus numbers."); +#endif + +static int pci_enable_ari = 1; +SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, + 0, "Enable support for PCIe Alternative RID Interpretation"); + static int pci_has_quirk(uint32_t devid, int quirk) { @@ -488,7 +501,7 @@ pci_maptype(uint64_t mapreg) /* return log2 of map size decoded for memory or port map */ -static int +int pci_mapsize(uint64_t testval) { int ln2size; @@ -532,7 +545,7 @@ pci_romsize(uint64_t testval) } return (ln2size); } - + /* return log2 of address range supported by map register */ static int @@ -580,12 +593,24 @@ pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) case PCIM_HDRTYPE_NORMAL: cfg->subvendor = REG(PCIR_SUBVEND_0, 2); cfg->subdevice = REG(PCIR_SUBDEV_0, 2); + cfg->mingnt = REG(PCIR_MINGNT, 1); + cfg->maxlat = REG(PCIR_MAXLAT, 1); cfg->nummaps = PCI_MAXMAPS_0; break; case PCIM_HDRTYPE_BRIDGE: + cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); + cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); + cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); + cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); + cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); cfg->nummaps = PCI_MAXMAPS_1; break; case PCIM_HDRTYPE_CARDBUS: + cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); + cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); + cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); + cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); + cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); cfg->subvendor = REG(PCIR_SUBVEND_2, 2); cfg->subdevice = REG(PCIR_SUBDEV_2, 2); cfg->nummaps = PCI_MAXMAPS_2; @@ -596,79 +621,167 @@ pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) /* read configuration header into pcicfgregs structure */ struct pci_devinfo * -pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size) +pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) { #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) - pcicfgregs *cfg = NULL; - struct pci_devinfo *devlist_entry; - struct devlist *devlist_head; + uint16_t vid, did; - devlist_head = &pci_devq; + vid = REG(PCIR_VENDOR, 2); + did = REG(PCIR_DEVICE, 2); + if (vid != 0xffff) + return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); - devlist_entry = NULL; + return (NULL); +} - if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) { - devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); - if (devlist_entry == NULL) - return (NULL); +struct pci_devinfo * +pci_alloc_devinfo_method(device_t dev) +{ + + return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, + M_WAITOK | M_ZERO)); +} + +static struct pci_devinfo * +pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, + uint16_t vid, uint16_t did) +{ + struct pci_devinfo *devlist_entry; + pcicfgregs *cfg; + + devlist_entry = PCI_ALLOC_DEVINFO(bus); + + cfg = &devlist_entry->cfg; + + cfg->domain = d; + cfg->bus = b; + cfg->slot = s; + cfg->func = f; + cfg->vendor = vid; + cfg->device = did; + cfg->cmdreg = REG(PCIR_COMMAND, 2); + cfg->statreg = REG(PCIR_STATUS, 2); + cfg->baseclass = REG(PCIR_CLASS, 1); + cfg->subclass = REG(PCIR_SUBCLASS, 1); + cfg->progif = REG(PCIR_PROGIF, 1); + cfg->revid = REG(PCIR_REVID, 1); + cfg->hdrtype = REG(PCIR_HDRTYPE, 1); + cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); + cfg->lattimer = REG(PCIR_LATTIMER, 1); + cfg->intpin = REG(PCIR_INTPIN, 1); + cfg->intline = REG(PCIR_INTLINE, 1); + + cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; + cfg->hdrtype &= ~PCIM_MFDEV; + STAILQ_INIT(&cfg->maps); + + cfg->iov = NULL; + + pci_fixancient(cfg); + pci_hdrtypedata(pcib, b, s, f, cfg); + + if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) + pci_read_cap(pcib, cfg); + + STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); + + devlist_entry->conf.pc_sel.pc_domain = cfg->domain; + devlist_entry->conf.pc_sel.pc_bus = cfg->bus; + devlist_entry->conf.pc_sel.pc_dev = cfg->slot; + devlist_entry->conf.pc_sel.pc_func = cfg->func; + devlist_entry->conf.pc_hdr = cfg->hdrtype; + + devlist_entry->conf.pc_subvendor = cfg->subvendor; + devlist_entry->conf.pc_subdevice = cfg->subdevice; + devlist_entry->conf.pc_vendor = cfg->vendor; + devlist_entry->conf.pc_device = cfg->device; + + devlist_entry->conf.pc_class = cfg->baseclass; + devlist_entry->conf.pc_subclass = cfg->subclass; + devlist_entry->conf.pc_progif = cfg->progif; + devlist_entry->conf.pc_revid = cfg->revid; + + pci_numdevs++; + pci_generation++; - cfg = &devlist_entry->cfg; - - cfg->domain = d; - cfg->bus = b; - cfg->slot = s; - cfg->func = f; - cfg->vendor = REG(PCIR_VENDOR, 2); - cfg->device = REG(PCIR_DEVICE, 2); - cfg->cmdreg = REG(PCIR_COMMAND, 2); - cfg->statreg = REG(PCIR_STATUS, 2); - cfg->baseclass = REG(PCIR_CLASS, 1); - cfg->subclass = REG(PCIR_SUBCLASS, 1); - cfg->progif = REG(PCIR_PROGIF, 1); - cfg->revid = REG(PCIR_REVID, 1); - cfg->hdrtype = REG(PCIR_HDRTYPE, 1); - cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); - cfg->lattimer = REG(PCIR_LATTIMER, 1); - cfg->intpin = REG(PCIR_INTPIN, 1); - cfg->intline = REG(PCIR_INTLINE, 1); - - cfg->mingnt = REG(PCIR_MINGNT, 1); - cfg->maxlat = REG(PCIR_MAXLAT, 1); - - cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; - cfg->hdrtype &= ~PCIM_MFDEV; - STAILQ_INIT(&cfg->maps); - - pci_fixancient(cfg); - pci_hdrtypedata(pcib, b, s, f, cfg); - - if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) - pci_read_cap(pcib, cfg); - - STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); - - devlist_entry->conf.pc_sel.pc_domain = cfg->domain; - devlist_entry->conf.pc_sel.pc_bus = cfg->bus; - devlist_entry->conf.pc_sel.pc_dev = cfg->slot; - devlist_entry->conf.pc_sel.pc_func = cfg->func; - devlist_entry->conf.pc_hdr = cfg->hdrtype; - - devlist_entry->conf.pc_subvendor = cfg->subvendor; - devlist_entry->conf.pc_subdevice = cfg->subdevice; - devlist_entry->conf.pc_vendor = cfg->vendor; - devlist_entry->conf.pc_device = cfg->device; - - devlist_entry->conf.pc_class = cfg->baseclass; - devlist_entry->conf.pc_subclass = cfg->subclass; - devlist_entry->conf.pc_progif = cfg->progif; - devlist_entry->conf.pc_revid = cfg->revid; - - pci_numdevs++; - pci_generation++; - } return (devlist_entry); +} #undef REG + +static void +pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) +{ +#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ + cfg->ea.ea_location + (n), w) + int num_ent; + int ptr; + int a, b; + uint32_t val; + int ent_size; + uint32_t dw[4]; + uint64_t base, max_offset; + struct pci_ea_entry *eae; + + if (cfg->ea.ea_location == 0) + return; + + STAILQ_INIT(&cfg->ea.ea_entries); + + /* Determine the number of entries */ + num_ent = REG(PCIR_EA_NUM_ENT, 2); + num_ent &= PCIM_EA_NUM_ENT_MASK; + + /* Find the first entry to care of */ + ptr = PCIR_EA_FIRST_ENT; + + /* Skip DWORD 2 for type 1 functions */ + if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) + ptr += 4; + + for (a = 0; a < num_ent; a++) { + + eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); + eae->eae_cfg_offset = cfg->ea.ea_location + ptr; + + /* Read a number of dwords in the entry */ + val = REG(ptr, 4); + ptr += 4; + ent_size = (val & PCIM_EA_ES); + + for (b = 0; b < ent_size; b++) { + dw[b] = REG(ptr, 4); + ptr += 4; + } + + eae->eae_flags = val; + eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; + + base = dw[0] & PCIM_EA_FIELD_MASK; + max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; + b = 2; + if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { + base |= (uint64_t)dw[b] << 32UL; + b++; + } + if (((dw[1] & PCIM_EA_IS_64) != 0) + && (b < ent_size)) { + max_offset |= (uint64_t)dw[b] << 32UL; + b++; + } + + eae->eae_base = base; + eae->eae_max_offset = max_offset; + + STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); + + if (bootverbose) { + printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", + cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, + (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); + } + } } +#undef REG static void pci_read_cap(device_t pcib, pcicfgregs *cfg) @@ -795,6 +908,7 @@ pci_read_cap(device_t pcib, pcicfgregs *cfg) if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) pcix_chipset = 1; + cfg->pcix.pcix_location = ptr; break; case PCIY_EXPRESS: /* PCI-express */ /* @@ -802,6 +916,13 @@ pci_read_cap(device_t pcib, pcicfgregs *cfg) * at least one PCI-express device. */ pcie_chipset = 1; + cfg->pcie.pcie_location = ptr; + val = REG(ptr + PCIER_FLAGS, 2); + cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; + break; + case PCIY_EA: /* Enhanced Allocation */ + cfg->ea.ea_location = ptr; + pci_ea_fill_info(pcib, cfg); break; default: break; @@ -958,10 +1079,9 @@ pci_read_vpd(device_t pcib, pcicfgregs *cfg) remain |= byte2 << 8; if (remain > (0x7f*4 - vrs.off)) { state = -1; - printf( - "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n", - cfg->domain, cfg->bus, cfg->slot, - cfg->func, remain); + pci_printf(cfg, + "invalid VPD data, remain %#x\n", + remain); } name = byte & 0x7f; } else { @@ -1033,10 +1153,8 @@ pci_read_vpd(device_t pcib, pcicfgregs *cfg) * if this happens, we can't trust the rest * of the VPD. */ - printf( - "pci%d:%d:%d:%d: bad keyword length: %d\n", - cfg->domain, cfg->bus, cfg->slot, - cfg->func, dflen); + pci_printf(cfg, "bad keyword length: %d\n", + dflen); cksumvalid = 0; state = -1; break; @@ -1069,10 +1187,8 @@ pci_read_vpd(device_t pcib, pcicfgregs *cfg) cksumvalid = 1; else { if (bootverbose) - printf( - "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n", - cfg->domain, cfg->bus, - cfg->slot, cfg->func, + pci_printf(cfg, + "bad VPD cksum, remain %hhu\n", vrs.cksum); cksumvalid = 0; state = -1; @@ -1150,9 +1266,7 @@ pci_read_vpd(device_t pcib, pcicfgregs *cfg) break; default: - printf("pci%d:%d:%d:%d: invalid state: %d\n", - cfg->domain, cfg->bus, cfg->slot, cfg->func, - state); + pci_printf(cfg, "invalid state: %d\n", state); state = -1; break; } @@ -1169,8 +1283,7 @@ pci_read_vpd(device_t pcib, pcicfgregs *cfg) } if (state < -1) { /* I/O error, clean up */ - printf("pci%d:%d:%d:%d: failed to read VPD data.\n", - cfg->domain, cfg->bus, cfg->slot, cfg->func); + pci_printf(cfg, "failed to read VPD data.\n"); if (cfg->vpd.vpd_ident != NULL) { free(cfg->vpd.vpd_ident, M_DEVBUF); cfg->vpd.vpd_ident = NULL; @@ -1238,12 +1351,55 @@ pci_fetch_vpd_list(device_t dev) } /* - * Find the requested extended capability and return the offset in - * configuration space via the pointer provided. The function returns - * 0 on success and error code otherwise. + * Find the requested HyperTransport capability and return the offset + * in configuration space via the pointer provided. The function + * returns 0 on success and an error code otherwise. */ int -pci_find_extcap_method(device_t dev, device_t child, int capability, +pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) +{ + int ptr, error; + uint16_t val; + + error = pci_find_cap(child, PCIY_HT, &ptr); + if (error) + return (error); + + /* + * Traverse the capabilities list checking each HT capability + * to see if it matches the requested HT capability. + */ + while (ptr != 0) { + val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); + if (capability == PCIM_HTCAP_SLAVE || + capability == PCIM_HTCAP_HOST) + val &= 0xe000; + else + val &= PCIM_HTCMD_CAP_MASK; + if (val == capability) { + if (capreg != NULL) + *capreg = ptr; + return (0); + } + + /* Skip to the next HT capability. */ + while (ptr != 0) { + ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); + if (pci_read_config(child, ptr + PCICAP_ID, 1) == + PCIY_HT) + break; + } + } + return (ENOENT); +} + +/* + * Find the requested capability and return the offset in + * configuration space via the pointer provided. The function returns + * 0 on success and an error code otherwise. + */ +int +pci_find_cap_method(device_t dev, device_t child, int capability, int *capreg) { struct pci_devinfo *dinfo = device_get_ivars(child); @@ -1291,12 +1447,50 @@ pci_find_extcap_method(device_t dev, device_t child, int capability, } /* + * Find the requested extended capability and return the offset in + * configuration space via the pointer provided. The function returns + * 0 on success and an error code otherwise. + */ +int +pci_find_extcap_method(device_t dev, device_t child, int capability, + int *capreg) +{ + struct pci_devinfo *dinfo = device_get_ivars(child); + pcicfgregs *cfg = &dinfo->cfg; + uint32_t ecap; + uint16_t ptr; + + /* Only supported for PCI-express devices. */ + if (cfg->pcie.pcie_location == 0) + return (ENXIO); + + ptr = PCIR_EXTCAP; + ecap = pci_read_config(child, ptr, 4); + if (ecap == 0xffffffff || ecap == 0) + return (ENOENT); + for (;;) { + if (PCI_EXTCAP_ID(ecap) == capability) { + if (capreg != NULL) + *capreg = ptr; + return (0); + } + ptr = PCI_EXTCAP_NEXTPTR(ecap); + if (ptr == 0) + break; + ecap = pci_read_config(child, ptr, 4); + } + + return (ENOENT); +} + +/* * Support for MSI-X message interrupts. */ void -pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) +pci_enable_msix_method(device_t dev, device_t child, u_int index, + uint64_t address, uint32_t data) { - struct pci_devinfo *dinfo = device_get_ivars(dev); + struct pci_devinfo *dinfo = device_get_ivars(child); struct pcicfg_msix *msix = &dinfo->cfg.msix; uint32_t offset; @@ -1307,7 +1501,7 @@ pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) bus_write_4(msix->msix_table_res, offset + 8, data); /* Enable MSI -> HT mapping. */ - pci_ht_map_msi(dev, address); + pci_ht_map_msi(child, address); } void @@ -1459,7 +1653,7 @@ pci_alloc_msix_method(device_t dev, device_t child, int *count) if (bootverbose) { rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); if (actual == 1) - device_printf(child, "using IRQ %lu for MSI-X\n", + device_printf(child, "using IRQ %ju for MSI-X\n", rle->start); else { int run; @@ -1469,7 +1663,7 @@ pci_alloc_msix_method(device_t dev, device_t child, int *count) * IRQ values as ranges. 'irq' is the previous IRQ. * 'run' is true if we are in a range. */ - device_printf(child, "using IRQs %lu", rle->start); + device_printf(child, "using IRQs %ju", rle->start); irq = rle->start; run = 0; for (i = 1; i < actual; i++) { @@ -1490,7 +1684,7 @@ pci_alloc_msix_method(device_t dev, device_t child, int *count) } /* Start new range. */ - printf(",%lu", rle->start); + printf(",%ju", rle->start); irq = rle->start; } @@ -1558,7 +1752,7 @@ pci_alloc_msix_method(device_t dev, device_t child, int *count) * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and * C. After the call to pci_alloc_msix(), the device will be setup to * have an MSI-X table of ABC--- (where - means no vector assigned). - * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 }, + * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, * then the MSI-X table will look like A-AB-B, and the 'C' vector will * be freed back to the system. This device will also have valid * SYS_RES_IRQ rids of 1, 3, 4, and 6. @@ -1608,17 +1802,21 @@ pci_remap_msix_method(device_t dev, device_t child, int count, free(used, M_DEVBUF); return (EINVAL); } - + /* Make sure none of the resources are allocated. */ for (i = 0; i < msix->msix_table_len; i++) { if (msix->msix_table[i].mte_vector == 0) continue; - if (msix->msix_table[i].mte_handlers > 0) + if (msix->msix_table[i].mte_handlers > 0) { + free(used, M_DEVBUF); return (EBUSY); + } rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); KASSERT(rle != NULL, ("missing resource")); - if (rle->res != NULL) + if (rle->res != NULL) { + free(used, M_DEVBUF); return (EBUSY); + } } /* Free the existing resource list entries. */ @@ -1663,7 +1861,7 @@ pci_remap_msix_method(device_t dev, device_t child, int count, for (i = 0; i < count; i++) { if (vectors[i] == 0) continue; - irq = msix->msix_vectors[vectors[i]].mv_irq; + irq = msix->msix_vectors[vectors[i] - 1].mv_irq; resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, irq, 1); } @@ -1677,7 +1875,7 @@ pci_remap_msix_method(device_t dev, device_t child, int count, printf("---"); else printf("%d", - msix->msix_vectors[vectors[i]].mv_irq); + msix->msix_vectors[vectors[i] - 1].mv_irq); } printf("\n"); } @@ -1749,6 +1947,28 @@ pci_msix_count_method(device_t dev, device_t child) return (0); } +int +pci_msix_pba_bar_method(device_t dev, device_t child) +{ + struct pci_devinfo *dinfo = device_get_ivars(child); + struct pcicfg_msix *msix = &dinfo->cfg.msix; + + if (pci_do_msix && msix->msix_location != 0) + return (msix->msix_pba_bar); + return (-1); +} + +int +pci_msix_table_bar_method(device_t dev, device_t child) +{ + struct pci_devinfo *dinfo = device_get_ivars(child); + struct pcicfg_msix *msix = &dinfo->cfg.msix; + + if (pci_do_msix && msix->msix_location != 0) + return (msix->msix_table_bar); + return (-1); +} + /* * HyperTransport MSI mapping control */ @@ -1778,12 +1998,30 @@ pci_ht_map_msi(device_t dev, uint64_t addr) } int +pci_get_max_payload(device_t dev) +{ + struct pci_devinfo *dinfo = device_get_ivars(dev); + int cap; + uint16_t val; + + cap = dinfo->cfg.pcie.pcie_location; + if (cap == 0) + return (0); + val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); + val &= PCIEM_CTL_MAX_PAYLOAD; + val >>= 5; + return (1 << (val + 7)); +} + +int pci_get_max_read_req(device_t dev) { + struct pci_devinfo *dinfo = device_get_ivars(dev); int cap; uint16_t val; - if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0) + cap = dinfo->cfg.pcie.pcie_location; + if (cap == 0) return (0); val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); val &= PCIEM_CTL_MAX_READ_REQUEST; @@ -1794,10 +2032,12 @@ pci_get_max_read_req(device_t dev) int pci_set_max_read_req(device_t dev, int size) { + struct pci_devinfo *dinfo = device_get_ivars(dev); int cap; uint16_t val; - if (pci_find_cap(dev, PCIY_EXPRESS, &cap) != 0) + cap = dinfo->cfg.pcie.pcie_location; + if (cap == 0) return (0); if (size < 128) size = 128; @@ -1811,49 +2051,107 @@ pci_set_max_read_req(device_t dev, int size) return (size); } +uint32_t +pcie_read_config(device_t dev, int reg, int width) +{ + struct pci_devinfo *dinfo = device_get_ivars(dev); + int cap; + + cap = dinfo->cfg.pcie.pcie_location; + if (cap == 0) { + if (width == 2) + return (0xffff); + return (0xffffffff); + } + + return (pci_read_config(dev, cap + reg, width)); +} + +void +pcie_write_config(device_t dev, int reg, uint32_t value, int width) +{ + struct pci_devinfo *dinfo = device_get_ivars(dev); + int cap; + + cap = dinfo->cfg.pcie.pcie_location; + if (cap == 0) + return; + pci_write_config(dev, cap + reg, value, width); +} + +/* + * Adjusts a PCI-e capability register by clearing the bits in mask + * and setting the bits in (value & mask). Bits not set in mask are + * not adjusted. + * + * Returns the old value on success or all ones on failure. + */ +uint32_t +pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, + int width) +{ + struct pci_devinfo *dinfo = device_get_ivars(dev); + uint32_t old, new; + int cap; + + cap = dinfo->cfg.pcie.pcie_location; + if (cap == 0) { + if (width == 2) + return (0xffff); + return (0xffffffff); + } + + old = pci_read_config(dev, cap + reg, width); + new = old & ~mask; + new |= (value & mask); + pci_write_config(dev, cap + reg, new, width); + return (old); +} + /* * Support for MSI message signalled interrupts. */ void -pci_enable_msi(device_t dev, uint64_t address, uint16_t data) +pci_enable_msi_method(device_t dev, device_t child, uint64_t address, + uint16_t data) { - struct pci_devinfo *dinfo = device_get_ivars(dev); + struct pci_devinfo *dinfo = device_get_ivars(child); struct pcicfg_msi *msi = &dinfo->cfg.msi; /* Write data and address values. */ - pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, + pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, address & 0xffffffff, 4); if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { - pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH, + pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, address >> 32, 4); - pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT, + pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, data, 2); } else - pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data, + pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2); /* Enable MSI in the control register. */ msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; - pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, - 2); + pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, + msi->msi_ctrl, 2); /* Enable MSI -> HT mapping. */ - pci_ht_map_msi(dev, address); + pci_ht_map_msi(child, address); } void -pci_disable_msi(device_t dev) +pci_disable_msi_method(device_t dev, device_t child) { - struct pci_devinfo *dinfo = device_get_ivars(dev); + struct pci_devinfo *dinfo = device_get_ivars(child); struct pcicfg_msi *msi = &dinfo->cfg.msi; /* Disable MSI -> HT mapping. */ - pci_ht_map_msi(dev, 0); + pci_ht_map_msi(child, 0); /* Disable MSI in the control register. */ msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; - pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, - 2); + pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, + msi->msi_ctrl, 2); } /* @@ -1896,7 +2194,7 @@ pci_remap_intr_method(device_t bus, device_t dev, u_int irq) struct msix_table_entry *mte; struct msix_vector *mv; uint64_t addr; - uint32_t data; + uint32_t data; int error, i, j; /* @@ -2282,7 +2580,7 @@ pci_set_powerstate_method(device_t dev, device_t child, int state) struct pci_devinfo *dinfo = device_get_ivars(child); pcicfgregs *cfg = &dinfo->cfg; uint16_t status; - int result, oldstate, highest, delay; + int oldstate, highest, delay; if (cfg->pp.pp_cap == 0) return (EOPNOTSUPP); @@ -2317,7 +2615,6 @@ pci_set_powerstate_method(device_t dev, device_t child, int state) delay = 0; status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) & ~PCIM_PSTAT_DMASK; - result = 0; switch (state) { case PCI_POWERSTATE_D0: status |= PCIM_PSTAT_D0; @@ -2533,8 +2830,9 @@ pci_memen(device_t dev) return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; } -static void -pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) +void +pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, + int *bar64) { struct pci_devinfo *dinfo; pci_addr_t map, testval; @@ -2554,6 +2852,8 @@ pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) pci_write_config(dev, reg, map, 4); *mapp = map; *testvalp = testval; + if (bar64 != NULL) + *bar64 = 0; return; } @@ -2595,6 +2895,8 @@ pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) *mapp = map; *testvalp = testval; + if (bar64 != NULL) + *bar64 = (ln2range == 64); } static void @@ -2649,7 +2951,7 @@ pci_bar_enabled(device_t dev, struct pci_map *pm) return ((cmd & PCIM_CMD_PORTEN) != 0); } -static struct pci_map * +struct pci_map * pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) { struct pci_devinfo *dinfo; @@ -2720,7 +3022,7 @@ pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, return (barlen); } - pci_read_bar(dev, reg, &map, &testval); + pci_read_bar(dev, reg, &map, &testval, NULL); if (PCI_BAR_MEM(map)) { type = SYS_RES_MEMORY; if (map & PCIM_BAR_MEM_PREFETCH) @@ -2816,7 +3118,7 @@ pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, flags |= RF_PREFETCHABLE; if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { start = 0; /* Let the parent decide. */ - end = ~0ul; + end = ~0; } else { start = base; end = base + count - 1; @@ -2831,7 +3133,7 @@ pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, */ res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, flags); - if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) { + if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0)) { /* * If the allocation fails, try to allocate a resource for * this BAR using any available range. The firmware felt @@ -2839,8 +3141,8 @@ pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, * disable decoding if we can help it. */ resource_list_delete(rl, type, reg); - resource_list_add(rl, type, reg, 0, ~0ul, count); - res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul, + resource_list_add(rl, type, reg, 0, ~0, count); + res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, count, flags); } if (res == NULL) { @@ -2877,7 +3179,6 @@ static void pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, uint32_t prefetchmask) { - struct resource *r; int rid, type, progif; #if 0 /* if this device supports PCI native addressing use it */ @@ -2900,11 +3201,11 @@ pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, } else { rid = PCIR_BAR(0); resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); - r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, + (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 0); rid = PCIR_BAR(1); resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); - r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, + (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 0); } if (progif & PCIP_STORAGE_IDE_MODESEC) { @@ -2915,11 +3216,11 @@ pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, } else { rid = PCIR_BAR(2); resource_list_add(rl, type, rid, 0x170, 0x177, 8); - r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170, + (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 0); rid = PCIR_BAR(3); resource_list_add(rl, type, rid, 0x376, 0x376, 1); - r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376, + (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 0); } pci_add_map(bus, dev, PCIR_BAR(4), rl, force, @@ -3159,6 +3460,335 @@ xhci_early_takeover(device_t self) bus_release_resource(self, SYS_RES_MEMORY, rid, res); } +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) +static void +pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, + struct resource_list *rl) +{ + struct resource *res; + char *cp; + rman_res_t start, end, count; + int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; + + switch (cfg->hdrtype & PCIM_HDRTYPE) { + case PCIM_HDRTYPE_BRIDGE: + sec_reg = PCIR_SECBUS_1; + sub_reg = PCIR_SUBBUS_1; + break; + case PCIM_HDRTYPE_CARDBUS: + sec_reg = PCIR_SECBUS_2; + sub_reg = PCIR_SUBBUS_2; + break; + default: + return; + } + + /* + * If the existing bus range is valid, attempt to reserve it + * from our parent. If this fails for any reason, clear the + * secbus and subbus registers. + * + * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? + * This would at least preserve the existing sec_bus if it is + * valid. + */ + sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); + sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); + + /* Quirk handling. */ + switch (pci_get_devid(dev)) { + case 0x12258086: /* Intel 82454KX/GX (Orion) */ + sup_bus = pci_read_config(dev, 0x41, 1); + if (sup_bus != 0xff) { + sec_bus = sup_bus + 1; + sub_bus = sup_bus + 1; + PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); + PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); + } + break; + + case 0x00dd10de: + /* Compaq R3000 BIOS sets wrong subordinate bus number. */ + if ((cp = kern_getenv("smbios.planar.maker")) == NULL) + break; + if (strncmp(cp, "Compal", 6) != 0) { + freeenv(cp); + break; + } + freeenv(cp); + if ((cp = kern_getenv("smbios.planar.product")) == NULL) + break; + if (strncmp(cp, "08A0", 4) != 0) { + freeenv(cp); + break; + } + freeenv(cp); + if (sub_bus < 0xa) { + sub_bus = 0xa; + PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); + } + break; + } + + if (bootverbose) + printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); + if (sec_bus > 0 && sub_bus >= sec_bus) { + start = sec_bus; + end = sub_bus; + count = end - start + 1; + + resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); + + /* + * If requested, clear secondary bus registers in + * bridge devices to force a complete renumbering + * rather than reserving the existing range. However, + * preserve the existing size. + */ + if (pci_clear_buses) + goto clear; + + rid = 0; + res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, + start, end, count, 0); + if (res != NULL) + return; + + if (bootverbose) + device_printf(bus, + "pci%d:%d:%d:%d secbus failed to allocate\n", + pci_get_domain(dev), pci_get_bus(dev), + pci_get_slot(dev), pci_get_function(dev)); + } + +clear: + PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); + PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); +} + +static struct resource * +pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, + rman_res_t end, rman_res_t count, u_int flags) +{ + struct pci_devinfo *dinfo; + pcicfgregs *cfg; + struct resource_list *rl; + struct resource *res; + int sec_reg, sub_reg; + + dinfo = device_get_ivars(child); + cfg = &dinfo->cfg; + rl = &dinfo->resources; + switch (cfg->hdrtype & PCIM_HDRTYPE) { + case PCIM_HDRTYPE_BRIDGE: + sec_reg = PCIR_SECBUS_1; + sub_reg = PCIR_SUBBUS_1; + break; + case PCIM_HDRTYPE_CARDBUS: + sec_reg = PCIR_SECBUS_2; + sub_reg = PCIR_SUBBUS_2; + break; + default: + return (NULL); + } + + if (*rid != 0) + return (NULL); + + if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) + resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); + if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { + res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, + start, end, count, flags & ~RF_ACTIVE); + if (res == NULL) { + resource_list_delete(rl, PCI_RES_BUS, *rid); + device_printf(child, "allocating %ju bus%s failed\n", + count, count == 1 ? "" : "es"); + return (NULL); + } + if (bootverbose) + device_printf(child, + "Lazy allocation of %ju bus%s at %ju\n", count, + count == 1 ? "" : "es", rman_get_start(res)); + PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); + PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); + } + return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, + end, count, flags)); +} +#endif + +static int +pci_ea_bei_to_rid(device_t dev, int bei) +{ +#ifdef PCI_IOV + struct pci_devinfo *dinfo; + int iov_pos; + struct pcicfg_iov *iov; + + dinfo = device_get_ivars(dev); + iov = dinfo->cfg.iov; + if (iov != NULL) + iov_pos = iov->iov_pos; + else + iov_pos = 0; +#endif + + /* Check if matches BAR */ + if ((bei >= PCIM_EA_BEI_BAR_0) && + (bei <= PCIM_EA_BEI_BAR_5)) + return (PCIR_BAR(bei)); + + /* Check ROM */ + if (bei == PCIM_EA_BEI_ROM) + return (PCIR_BIOS); + +#ifdef PCI_IOV + /* Check if matches VF_BAR */ + if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && + (bei <= PCIM_EA_BEI_VF_BAR_5)) + return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + + iov_pos); +#endif + + return (-1); +} + +int +pci_ea_is_enabled(device_t dev, int rid) +{ + struct pci_ea_entry *ea; + struct pci_devinfo *dinfo; + + dinfo = device_get_ivars(dev); + + STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { + if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) + return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); + } + + return (0); +} + +void +pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) +{ + struct pci_ea_entry *ea; + struct pci_devinfo *dinfo; + pci_addr_t start, end, count; + struct resource_list *rl; + int type, flags, rid; + struct resource *res; + uint32_t tmp; +#ifdef PCI_IOV + struct pcicfg_iov *iov; +#endif + + dinfo = device_get_ivars(dev); + rl = &dinfo->resources; + flags = 0; + +#ifdef PCI_IOV + iov = dinfo->cfg.iov; +#endif + + if (dinfo->cfg.ea.ea_location == 0) + return; + + STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { + + /* + * TODO: Ignore EA-BAR if is not enabled. + * Currently the EA implementation supports + * only situation, where EA structure contains + * predefined entries. In case they are not enabled + * leave them unallocated and proceed with + * a legacy-BAR mechanism. + */ + if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) + continue; + + switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { + case PCIM_EA_P_MEM_PREFETCH: + case PCIM_EA_P_VF_MEM_PREFETCH: + flags = RF_PREFETCHABLE; + /* FALLTHROUGH */ + case PCIM_EA_P_VF_MEM: + case PCIM_EA_P_MEM: + type = SYS_RES_MEMORY; + break; + case PCIM_EA_P_IO: + type = SYS_RES_IOPORT; + break; + default: + continue; + } + + if (alloc_iov != 0) { +#ifdef PCI_IOV + /* Allocating IOV, confirm BEI matches */ + if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || + (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) + continue; +#else + continue; +#endif + } else { + /* Allocating BAR, confirm BEI matches */ + if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || + (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && + (ea->eae_bei != PCIM_EA_BEI_ROM)) + continue; + } + + rid = pci_ea_bei_to_rid(dev, ea->eae_bei); + if (rid < 0) + continue; + + /* Skip resources already allocated by EA */ + if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || + (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) + continue; + + start = ea->eae_base; + count = ea->eae_max_offset + 1; +#ifdef PCI_IOV + if (iov != NULL) + count = count * iov->iov_num_vfs; +#endif + end = start + count - 1; + if (count == 0) + continue; + + resource_list_add(rl, type, rid, start, end, count); + res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, + flags); + if (res == NULL) { + resource_list_delete(rl, type, rid); + + /* + * Failed to allocate using EA, disable entry. + * Another attempt to allocation will be performed + * further, but this time using legacy BAR registers + */ + tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); + tmp &= ~PCIM_EA_ENABLE; + pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); + + /* + * Disabling entry might fail in case it is hardwired. + * Read flags again to match current status. + */ + ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); + + continue; + } + + /* As per specification, fill BAR with zeros */ + pci_write_config(dev, rid, 0, 4); + } +} + void pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) { @@ -3174,6 +3804,9 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) rl = &dinfo->resources; devid = (cfg->device << 16) | cfg->vendor; + /* Allocate resources using Enhanced Allocation */ + pci_add_resources_ea(bus, dev, 0); + /* ATA devices needs special map treatment */ if ((pci_get_class(dev) == PCIC_STORAGE) && (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && @@ -3183,6 +3816,14 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) pci_ata_maps(bus, dev, rl, force, prefetchmask); else for (i = 0; i < cfg->nummaps;) { + /* Skip resources already managed by EA */ + if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || + (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || + pci_ea_is_enabled(dev, PCIR_BAR(i))) { + i++; + continue; + } + /* * Skip quirked resources. */ @@ -3233,10 +3874,31 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) uhci_early_takeover(dev); #endif /* __rtems__ */ } + +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) + /* + * Reserve resources for secondary bus ranges behind bridge + * devices. + */ + pci_reserve_secbus(bus, dev, cfg, rl); +#endif +} + +static struct pci_devinfo * +pci_identify_function(device_t pcib, device_t dev, int domain, int busno, + int slot, int func) +{ + struct pci_devinfo *dinfo; + + dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); + if (dinfo != NULL) + pci_add_child(dev, dinfo); + + return (dinfo); } void -pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) +pci_add_children(device_t dev, int domain, int busno) { #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) device_t pcib = device_get_parent(dev); @@ -3244,11 +3906,26 @@ pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) int maxslots; int s, f, pcifunchigh; uint8_t hdrtype; + int first_func; + + /* + * Try to detect a device at slot 0, function 0. If it exists, try to + * enable ARI. We must enable ARI before detecting the rest of the + * functions on this bus as ARI changes the set of slots and functions + * that are legal on this bus. + */ + dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); + if (dinfo != NULL && pci_enable_ari) + PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); + + /* + * Start looking for new devices on slot 0 at function 1 because we + * just identified the device at slot 0, function 0. + */ + first_func = 1; - KASSERT(dinfo_size >= sizeof(struct pci_devinfo), - ("dinfo_size too small")); maxslots = PCIB_MAXSLOTS(pcib); - for (s = 0; s <= maxslots; s++) { + for (s = 0; s <= maxslots; s++, first_func = 0) { pcifunchigh = 0; f = 0; DELAY(1); @@ -3256,18 +3933,143 @@ pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) continue; if (hdrtype & PCIM_MFDEV) - pcifunchigh = PCI_FUNCMAX; + pcifunchigh = PCIB_MAXFUNCS(pcib); + for (f = first_func; f <= pcifunchigh; f++) + pci_identify_function(pcib, dev, domain, busno, s, f); + } +#undef REG +} + +int +pci_rescan_method(device_t dev) +{ +#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) + device_t pcib = device_get_parent(dev); + struct pci_softc *sc; + device_t child, *devlist, *unchanged; + int devcount, error, i, j, maxslots, oldcount; + int busno, domain, s, f, pcifunchigh; + uint8_t hdrtype; + + /* No need to check for ARI on a rescan. */ + error = device_get_children(dev, &devlist, &devcount); + if (error) + return (error); + if (devcount != 0) { + unchanged = malloc(devcount * sizeof(device_t), M_TEMP, + M_NOWAIT | M_ZERO); + if (unchanged == NULL) { + free(devlist, M_TEMP); + return (ENOMEM); + } + } else + unchanged = NULL; + + sc = device_get_softc(dev); + domain = pcib_get_domain(dev); + busno = pcib_get_bus(dev); + maxslots = PCIB_MAXSLOTS(pcib); + for (s = 0; s <= maxslots; s++) { + /* If function 0 is not present, skip to the next slot. */ + f = 0; + if (REG(PCIR_VENDOR, 2) == 0xffff) + continue; + pcifunchigh = 0; + hdrtype = REG(PCIR_HDRTYPE, 1); + if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) + continue; + if (hdrtype & PCIM_MFDEV) + pcifunchigh = PCIB_MAXFUNCS(pcib); for (f = 0; f <= pcifunchigh; f++) { - dinfo = pci_read_device(pcib, domain, busno, s, f, - dinfo_size); - if (dinfo != NULL) { - pci_add_child(dev, dinfo); + if (REG(PCIR_VENDOR, 2) == 0xfff) + continue; + + /* + * Found a valid function. Check if a + * device_t for this device already exists. + */ + for (i = 0; i < devcount; i++) { + child = devlist[i]; + if (child == NULL) + continue; + if (pci_get_slot(child) == s && + pci_get_function(child) == f) { + unchanged[i] = child; + goto next_func; + } } + + pci_identify_function(pcib, dev, domain, busno, s, f); + next_func:; } } + + /* Remove devices that are no longer present. */ + for (i = 0; i < devcount; i++) { + if (unchanged[i] != NULL) + continue; + device_delete_child(dev, devlist[i]); + } + + free(devlist, M_TEMP); + oldcount = devcount; + + /* Try to attach the devices just added. */ + error = device_get_children(dev, &devlist, &devcount); + if (error) { + free(unchanged, M_TEMP); + return (error); + } + + for (i = 0; i < devcount; i++) { + for (j = 0; j < oldcount; j++) { + if (devlist[i] == unchanged[j]) + goto next_device; + } + + device_probe_and_attach(devlist[i]); + next_device:; + } + + free(unchanged, M_TEMP); + free(devlist, M_TEMP); + return (0); #undef REG } +#ifdef PCI_IOV +device_t +pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, + uint16_t did) +{ + struct pci_devinfo *pf_dinfo, *vf_dinfo; + device_t pcib; + int busno, slot, func; + + pf_dinfo = device_get_ivars(pf); + + pcib = device_get_parent(bus); + + PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); + + vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, + slot, func, vid, did); + + vf_dinfo->cfg.flags |= PCICFG_VF; + pci_add_child(bus, vf_dinfo); + + return (vf_dinfo->cfg.dev); +} + +device_t +pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, + uint16_t vid, uint16_t did) +{ + + return (pci_add_iov_child(bus, pf, rid, vid, did)); +} +#endif + void pci_add_child(device_t bus, struct pci_devinfo *dinfo) { @@ -3278,6 +4080,13 @@ pci_add_child(device_t bus, struct pci_devinfo *dinfo) pci_cfg_restore(dinfo->cfg.dev, dinfo); pci_print_verbose(dinfo); pci_add_resources(bus, dinfo->cfg.dev, 0, 0); + pci_child_added(dinfo->cfg.dev); +} + +void +pci_child_added_method(device_t dev, device_t child) +{ + } static int @@ -3298,10 +4107,22 @@ pci_attach_common(device_t dev) #ifdef PCI_DMA_BOUNDARY int error, tag_valid; #endif +#ifdef PCI_RES_BUS + int rid; +#endif sc = device_get_softc(dev); domain = pcib_get_domain(dev); busno = pcib_get_bus(dev); +#ifdef PCI_RES_BUS + rid = 0; + sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, + 1, 0); + if (sc->sc_bus == NULL) { + device_printf(dev, "failed to allocate bus number\n"); + return (ENXIO); + } +#endif if (bootverbose) device_printf(dev, "domain=%d, physical bus=%d\n", domain, busno); @@ -3335,24 +4156,42 @@ pci_attach(device_t dev) return (error); /* - * Since there can be multiple independantly numbered PCI + * Since there can be multiple independently numbered PCI * busses on systems with multiple PCI domains, we can't use * the unit number to decide which bus we are probing. We ask * the parent pcib what our domain and bus numbers are. */ domain = pcib_get_domain(dev); busno = pcib_get_bus(dev); - pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo)); + pci_add_children(dev, domain, busno); return (bus_generic_attach(dev)); } +static int +pci_detach(device_t dev) +{ +#ifdef PCI_RES_BUS + struct pci_softc *sc; +#endif + int error; + + error = bus_generic_detach(dev); + if (error) + return (error); +#ifdef PCI_RES_BUS + sc = device_get_softc(dev); + error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); + if (error) + return (error); +#endif + return (device_delete_children(dev)); +} + static void -pci_set_power_children(device_t dev, device_t *devlist, int numdevs, - int state) +pci_set_power_child(device_t dev, device_t child, int state) { - device_t child, pcib; - struct pci_devinfo *dinfo; - int dstate, i; + device_t pcib; + int dstate; /* * Set the device to the given state. If the firmware suggests @@ -3362,45 +4201,53 @@ pci_set_power_children(device_t dev, device_t *devlist, int numdevs, * are handled separately. */ pcib = device_get_parent(dev); - for (i = 0; i < numdevs; i++) { - child = devlist[i]; - dinfo = device_get_ivars(child); - dstate = state; - if (device_is_attached(child) && - PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) - pci_set_powerstate(child, dstate); - } + dstate = state; + if (device_is_attached(child) && + PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) + pci_set_powerstate(child, dstate); } int -pci_suspend(device_t dev) +pci_suspend_child(device_t dev, device_t child) { - device_t child, *devlist; struct pci_devinfo *dinfo; - int error, i, numdevs; + int error; + + dinfo = device_get_ivars(child); /* - * Save the PCI configuration space for each child and set the + * Save the PCI configuration space for the child and set the * device in the appropriate power state for this sleep state. */ - if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) - return (error); - for (i = 0; i < numdevs; i++) { - child = devlist[i]; - dinfo = device_get_ivars(child); - pci_cfg_save(child, dinfo, 0); - } + pci_cfg_save(child, dinfo, 0); /* Suspend devices before potentially powering them down. */ - error = bus_generic_suspend(dev); - if (error) { - free(devlist, M_TEMP); + error = bus_generic_suspend_child(dev, child); + + if (error) return (error); - } + if (pci_do_power_suspend) - pci_set_power_children(dev, devlist, numdevs, - PCI_POWERSTATE_D3); - free(devlist, M_TEMP); + pci_set_power_child(dev, child, PCI_POWERSTATE_D3); + + return (0); +} + +int +pci_resume_child(device_t dev, device_t child) +{ + struct pci_devinfo *dinfo; + + if (pci_do_power_resume) + pci_set_power_child(dev, child, PCI_POWERSTATE_D0); + + dinfo = device_get_ivars(child); + pci_cfg_restore(child, dinfo); + if (!device_is_attached(child)) + pci_cfg_save(child, dinfo, 1); + + bus_generic_resume_child(dev, child); + return (0); } @@ -3408,27 +4255,10 @@ int pci_resume(device_t dev) { device_t child, *devlist; - struct pci_devinfo *dinfo; int error, i, numdevs; - /* - * Set each child to D0 and restore its PCI configuration space. - */ if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) return (error); - if (pci_do_power_resume) - pci_set_power_children(dev, devlist, numdevs, - PCI_POWERSTATE_D0); - - /* Now the device is powered up, restore its config space. */ - for (i = 0; i < numdevs; i++) { - child = devlist[i]; - dinfo = device_get_ivars(child); - - pci_cfg_restore(child, dinfo); - if (!device_is_attached(child)) - pci_cfg_save(child, dinfo, 1); - } /* * Resume critical devices first, then everything else later. @@ -3440,7 +4270,7 @@ pci_resume(device_t dev) case PCIC_MEMORY: case PCIC_BRIDGE: case PCIC_BASEPERIPH: - DEVICE_RESUME(child); + BUS_RESUME_CHILD(dev, child); break; } } @@ -3453,7 +4283,7 @@ pci_resume(device_t dev) case PCIC_BASEPERIPH: break; default: - DEVICE_RESUME(child); + BUS_RESUME_CHILD(dev, child); } } free(devlist, M_TEMP); @@ -3504,7 +4334,7 @@ pci_driver_added(device_t dev, driver_t *driver) pci_printf(&dinfo->cfg, "reprobing on driver added\n"); pci_cfg_restore(child, dinfo); if (device_probe_and_attach(child) != 0) - pci_cfg_save(child, dinfo, 1); + pci_child_detached(dev, child); } free(devlist, M_TEMP); } @@ -3680,15 +4510,16 @@ pci_print_child(device_t dev, device_t child) retval += bus_print_child_header(dev, child); - retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); - retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); - retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); + retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); + retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); + retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); if (device_get_flags(dev)) retval += printf(" flags %#x", device_get_flags(dev)); retval += printf(" at device %d.%d", pci_get_slot(child), pci_get_function(child)); + retval += bus_print_child_domain(dev, child); retval += bus_print_child_footer(dev, child); return (retval); @@ -3754,6 +4585,7 @@ static const struct {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, + {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, {PCIC_INPUTDEV, -1, 1, "input device"}, {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, @@ -3835,6 +4667,38 @@ pci_probe_nomatch(device_t dev, device_t child) pci_cfg_save(child, device_get_ivars(child), 1); } +void +pci_child_detached(device_t dev, device_t child) +{ + struct pci_devinfo *dinfo; + struct resource_list *rl; + + dinfo = device_get_ivars(child); + rl = &dinfo->resources; + + /* + * Have to deallocate IRQs before releasing any MSI messages and + * have to release MSI messages before deallocating any memory + * BARs. + */ + if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) + pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); + if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { + pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); + (void)pci_release_msi(child); + } + if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) + pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); + if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) + pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); +#ifdef PCI_RES_BUS + if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) + pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); +#endif + + pci_cfg_save(child, dinfo, 1); +} + /* * Parse the PCI device database, if loaded, and return a pointer to a * description of the device. @@ -4031,9 +4895,17 @@ pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) *result = cfg->cachelnsz; break; case PCI_IVAR_MINGNT: + if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { + *result = -1; + return (EINVAL); + } *result = cfg->mingnt; break; case PCI_IVAR_MAXLAT: + if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { + *result = -1; + return (EINVAL); + } *result = cfg->maxlat; break; case PCI_IVAR_LATTIMER: @@ -4130,7 +5002,8 @@ DB_SHOW_COMMAND(pciregs, db_pci_dump) static struct resource * pci_reserve_map(device_t dev, device_t child, int type, int *rid, - u_long start, u_long end, u_long count, u_int flags) + rman_res_t start, rman_res_t end, rman_res_t count, u_int num, + u_int flags) { struct pci_devinfo *dinfo = device_get_ivars(child); struct resource_list *rl = &dinfo->resources; @@ -4140,6 +5013,11 @@ pci_reserve_map(device_t dev, device_t child, int type, int *rid, int mapsize; res = NULL; + + /* If rid is managed by EA, ignore it */ + if (pci_ea_is_enabled(child, *rid)) + goto out; + pm = pci_find_bar(child, *rid); if (pm != NULL) { /* This is a BAR that we failed to allocate earlier. */ @@ -4154,7 +5032,7 @@ pci_reserve_map(device_t dev, device_t child, int type, int *rid, * have a atapci device in legacy mode and it fails * here, that other code is broken. */ - pci_read_bar(child, *rid, &map, &testval); + pci_read_bar(child, *rid, &map, &testval, NULL); /* * Determine the size of the BAR and ignore BARs with a size @@ -4196,7 +5074,7 @@ pci_reserve_map(device_t dev, device_t child, int type, int *rid, * situation where we might allocate the excess to * another driver, which won't work. */ - count = (pci_addr_t)1 << mapsize; + count = ((pci_addr_t)1 << mapsize) * num; if (RF_ALIGNMENT(flags) < mapsize) flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) @@ -4221,13 +5099,13 @@ pci_reserve_map(device_t dev, device_t child, int type, int *rid, if (res == NULL) { resource_list_delete(rl, type, *rid); device_printf(child, - "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", + "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", count, *rid, type, start, end); goto out; } if (bootverbose) device_printf(child, - "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", + "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", count, *rid, type, rman_get_start(res)); map = rman_get_start(res); pci_write_bar(child, pm, map); @@ -4236,8 +5114,9 @@ out: } struct resource * -pci_alloc_resource(device_t dev, device_t child, int type, int *rid, - u_long start, u_long end, u_long count, u_int flags) +pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, + rman_res_t start, rman_res_t end, rman_res_t count, u_long num, + u_int flags) { struct pci_devinfo *dinfo; struct resource_list *rl; @@ -4245,10 +5124,6 @@ pci_alloc_resource(device_t dev, device_t child, int type, int *rid, struct resource *res; pcicfgregs *cfg; - if (device_get_parent(child) != dev) - return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, - type, rid, start, end, count, flags)); - /* * Perform lazy resource allocation */ @@ -4256,6 +5131,11 @@ pci_alloc_resource(device_t dev, device_t child, int type, int *rid, rl = &dinfo->resources; cfg = &dinfo->cfg; switch (type) { +#if defined(NEW_PCIB) && defined(PCI_RES_BUS) + case PCI_RES_BUS: + return (pci_alloc_secbus(dev, child, rid, start, end, count, + flags)); +#endif case SYS_RES_IRQ: /* * Can't alloc legacy interrupt once MSI messages have @@ -4300,7 +5180,7 @@ pci_alloc_resource(device_t dev, device_t child, int type, int *rid, rle = resource_list_find(rl, type, *rid); if (rle == NULL) { res = pci_reserve_map(dev, child, type, rid, start, end, - count, flags); + count, num, flags); if (res == NULL) return (NULL); } @@ -4309,6 +5189,38 @@ pci_alloc_resource(device_t dev, device_t child, int type, int *rid, start, end, count, flags)); } +struct resource * +pci_alloc_resource(device_t dev, device_t child, int type, int *rid, + rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) +{ +#ifdef PCI_IOV + struct pci_devinfo *dinfo; +#endif + + if (device_get_parent(child) != dev) + return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, + type, rid, start, end, count, flags)); + +#ifdef PCI_IOV + dinfo = device_get_ivars(child); + if (dinfo->cfg.flags & PCICFG_VF) { + switch (type) { + /* VFs can't have I/O BARs. */ + case SYS_RES_IOPORT: + return (NULL); + case SYS_RES_MEMORY: + return (pci_vf_alloc_mem_resource(dev, child, rid, + start, end, count, flags)); + } + + /* Fall through for other types of resource allocations. */ + } +#endif + + return (pci_alloc_multi_resource(dev, child, type, rid, start, end, + count, 1, flags)); +} + int pci_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r) @@ -4323,6 +5235,22 @@ pci_release_resource(device_t dev, device_t child, int type, int rid, dinfo = device_get_ivars(child); cfg = &dinfo->cfg; + +#ifdef PCI_IOV + if (dinfo->cfg.flags & PCICFG_VF) { + switch (type) { + /* VFs can't have I/O BARs. */ + case SYS_RES_IOPORT: + return (EDOOFUS); + case SYS_RES_MEMORY: + return (pci_vf_release_mem_resource(dev, child, rid, + r)); + } + + /* Fall through for other types of resource allocations. */ + } +#endif + #ifdef NEW_PCIB /* * PCI-PCI bridge I/O window resources are not BARs. For @@ -4383,7 +5311,7 @@ pci_deactivate_resource(device_t dev, device_t child, int type, if (error) return (error); - /* Disable decoding for device ROMs. */ + /* Disable decoding for device ROMs. */ if (device_get_parent(child) == dev) { dinfo = device_get_ivars(child); if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) @@ -4394,7 +5322,7 @@ pci_deactivate_resource(device_t dev, device_t child, int type, } void -pci_delete_child(device_t dev, device_t child) +pci_child_deleted(device_t dev, device_t child) { struct resource_list_entry *rle; struct resource_list *rl; @@ -4403,12 +5331,13 @@ pci_delete_child(device_t dev, device_t child) dinfo = device_get_ivars(child); rl = &dinfo->resources; - if (device_is_attached(child)) - device_detach(child); - /* Turn off access to resources we're about to free */ - pci_write_config(child, PCIR_COMMAND, pci_read_config(child, - PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); + if (bus_child_present(child) != 0) { + pci_write_config(child, PCIR_COMMAND, pci_read_config(child, + PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); + + pci_disable_busmaster(child); + } /* Free all allocated resources */ STAILQ_FOREACH(rle, rl, link) { @@ -4429,7 +5358,6 @@ pci_delete_child(device_t dev, device_t child) } resource_list_free(rl); - device_delete_child(dev, child); pci_freecfg(dinfo); } @@ -4454,7 +5382,7 @@ pci_delete_resource(device_t dev, device_t child, int type, int rid) resource_list_busy(rl, type, rid)) { device_printf(dev, "delete_resource: " "Resource still owned by child, oops. " - "(type=%d, rid=%d, addr=%lx)\n", + "(type=%d, rid=%d, addr=%jx)\n", type, rid, rman_get_start(rle->res)); return; } @@ -4485,6 +5413,37 @@ pci_read_config_method(device_t dev, device_t child, int reg, int width) struct pci_devinfo *dinfo = device_get_ivars(child); pcicfgregs *cfg = &dinfo->cfg; +#ifdef PCI_IOV + /* + * SR-IOV VFs don't implement the VID or DID registers, so we have to + * emulate them here. + */ + if (cfg->flags & PCICFG_VF) { + if (reg == PCIR_VENDOR) { + switch (width) { + case 4: + return (cfg->device << 16 | cfg->vendor); + case 2: + return (cfg->vendor); + case 1: + return (cfg->vendor & 0xff); + default: + return (0xffffffff); + } + } else if (reg == PCIR_DEVICE) { + switch (width) { + /* Note that an unaligned 4-byte read is an error. */ + case 2: + return (cfg->device); + case 1: + return (cfg->device & 0xff); + default: + return (0xffffffff); + } + } + } +#endif + return (PCIB_READ_CONFIG(device_get_parent(dev), cfg->bus, cfg->slot, cfg->func, reg, width)); } @@ -4505,8 +5464,9 @@ pci_child_location_str_method(device_t dev, device_t child, char *buf, size_t buflen) { - snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), - pci_get_function(child)); + snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", + pci_get_slot(child), pci_get_function(child), pci_get_domain(child), + pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); return (0); } @@ -4536,10 +5496,60 @@ pci_assign_interrupt_method(device_t dev, device_t child) cfg->intpin)); } +static void +pci_lookup(void *arg, const char *name, device_t *dev) +{ + long val; + char *end; + int domain, bus, slot, func; + + if (*dev != NULL) + return; + + /* + * Accept pciconf-style selectors of either pciD:B:S:F or + * pciB:S:F. In the latter case, the domain is assumed to + * be zero. + */ + if (strncmp(name, "pci", 3) != 0) + return; + val = strtol(name + 3, &end, 10); + if (val < 0 || val > INT_MAX || *end != ':') + return; + domain = val; + val = strtol(end + 1, &end, 10); + if (val < 0 || val > INT_MAX || *end != ':') + return; + bus = val; + val = strtol(end + 1, &end, 10); + if (val < 0 || val > INT_MAX) + return; + slot = val; + if (*end == ':') { + val = strtol(end + 1, &end, 10); + if (val < 0 || val > INT_MAX || *end != '\0') + return; + func = val; + } else if (*end == '\0') { + func = slot; + slot = bus; + bus = domain; + domain = 0; + } else + return; + + if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || + func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) + return; + + *dev = pci_find_dbsf(domain, bus, slot, func); +} + static int pci_modevent(module_t mod, int what, void *arg) { static struct cdev *pci_cdev; + static eventhandler_tag tag; switch (what) { case MOD_LOAD: @@ -4548,9 +5558,13 @@ pci_modevent(module_t mod, int what, void *arg) pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); pci_load_vendor_data(); + tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, + 1000); break; case MOD_UNLOAD: + if (tag != NULL) + EVENTHANDLER_DEREGISTER(dev_lookup, tag); destroy_dev(pci_cdev); break; } @@ -4558,21 +5572,54 @@ pci_modevent(module_t mod, int what, void *arg) return (0); } +static void +pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) +{ +#define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) + struct pcicfg_pcie *cfg; + int version, pos; + + cfg = &dinfo->cfg.pcie; + pos = cfg->pcie_location; + + version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; + + WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); + + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ENDPOINT || + cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) + WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); + + if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && + (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) + WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); + + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ROOT_EC) + WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); + + if (version > 1) { + WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); + WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); + WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); + } +#undef WREG +} + +static void +pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) +{ + pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, + dinfo->cfg.pcix.pcix_command, 2); +} + void pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) { /* - * Only do header type 0 devices. Type 1 devices are bridges, - * which we know need special treatment. Type 2 devices are - * cardbus bridges which also require special treatment. - * Other types are unknown, and we err on the side of safety - * by ignoring them. - */ - if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) - return; - - /* * Restore the device to full power mode. We must do this * before we restore the registers because moving from D3 to * D0 will cause the chip's BARs and some other registers to @@ -4582,22 +5629,108 @@ pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) */ if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) pci_set_powerstate(dev, PCI_POWERSTATE_D0); - pci_restore_bars(dev); pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); - pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); - pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); + switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { + case PCIM_HDRTYPE_NORMAL: + pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); + pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); + break; + case PCIM_HDRTYPE_BRIDGE: + pci_write_config(dev, PCIR_SECLAT_1, + dinfo->cfg.bridge.br_seclat, 1); + pci_write_config(dev, PCIR_SUBBUS_1, + dinfo->cfg.bridge.br_subbus, 1); + pci_write_config(dev, PCIR_SECBUS_1, + dinfo->cfg.bridge.br_secbus, 1); + pci_write_config(dev, PCIR_PRIBUS_1, + dinfo->cfg.bridge.br_pribus, 1); + pci_write_config(dev, PCIR_BRIDGECTL_1, + dinfo->cfg.bridge.br_control, 2); + break; + case PCIM_HDRTYPE_CARDBUS: + pci_write_config(dev, PCIR_SECLAT_2, + dinfo->cfg.bridge.br_seclat, 1); + pci_write_config(dev, PCIR_SUBBUS_2, + dinfo->cfg.bridge.br_subbus, 1); + pci_write_config(dev, PCIR_SECBUS_2, + dinfo->cfg.bridge.br_secbus, 1); + pci_write_config(dev, PCIR_PRIBUS_2, + dinfo->cfg.bridge.br_pribus, 1); + pci_write_config(dev, PCIR_BRIDGECTL_2, + dinfo->cfg.bridge.br_control, 2); + break; + } + pci_restore_bars(dev); + + /* + * Restore extended capabilities for PCI-Express and PCI-X + */ + if (dinfo->cfg.pcie.pcie_location != 0) + pci_cfg_restore_pcie(dev, dinfo); + if (dinfo->cfg.pcix.pcix_location != 0) + pci_cfg_restore_pcix(dev, dinfo); /* Restore MSI and MSI-X configurations if they are present. */ if (dinfo->cfg.msi.msi_location != 0) pci_resume_msi(dev); if (dinfo->cfg.msix.msix_location != 0) pci_resume_msix(dev); + +#ifdef PCI_IOV + if (dinfo->cfg.iov != NULL) + pci_iov_cfg_restore(dev, dinfo); +#endif +} + +static void +pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) +{ +#define RREG(n) pci_read_config(dev, pos + (n), 2) + struct pcicfg_pcie *cfg; + int version, pos; + + cfg = &dinfo->cfg.pcie; + pos = cfg->pcie_location; + + cfg->pcie_flags = RREG(PCIER_FLAGS); + + version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; + + cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); + + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ENDPOINT || + cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) + cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); + + if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && + (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) + cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); + + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ROOT_EC) + cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); + + if (version > 1) { + cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); + cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); + cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); + } +#undef RREG +} + +static void +pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) +{ + dinfo->cfg.pcix.pcix_command = pci_read_config(dev, + dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); } void @@ -4607,40 +5740,68 @@ pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) int ps; /* - * Only do header type 0 devices. Type 1 devices are bridges, which - * we know need special treatment. Type 2 devices are cardbus bridges - * which also require special treatment. Other types are unknown, and - * we err on the side of safety by ignoring them. Powering down - * bridges should not be undertaken lightly. - */ - if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) - return; - - /* * Some drivers apparently write to these registers w/o updating our * cached copy. No harm happens if we update the copy, so do so here * so we can restore them. The COMMAND register is modified by the * bus w/o updating the cache. This should represent the normally - * writable portion of the 'defined' part of type 0 headers. In - * theory we also need to save/restore the PCI capability structures - * we know about, but apart from power we don't know any that are - * writable. + * writable portion of the 'defined' part of type 0/1/2 headers. */ - dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); - dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); - dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); - dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); + switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { + case PCIM_HDRTYPE_NORMAL: + dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); + dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); + dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); + dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); + break; + case PCIM_HDRTYPE_BRIDGE: + dinfo->cfg.bridge.br_seclat = pci_read_config(dev, + PCIR_SECLAT_1, 1); + dinfo->cfg.bridge.br_subbus = pci_read_config(dev, + PCIR_SUBBUS_1, 1); + dinfo->cfg.bridge.br_secbus = pci_read_config(dev, + PCIR_SECBUS_1, 1); + dinfo->cfg.bridge.br_pribus = pci_read_config(dev, + PCIR_PRIBUS_1, 1); + dinfo->cfg.bridge.br_control = pci_read_config(dev, + PCIR_BRIDGECTL_1, 2); + break; + case PCIM_HDRTYPE_CARDBUS: + dinfo->cfg.bridge.br_seclat = pci_read_config(dev, + PCIR_SECLAT_2, 1); + dinfo->cfg.bridge.br_subbus = pci_read_config(dev, + PCIR_SUBBUS_2, 1); + dinfo->cfg.bridge.br_secbus = pci_read_config(dev, + PCIR_SECBUS_2, 1); + dinfo->cfg.bridge.br_pribus = pci_read_config(dev, + PCIR_PRIBUS_2, 1); + dinfo->cfg.bridge.br_control = pci_read_config(dev, + PCIR_BRIDGECTL_2, 2); + dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); + dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); + break; + } + + if (dinfo->cfg.pcie.pcie_location != 0) + pci_cfg_save_pcie(dev, dinfo); + + if (dinfo->cfg.pcix.pcix_location != 0) + pci_cfg_save_pcix(dev, dinfo); + +#ifdef PCI_IOV + if (dinfo->cfg.iov != NULL) + pci_iov_cfg_save(dev, dinfo); +#endif /* * don't set the state for display devices, base peripherals and @@ -4661,7 +5822,7 @@ pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) if (cls == PCIC_STORAGE) return; /*FALLTHROUGH*/ - case 2: /* Agressive about what to power down */ + case 2: /* Aggressive about what to power down */ if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || cls == PCIC_BASEPERIPH) return; @@ -4698,3 +5859,52 @@ pci_restore_state(device_t dev) dinfo = device_get_ivars(dev); pci_cfg_restore(dev, dinfo); } + +static int +pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, + uintptr_t *id) +{ + + return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); +} + +/* Find the upstream port of a given PCI device in a root complex. */ +device_t +pci_find_pcie_root_port(device_t dev) +{ + struct pci_devinfo *dinfo; + devclass_t pci_class; + device_t pcib, bus; + + pci_class = devclass_find("pci"); + KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, + ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); + + /* + * Walk the bridge hierarchy until we find a PCI-e root + * port or a non-PCI device. + */ + for (;;) { + bus = device_get_parent(dev); + KASSERT(bus != NULL, ("%s: null parent of %s", __func__, + device_get_nameunit(dev))); + + pcib = device_get_parent(bus); + KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, + device_get_nameunit(bus))); + + /* + * pcib's parent must be a PCI bus for this to be a + * PCI-PCI bridge. + */ + if (device_get_devclass(device_get_parent(pcib)) != pci_class) + return (NULL); + + dinfo = device_get_ivars(pcib); + if (dinfo->cfg.pcie.pcie_location != 0 && + dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) + return (pcib); + + dev = pcib; + } +} |