diff options
Diffstat (limited to 'freebsd/sys/dev/dwc/if_dwc.h')
| -rw-r--r-- | freebsd/sys/dev/dwc/if_dwc.h | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/freebsd/sys/dev/dwc/if_dwc.h b/freebsd/sys/dev/dwc/if_dwc.h index 2ba9860e..d88ca0db 100644 --- a/freebsd/sys/dev/dwc/if_dwc.h +++ b/freebsd/sys/dev/dwc/if_dwc.h @@ -34,23 +34,27 @@ * Register names were taken almost as is from the documentation. */ +#ifndef __IF_DWC_H__ +#define __IF_DWC_H__ + #define MAC_CONFIGURATION 0x0 #define CONF_JD (1 << 22) /* jabber timer disable */ #define CONF_BE (1 << 21) /* Frame Burst Enable */ #define CONF_PS (1 << 15) /* GMII/MII */ #define CONF_FES (1 << 14) /* MII speed select */ #define CONF_DM (1 << 11) /* Full Duplex Enable */ -#define CONF_IPC (1 << 10) /* Checksum Enable */ #define CONF_ACS (1 << 7) #define CONF_TE (1 << 3) #define CONF_RE (1 << 2) #define MAC_FRAME_FILTER 0x4 -#define FRAME_FILTER_RA (1 << 31) /* Receive All */ +#define FRAME_FILTER_RA (1U << 31) /* Receive All */ #define FRAME_FILTER_HPF (1 << 10) /* Hash or Perfect Filter */ #define FRAME_FILTER_PM (1 << 4) /* Pass multicast */ #define FRAME_FILTER_HMC (1 << 2) #define FRAME_FILTER_HUC (1 << 1) #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */ +#define GMAC_MAC_HTHIGH 0x08 +#define GMAC_MAC_HTLOW 0x0c #define GMII_ADDRESS 0x10 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */ #define GMII_ADDRESS_PA_SHIFT 11 @@ -208,9 +212,14 @@ /* DMA */ #define BUS_MODE 0x1000 #define BUS_MODE_EIGHTXPBL (1 << 24) /* Multiplies PBL by 8 */ +#define BUS_MODE_FIXEDBURST (1 << 16) +#define BUS_MODE_PRIORXTX_SHIFT 14 +#define BUS_MODE_PRIORXTX_41 3 +#define BUS_MODE_PRIORXTX_31 2 +#define BUS_MODE_PRIORXTX_21 1 +#define BUS_MODE_PRIORXTX_11 0 #define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */ #define BUS_MODE_PBL_BEATS_8 8 -#define BUS_MODE_ATDS (1 << 7) /* Alternate Descriptor Size */ #define BUS_MODE_SWR (1 << 0) /* Reset */ #define TRANSMIT_POLL_DEMAND 0x1004 #define RECEIVE_POLL_DEMAND 0x1008 @@ -220,7 +229,6 @@ #define DMA_STATUS_NIS (1 << 16) #define DMA_STATUS_AIS (1 << 15) #define DMA_STATUS_FBI (1 << 13) -#define DMA_STATUS_RU (1 << 7) #define DMA_STATUS_RI (1 << 6) #define DMA_STATUS_TI (1 << 0) #define DMA_STATUS_INTR_MASK 0x1ffff @@ -263,3 +271,22 @@ #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050 #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054 #define HW_FEATURE 0x1058 + +#define DWC_GMAC 0x1 +#define DWC_GMAC_ALT_DESC 0x2 +#define GMAC_MII_CLK_60_100M_DIV42 0x0 +#define GMAC_MII_CLK_100_150M_DIV62 0x1 +#define GMAC_MII_CLK_25_35M_DIV16 0x2 +#define GMAC_MII_CLK_35_60M_DIV26 0x3 +#define GMAC_MII_CLK_150_250M_DIV102 0x4 +#define GMAC_MII_CLK_250_300M_DIV124 0x5 +#define GMAC_MII_CLK_DIV4 0x8 +#define GMAC_MII_CLK_DIV6 0x9 +#define GMAC_MII_CLK_DIV8 0xa +#define GMAC_MII_CLK_DIV10 0xb +#define GMAC_MII_CLK_DIV12 0xc +#define GMAC_MII_CLK_DIV14 0xd +#define GMAC_MII_CLK_DIV16 0xe +#define GMAC_MII_CLK_DIV18 0xf + +#endif /* __IF_DWC_H__ */ |