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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-08-22 14:59:50 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-09-21 10:29:41 +0200
commit3489e3b6396ee9944a6a2e19e675ca54c36993b4 (patch)
treecd55cfac1c96ff4b888a9606fd6a0d8eb65bb446 /rtemsbsd
parentck: Define CK_MD_PPC32_LWSYNC if available (diff)
downloadrtems-libbsd-3489e3b6396ee9944a6a2e19e675ca54c36993b4.tar.bz2
Update to FreeBSD head 2018-09-17
Git mirror commit 6c2192b1ef8c50788c751f878552526800b1e319. Update #3472.
Diffstat (limited to 'rtemsbsd')
-rw-r--r--rtemsbsd/include/machine/rtems-bsd-kernel-namespace.h102
-rw-r--r--rtemsbsd/include/rtems/bsd/local/cryptodev_if.h36
-rw-r--r--rtemsbsd/include/rtems/bsd/local/sdhci_if.h24
-rw-r--r--rtemsbsd/include/rtems/bsd/local/usbdevs.h109
-rw-r--r--rtemsbsd/include/rtems/bsd/local/usbdevs_data.h546
-rw-r--r--rtemsbsd/include/sys/boot.h0
-rw-r--r--rtemsbsd/include/sys/epoch.h4
-rw-r--r--rtemsbsd/include/sys/kpilite.h0
-rw-r--r--rtemsbsd/include/vm/vm_pager.h0
-rw-r--r--rtemsbsd/local/cryptodev_if.c29
-rw-r--r--rtemsbsd/local/ifdi_if.c106
-rw-r--r--rtemsbsd/local/sdhci_if.c4
-rw-r--r--rtemsbsd/rtems/rtems-kernel-epoch.c25
-rw-r--r--rtemsbsd/sys/arm/at91/at91_mci.c1713
-rw-r--r--rtemsbsd/sys/arm/at91/at91_mcireg.h183
-rw-r--r--rtemsbsd/sys/arm/at91/at91_pdcreg.h50
-rw-r--r--rtemsbsd/sys/arm/at91/at91reg.h92
-rw-r--r--rtemsbsd/sys/arm/at91/at91var.h175
18 files changed, 3069 insertions, 129 deletions
diff --git a/rtemsbsd/include/machine/rtems-bsd-kernel-namespace.h b/rtemsbsd/include/machine/rtems-bsd-kernel-namespace.h
index f0c4ceb0..0a63324b 100644
--- a/rtemsbsd/include/machine/rtems-bsd-kernel-namespace.h
+++ b/rtemsbsd/include/machine/rtems-bsd-kernel-namespace.h
@@ -58,6 +58,7 @@
#define auth_hash_hmac_md5 _bsd_auth_hash_hmac_md5
#define auth_hash_hmac_ripemd_160 _bsd_auth_hash_hmac_ripemd_160
#define auth_hash_hmac_sha1 _bsd_auth_hash_hmac_sha1
+#define auth_hash_hmac_sha2_224 _bsd_auth_hash_hmac_sha2_224
#define auth_hash_hmac_sha2_256 _bsd_auth_hash_hmac_sha2_256
#define auth_hash_hmac_sha2_384 _bsd_auth_hash_hmac_sha2_384
#define auth_hash_hmac_sha2_512 _bsd_auth_hash_hmac_sha2_512
@@ -67,6 +68,12 @@
#define auth_hash_nist_gmac_aes_192 _bsd_auth_hash_nist_gmac_aes_192
#define auth_hash_nist_gmac_aes_256 _bsd_auth_hash_nist_gmac_aes_256
#define auth_hash_null _bsd_auth_hash_null
+#define auth_hash_poly1305 _bsd_auth_hash_poly1305
+#define auth_hash_sha1 _bsd_auth_hash_sha1
+#define auth_hash_sha2_224 _bsd_auth_hash_sha2_224
+#define auth_hash_sha2_256 _bsd_auth_hash_sha2_256
+#define auth_hash_sha2_384 _bsd_auth_hash_sha2_384
+#define auth_hash_sha2_512 _bsd_auth_hash_sha2_512
#define badport_bandlim _bsd_badport_bandlim
#define bcd2bin_data _bsd_bcd2bin_data
#define bce_COM_b06FwBss _bsd_bce_COM_b06FwBss
@@ -575,6 +582,7 @@
#define crypto_freesession _bsd_crypto_freesession
#define crypto_getcaps _bsd_crypto_getcaps
#define crypto_get_driverid _bsd_crypto_get_driverid
+#define crypto_get_driver_session _bsd_crypto_get_driver_session
#define crypto_getfeat _bsd_crypto_getfeat
#define crypto_getreq _bsd_crypto_getreq
#define crypto_kdispatch _bsd_crypto_kdispatch
@@ -583,12 +591,31 @@
#define crypto_mbuftoiov _bsd_crypto_mbuftoiov
#define crypto_modevent _bsd_crypto_modevent
#define crypto_newsession _bsd_crypto_newsession
+#define crypto_onetimeauth_poly1305 _bsd_crypto_onetimeauth_poly1305
+#define crypto_onetimeauth_poly1305_bytes _bsd_crypto_onetimeauth_poly1305_bytes
+#define crypto_onetimeauth_poly1305_donna_implementation _bsd_crypto_onetimeauth_poly1305_donna_implementation
+#define crypto_onetimeauth_poly1305_final _bsd_crypto_onetimeauth_poly1305_final
+#define crypto_onetimeauth_poly1305_init _bsd_crypto_onetimeauth_poly1305_init
+#define crypto_onetimeauth_poly1305_keybytes _bsd_crypto_onetimeauth_poly1305_keybytes
+#define crypto_onetimeauth_poly1305_keygen _bsd_crypto_onetimeauth_poly1305_keygen
+#define _crypto_onetimeauth_poly1305_pick_best_implementation _bsd__crypto_onetimeauth_poly1305_pick_best_implementation
+#define crypto_onetimeauth_poly1305_statebytes _bsd_crypto_onetimeauth_poly1305_statebytes
+#define crypto_onetimeauth_poly1305_update _bsd_crypto_onetimeauth_poly1305_update
+#define crypto_onetimeauth_poly1305_verify _bsd_crypto_onetimeauth_poly1305_verify
#define crypto_register _bsd_crypto_register
+#define crypto_ses2caps _bsd_crypto_ses2caps
+#define crypto_ses2hid _bsd_crypto_ses2hid
#define crypto_support _bsd_crypto_support
#define crypto_unblock _bsd_crypto_unblock
#define crypto_unregister _bsd_crypto_unregister
#define crypto_unregister_all _bsd_crypto_unregister_all
#define crypto_userasymcrypto _bsd_crypto_userasymcrypto
+#define crypto_verify_16 _bsd_crypto_verify_16
+#define crypto_verify_16_bytes _bsd_crypto_verify_16_bytes
+#define crypto_verify_32 _bsd_crypto_verify_32
+#define crypto_verify_32_bytes _bsd_crypto_verify_32_bytes
+#define crypto_verify_64 _bsd_crypto_verify_64
+#define crypto_verify_64_bytes _bsd_crypto_verify_64_bytes
#define ctl_subtype_name _bsd_ctl_subtype_name
#define cuio_apply _bsd_cuio_apply
#define cuio_copyback _bsd_cuio_copyback
@@ -1069,10 +1096,6 @@
#define enc_algorithm_lookup _bsd_enc_algorithm_lookup
#define encap4_input _bsd_encap4_input
#define encap6_input _bsd_encap6_input
-#define encap_attach _bsd_encap_attach
-#define encap_attach_func _bsd_encap_attach_func
-#define encap_detach _bsd_encap_detach
-#define encap_getarg _bsd_encap_getarg
#define enc_xform_3des _bsd_enc_xform_3des
#define enc_xform_aes_icm _bsd_enc_xform_aes_icm
#define enc_xform_aes_nist_gcm _bsd_enc_xform_aes_nist_gcm
@@ -1117,11 +1140,11 @@
#define evdev_client_push _bsd_evdev_client_push
#define evdev_dispose_client _bsd_evdev_dispose_client
#define evdev_event_supported _bsd_evdev_event_supported
-#define evdev_ev_kbd_event _bsd_evdev_ev_kbd_event
#define evdev_free _bsd_evdev_free
#define evdev_get_last_mt_slot _bsd_evdev_get_last_mt_slot
#define evdev_get_mt_slot_by_tracking_id _bsd_evdev_get_mt_slot_by_tracking_id
#define evdev_get_mt_value _bsd_evdev_get_mt_value
+#define evdev_get_softc _bsd_evdev_get_softc
#define evdev_grab_client _bsd_evdev_grab_client
#define evdev_hid2key _bsd_evdev_hid2key
#define evdev_inject_event _bsd_evdev_inject_event
@@ -1236,6 +1259,8 @@
#define frag6_drain _bsd_frag6_drain
#define frag6_init _bsd_frag6_init
#define frag6_input _bsd_frag6_input
+#define frag6_nfrags _bsd_frag6_nfrags
+#define frag6_set_bucketsize _bsd_frag6_set_bucketsize
#define frag6_slowtimo _bsd_frag6_slowtimo
#define free_unr _bsd_free_unr
#define genkbd_commonioctl _bsd_genkbd_commonioctl
@@ -1269,7 +1294,8 @@
#define gf128_mul4 _bsd_gf128_mul4
#define gf128_mul4b _bsd_gf128_mul4b
#define Giant _bsd_Giant
-#define gif_encapcheck _bsd_gif_encapcheck
+#define gif_hashdestroy _bsd_gif_hashdestroy
+#define gif_hashinit _bsd_gif_hashinit
#define gif_input _bsd_gif_input
#define gif_output _bsd_gif_output
#define global_epoch _bsd_global_epoch
@@ -1285,7 +1311,10 @@
#define gpiobus_init_softc _bsd_gpiobus_init_softc
#define gpiobus_release_pin _bsd_gpiobus_release_pin
#define gpio_check_flags _bsd_gpio_check_flags
+#define gre_hashdestroy _bsd_gre_hashdestroy
+#define gre_hashinit _bsd_gre_hashinit
#define gre_input _bsd_gre_input
+#define gre_updatehdr _bsd_gre_updatehdr
#define grouptaskqueue_enqueue _bsd_grouptaskqueue_enqueue
#define gtaskqueue_block _bsd_gtaskqueue_block
#define gtaskqueue_cancel _bsd_gtaskqueue_cancel
@@ -1927,6 +1956,7 @@
#define if_simloop _bsd_if_simloop
#define if_start _bsd_if_start
#define if_togglecapenable _bsd_if_togglecapenable
+#define if_tunnel_check_nesting _bsd_if_tunnel_check_nesting
#define ifunit _bsd_ifunit
#define ifunit_ref _bsd_ifunit_ref
#define if_up _bsd_if_up
@@ -1965,9 +1995,11 @@
#define in6_getscopezone _bsd_in6_getscopezone
#define in6_getsockaddr _bsd_in6_getsockaddr
#define in6_get_tmpifid _bsd_in6_get_tmpifid
-#define in6_gif_attach _bsd_in6_gif_attach
-#define in6_gif_encapcheck _bsd_in6_gif_encapcheck
+#define in6_gif_init _bsd_in6_gif_init
+#define in6_gif_ioctl _bsd_in6_gif_ioctl
#define in6_gif_output _bsd_in6_gif_output
+#define in6_gif_setopts _bsd_in6_gif_setopts
+#define in6_gif_uninit _bsd_in6_gif_uninit
#define in6_if2idlen _bsd_in6_if2idlen
#define in6_ifaddrhashtbl _bsd_in6_ifaddrhashtbl
#define in6_ifaddrhead _bsd_in6_ifaddrhead
@@ -2078,11 +2110,16 @@
#define inetsw _bsd_inetsw
#define in_getpeeraddr _bsd_in_getpeeraddr
#define in_getsockaddr _bsd_in_getsockaddr
-#define in_gif_attach _bsd_in_gif_attach
-#define in_gif_encapcheck _bsd_in_gif_encapcheck
+#define in_gif_init _bsd_in_gif_init
+#define in_gif_ioctl _bsd_in_gif_ioctl
#define in_gif_output _bsd_in_gif_output
-#define in_gre_attach _bsd_in_gre_attach
+#define in_gif_setopts _bsd_in_gif_setopts
+#define in_gif_uninit _bsd_in_gif_uninit
+#define in_gre_init _bsd_in_gre_init
+#define in_gre_ioctl _bsd_in_gre_ioctl
#define in_gre_output _bsd_in_gre_output
+#define in_gre_setopts _bsd_in_gre_setopts
+#define in_gre_uninit _bsd_in_gre_uninit
#define in_ifaddr_broadcast _bsd_in_ifaddr_broadcast
#define in_ifaddrhashtbl _bsd_in_ifaddrhashtbl
#define in_ifaddrhead _bsd_in_ifaddrhead
@@ -2161,6 +2198,7 @@
#define inp_setmoptions _bsd_inp_setmoptions
#define in_pseudo _bsd_in_pseudo
#define inp_so_options _bsd_inp_so_options
+#define inp_to_cpuid _bsd_inp_to_cpuid
#define inp_wlock _bsd_inp_wlock
#define inp_wunlock _bsd_inp_wunlock
#define in_rtalloc_ign _bsd_in_rtalloc_ign
@@ -2169,7 +2207,6 @@
#define in_sockaddr _bsd_in_sockaddr
#define intr_event_add_handler _bsd_intr_event_add_handler
#define intr_event_create _bsd_intr_event_create
-#define intr_event_execute_handlers _bsd_intr_event_execute_handlers
#define ip4_ah_net_deflev _bsd_ip4_ah_net_deflev
#define ip4_ah_trans_deflev _bsd_ip4_ah_trans_deflev
#define ip4_esp_net_deflev _bsd_ip4_esp_net_deflev
@@ -2191,6 +2228,8 @@
#define ip6_desync_factor _bsd_ip6_desync_factor
#define ip6_ecn_egress _bsd_ip6_ecn_egress
#define ip6_ecn_ingress _bsd_ip6_ecn_ingress
+#define ip6_encap_attach _bsd_ip6_encap_attach
+#define ip6_encap_detach _bsd_ip6_encap_detach
#define ip6_esp_net_deflev _bsd_ip6_esp_net_deflev
#define ip6_esp_trans_deflev _bsd_ip6_esp_trans_deflev
#define ip6_forward _bsd_ip6_forward
@@ -2208,8 +2247,10 @@
#define ip6_lasthdr _bsd_ip6_lasthdr
#define ip6_log_interval _bsd_ip6_log_interval
#define ip6_log_time _bsd_ip6_log_time
+#define ip6_maxfragbucketsize _bsd_ip6_maxfragbucketsize
#define ip6_maxfragpackets _bsd_ip6_maxfragpackets
#define ip6_maxfrags _bsd_ip6_maxfrags
+#define ip6_maxfragsperpacket _bsd_ip6_maxfragsperpacket
#define ip6_mcast_pmtu _bsd_ip6_mcast_pmtu
#define ip6_mforward _bsd_ip6_mforward
#define ip6_mloopback _bsd_ip6_mloopback
@@ -2271,6 +2312,8 @@
#define ip_drain _bsd_ip_drain
#define ip_ecn_egress _bsd_ip_ecn_egress
#define ip_ecn_ingress _bsd_ip_ecn_ingress
+#define ip_encap_attach _bsd_ip_encap_attach
+#define ip_encap_detach _bsd_ip_encap_detach
#define ip_fillid _bsd_ip_fillid
#define ip_forward _bsd_ip_forward
#define ipforwarding _bsd_ipforwarding
@@ -2390,6 +2433,7 @@
#define kbd_configure _bsd_kbd_configure
#define kbd_delete_driver _bsd_kbd_delete_driver
#define kbd_detach _bsd_kbd_detach
+#define kbd_ev_event _bsd_kbd_ev_event
#define kbd_find_keyboard _bsd_kbd_find_keyboard
#define kbd_find_keyboard2 _bsd_kbd_find_keyboard2
#define kbd_get_keyboard _bsd_kbd_get_keyboard
@@ -2556,6 +2600,9 @@
#define LibAliasSetTarget _bsd_LibAliasSetTarget
#define LibAliasUnaliasOut _bsd_LibAliasUnaliasOut
#define LibAliasUninit _bsd_LibAliasUninit
+#define _libmd_SHA224_Final _bsd__libmd_SHA224_Final
+#define _libmd_SHA224_Init _bsd__libmd_SHA224_Init
+#define _libmd_SHA224_Update _bsd__libmd_SHA224_Update
#define _libmd_SHA512_224_Final _bsd__libmd_SHA512_224_Final
#define _libmd_SHA512_224_Init _bsd__libmd_SHA512_224_Init
#define _libmd_SHA512_224_Update _bsd__libmd_SHA512_224_Update
@@ -2660,6 +2707,7 @@
#define m_demote_pkthdr _bsd_m_demote_pkthdr
#define M_DEVBUF _bsd_M_DEVBUF
#define m_devget _bsd_m_devget
+#define m_dispose_extcontrolm _bsd_m_dispose_extcontrolm
#define m_dup _bsd_m_dup
#define m_dup_pkthdr _bsd_m_dup_pkthdr
#define mesh_airtime_calc _bsd_mesh_airtime_calc
@@ -2673,6 +2721,8 @@
#define m_getjcl _bsd_m_getjcl
#define m_getm2 _bsd_m_getm2
#define m_getptr _bsd_m_getptr
+#define M_GIF _bsd_M_GIF
+#define M_GRE _bsd_M_GRE
#define mgt_subtype_name _bsd_mgt_subtype_name
#define M_IFADDR _bsd_M_IFADDR
#define M_IFMADDR _bsd_M_IFMADDR
@@ -3069,6 +3119,7 @@
#define pci_get_vpd_readonly_method _bsd_pci_get_vpd_readonly_method
#define pci_ht_map_msi _bsd_pci_ht_map_msi
#define pci_mapsize _bsd_pci_mapsize
+#define pci_match_device _bsd_pci_match_device
#define pci_msi_count_method _bsd_pci_msi_count_method
#define pci_msi_device_blacklisted _bsd_pci_msi_device_blacklisted
#define pci_msix_count_method _bsd_pci_msix_count_method
@@ -3078,6 +3129,7 @@
#define pci_numdevs _bsd_pci_numdevs
#define pci_pending_msix _bsd_pci_pending_msix
#define pci_print_child _bsd_pci_print_child
+#define pci_print_faulted_dev _bsd_pci_print_faulted_dev
#define pci_print_verbose _bsd_pci_print_verbose
#define pci_probe_nomatch _bsd_pci_probe_nomatch
#define pci_read_bar _bsd_pci_read_bar
@@ -3344,14 +3396,16 @@
#define pgsigio _bsd_pgsigio
#define phashinit _bsd_phashinit
#define phashinit_flags _bsd_phashinit_flags
-#define pim6_input _bsd_pim6_input
-#define pim_input _bsd_pim_input
#define pipe_dtor _bsd_pipe_dtor
#define pipe_named_ctor _bsd_pipe_named_ctor
#define pipeselwakeup _bsd_pipeselwakeup
#define pmtu_expire _bsd_pmtu_expire
#define pmtu_probe _bsd_pmtu_probe
#define poll_no_poll _bsd_poll_no_poll
+#define Poly1305_Final _bsd_Poly1305_Final
+#define Poly1305_Init _bsd_Poly1305_Init
+#define Poly1305_Setkey _bsd_Poly1305_Setkey
+#define Poly1305_Update _bsd_Poly1305_Update
#define ppsratecheck _bsd_ppsratecheck
#define preload_addr_relocate _bsd_preload_addr_relocate
#define preload_bootstrap_relocate _bsd_preload_bootstrap_relocate
@@ -3461,6 +3515,7 @@
#define r12au_init_ampdu _bsd_r12au_init_ampdu
#define r12au_init_ampdu_fwhw _bsd_r12au_init_ampdu_fwhw
#define r12au_init_burstlen _bsd_r12au_init_burstlen
+#define r12au_init_burstlen_usb2 _bsd_r12au_init_burstlen_usb2
#define r12au_init_rx_agg _bsd_r12au_init_rx_agg
#define r12au_post_init _bsd_r12au_post_init
#define r12a_vap_preattach _bsd_r12a_vap_preattach
@@ -3482,7 +3537,6 @@
#define r21a_set_led _bsd_r21a_set_led
#define r21au_attach _bsd_r21au_attach
#define r21au_chan_check _bsd_r21au_chan_check
-#define r21au_init_burstlen _bsd_r21au_init_burstlen
#define r21au_init_tx_agg _bsd_r21au_init_tx_agg
#define r21au_newstate _bsd_r21au_newstate
#define r21au_scan_end _bsd_r21au_scan_end
@@ -3912,6 +3966,8 @@
#define sbsetopt _bsd_sbsetopt
#define sbsndmbuf _bsd_sbsndmbuf
#define sbsndptr _bsd_sbsndptr
+#define sbsndptr_adv _bsd_sbsndptr_adv
+#define sbsndptr_noadv _bsd_sbsndptr_noadv
#define sbtoxsockbuf _bsd_sbtoxsockbuf
#define sbt_tickthreshold _bsd_sbt_tickthreshold
#define sbt_timethreshold _bsd_sbt_timethreshold
@@ -4032,6 +4088,7 @@
#define sctp_addr_mgmt_ep_sa _bsd_sctp_addr_mgmt_ep_sa
#define sctp_add_stream_reset_result _bsd_sctp_add_stream_reset_result
#define sctp_add_stream_reset_result_tsn _bsd_sctp_add_stream_reset_result_tsn
+#define sctp_add_substate _bsd_sctp_add_substate
#define sctp_add_to_readq _bsd_sctp_add_to_readq
#define sctp_add_vtag_to_timewait _bsd_sctp_add_vtag_to_timewait
#define SctpAlias _bsd_SctpAlias
@@ -4296,6 +4353,7 @@
#define sctp_set_primary_addr _bsd_sctp_set_primary_addr
#define sctp_set_primary_ip_address_sa _bsd_sctp_set_primary_ip_address_sa
#define sctp_set_rwnd _bsd_sctp_set_rwnd
+#define sctp_set_state _bsd_sctp_set_state
#define SctpShowAliasStats _bsd_SctpShowAliasStats
#define sctp_show_key _bsd_sctp_show_key
#define sctp_shutdown _bsd_sctp_shutdown
@@ -4480,6 +4538,8 @@
#define soconnectat _bsd_soconnectat
#define socreate _bsd_socreate
#define sodisconnect _bsd_sodisconnect
+#define sodium_memzero _bsd_sodium_memzero
+#define sodtor_set _bsd_sodtor_set
#define sodupsockaddr _bsd_sodupsockaddr
#define so_error_get _bsd_so_error_get
#define so_error_set _bsd_so_error_set
@@ -4708,7 +4768,6 @@
#define taskqgroup_detach _bsd_taskqgroup_detach
#define TB_DRAIN_WAITER _bsd_TB_DRAIN_WAITER
#define tbr_dequeue_ptr _bsd_tbr_dequeue_ptr
-#define tbr_get _bsd_tbr_get
#define tbr_set _bsd_tbr_set
#define tcb _bsd_tcb
#define tcbinfo _bsd_tcbinfo
@@ -4764,7 +4823,6 @@
#define tcp_hc_updatemtu _bsd_tcp_hc_updatemtu
#define tcp_init _bsd_tcp_init
#define tcp_initcwnd_segments _bsd_tcp_initcwnd_segments
-#define tcp_inpinfo_lock_add _bsd_tcp_inpinfo_lock_add
#define tcp_inpinfo_lock_del _bsd_tcp_inpinfo_lock_del
#define tcp_inptoxtp _bsd_tcp_inptoxtp
#define tcp_input _bsd_tcp_input
@@ -4792,6 +4850,7 @@
#define tcp_maxmtu6 _bsd_tcp_maxmtu6
#define tcp_maxpersistidle _bsd_tcp_maxpersistidle
#define tcp_maxseg _bsd_tcp_maxseg
+#define tcp_m_copym _bsd_tcp_m_copym
#define tcp_minmss _bsd_tcp_minmss
#define tcp_msl _bsd_tcp_msl
#define tcp_mss _bsd_tcp_mss
@@ -4801,6 +4860,7 @@
#define tcp_new_isn _bsd_tcp_new_isn
#define tcp_newreno_partial_ack _bsd_tcp_newreno_partial_ack
#define tcp_newtcpcb _bsd_tcp_newtcpcb
+#define tcp_new_ts_offset _bsd_tcp_new_ts_offset
#define tcp_offload_connect _bsd_tcp_offload_connect
#define tcp_offload_ctloutput _bsd_tcp_offload_ctloutput
#define tcp_offload_detach _bsd_tcp_offload_detach
@@ -4820,6 +4880,7 @@
#define tc_precexp _bsd_tc_precexp
#define tcp_recvspace _bsd_tcp_recvspace
#define tcp_respond _bsd_tcp_respond
+#define tcp_rexmit_drop_options _bsd_tcp_rexmit_drop_options
#define tcp_rexmit_min _bsd_tcp_rexmit_min
#define tcp_rexmit_slop _bsd_tcp_rexmit_slop
#define tcprexmtthresh _bsd_tcprexmtthresh
@@ -4850,6 +4911,9 @@
#define tcp_timer_persist _bsd_tcp_timer_persist
#define tcp_timer_rexmt _bsd_tcp_timer_rexmt
#define tcp_timer_stop _bsd_tcp_timer_stop
+#define tcp_timers_unsuspend _bsd_tcp_timers_unsuspend
+#define tcp_timer_suspend _bsd_tcp_timer_suspend
+#define tcp_totbackoff _bsd_tcp_totbackoff
#define tcp_trace _bsd_tcp_trace
#define tcp_tw_2msl_scan _bsd_tcp_tw_2msl_scan
#define tcp_twcheck _bsd_tcp_twcheck
@@ -5046,11 +5110,13 @@
#define uma_startup _bsd_uma_startup
#define uma_zalloc_arg _bsd_uma_zalloc_arg
#define uma_zalloc_domain _bsd_uma_zalloc_domain
+#define uma_zalloc_pcpu_arg _bsd_uma_zalloc_pcpu_arg
#define uma_zcache_create _bsd_uma_zcache_create
#define uma_zcreate _bsd_uma_zcreate
#define uma_zdestroy _bsd_uma_zdestroy
#define uma_zfree_arg _bsd_uma_zfree_arg
#define uma_zfree_domain _bsd_uma_zfree_domain
+#define uma_zfree_pcpu_arg _bsd_uma_zfree_pcpu_arg
#define uma_zone_exhausted _bsd_uma_zone_exhausted
#define uma_zone_exhausted_nolock _bsd_uma_zone_exhausted_nolock
#define uma_zone_get_cur _bsd_uma_zone_get_cur
@@ -5067,6 +5133,7 @@
#define uma_zone_set_zinit _bsd_uma_zone_set_zinit
#define uma_zsecond_create _bsd_uma_zsecond_create
#define uma_zwait _bsd_uma_zwait
+#define unp_copy_peercred _bsd_unp_copy_peercred
#define untimeout _bsd_untimeout
#define usb_alloc_device _bsd_usb_alloc_device
#define usb_alloc_mbufs _bsd_usb_alloc_mbufs
@@ -5353,6 +5420,7 @@
#define vlan_input_p _bsd_vlan_input_p
#define vlan_link_state_p _bsd_vlan_link_state_p
#define vlan_mtag_pcp _bsd_vlan_mtag_pcp
+#define vlan_pcp_p _bsd_vlan_pcp_p
#define vlan_setcookie_p _bsd_vlan_setcookie_p
#define vlan_tag_p _bsd_vlan_tag_p
#define vlan_trunk_cap_p _bsd_vlan_trunk_cap_p
diff --git a/rtemsbsd/include/rtems/bsd/local/cryptodev_if.h b/rtemsbsd/include/rtems/bsd/local/cryptodev_if.h
index 752527ed..a789317b 100644
--- a/rtemsbsd/include/rtems/bsd/local/cryptodev_if.h
+++ b/rtemsbsd/include/rtems/bsd/local/cryptodev_if.h
@@ -17,27 +17,43 @@
/** @brief Unique descriptor for the CRYPTODEV_NEWSESSION() method */
extern struct kobjop_desc cryptodev_newsession_desc;
/** @brief A function implementing the CRYPTODEV_NEWSESSION() method */
-typedef int cryptodev_newsession_t(device_t dev, uint32_t *sid,
+typedef int cryptodev_newsession_t(device_t dev,
+ crypto_session_t crypto_session,
struct cryptoini *cri);
+/**
+ * Crypto driver method to initialize a new session object with the given
+ * initialization parameters (cryptoini). The driver's session memory object
+ * is already allocated and zeroed, like driver softcs. It is accessed with
+ * crypto_get_driver_session().
+ */
-static __inline int CRYPTODEV_NEWSESSION(device_t dev, uint32_t *sid,
+static __inline int CRYPTODEV_NEWSESSION(device_t dev,
+ crypto_session_t crypto_session,
struct cryptoini *cri)
{
kobjop_t _m;
+ int rc;
KOBJOPLOOKUP(((kobj_t)dev)->ops,cryptodev_newsession);
- return ((cryptodev_newsession_t *) _m)(dev, sid, cri);
+ rc = ((cryptodev_newsession_t *) _m)(dev, crypto_session, cri);
+ return (rc);
}
/** @brief Unique descriptor for the CRYPTODEV_FREESESSION() method */
extern struct kobjop_desc cryptodev_freesession_desc;
/** @brief A function implementing the CRYPTODEV_FREESESSION() method */
-typedef int cryptodev_freesession_t(device_t dev, uint64_t sid);
+typedef void cryptodev_freesession_t(device_t dev,
+ crypto_session_t crypto_session);
+/**
+ * Optional crypto driver method to release any additional allocations. OCF
+ * owns session memory itself; it is zeroed before release.
+ */
-static __inline int CRYPTODEV_FREESESSION(device_t dev, uint64_t sid)
+static __inline void CRYPTODEV_FREESESSION(device_t dev,
+ crypto_session_t crypto_session)
{
kobjop_t _m;
KOBJOPLOOKUP(((kobj_t)dev)->ops,cryptodev_freesession);
- return ((cryptodev_freesession_t *) _m)(dev, sid);
+ ((cryptodev_freesession_t *) _m)(dev, crypto_session);
}
/** @brief Unique descriptor for the CRYPTODEV_PROCESS() method */
@@ -49,8 +65,10 @@ static __inline int CRYPTODEV_PROCESS(device_t dev, struct cryptop *op,
int flags)
{
kobjop_t _m;
+ int rc;
KOBJOPLOOKUP(((kobj_t)dev)->ops,cryptodev_process);
- return ((cryptodev_process_t *) _m)(dev, op, flags);
+ rc = ((cryptodev_process_t *) _m)(dev, op, flags);
+ return (rc);
}
/** @brief Unique descriptor for the CRYPTODEV_KPROCESS() method */
@@ -62,8 +80,10 @@ static __inline int CRYPTODEV_KPROCESS(device_t dev, struct cryptkop *op,
int flags)
{
kobjop_t _m;
+ int rc;
KOBJOPLOOKUP(((kobj_t)dev)->ops,cryptodev_kprocess);
- return ((cryptodev_kprocess_t *) _m)(dev, op, flags);
+ rc = ((cryptodev_kprocess_t *) _m)(dev, op, flags);
+ return (rc);
}
#endif /* _cryptodev_if_h_ */
diff --git a/rtemsbsd/include/rtems/bsd/local/sdhci_if.h b/rtemsbsd/include/rtems/bsd/local/sdhci_if.h
index 531090f8..f8ee4fe4 100644
--- a/rtemsbsd/include/rtems/bsd/local/sdhci_if.h
+++ b/rtemsbsd/include/rtems/bsd/local/sdhci_if.h
@@ -24,8 +24,10 @@ static __inline uint8_t SDHCI_READ_1(device_t brdev, struct sdhci_slot *slot,
bus_size_t off)
{
kobjop_t _m;
+ uint8_t rc;
KOBJOPLOOKUP(((kobj_t)brdev)->ops,sdhci_read_1);
- return ((sdhci_read_1_t *) _m)(brdev, slot, off);
+ rc = ((sdhci_read_1_t *) _m)(brdev, slot, off);
+ return (rc);
}
/** @brief Unique descriptor for the SDHCI_READ_2() method */
@@ -38,8 +40,10 @@ static __inline uint16_t SDHCI_READ_2(device_t brdev, struct sdhci_slot *slot,
bus_size_t off)
{
kobjop_t _m;
+ uint16_t rc;
KOBJOPLOOKUP(((kobj_t)brdev)->ops,sdhci_read_2);
- return ((sdhci_read_2_t *) _m)(brdev, slot, off);
+ rc = ((sdhci_read_2_t *) _m)(brdev, slot, off);
+ return (rc);
}
/** @brief Unique descriptor for the SDHCI_READ_4() method */
@@ -52,8 +56,10 @@ static __inline uint32_t SDHCI_READ_4(device_t brdev, struct sdhci_slot *slot,
bus_size_t off)
{
kobjop_t _m;
+ uint32_t rc;
KOBJOPLOOKUP(((kobj_t)brdev)->ops,sdhci_read_4);
- return ((sdhci_read_4_t *) _m)(brdev, slot, off);
+ rc = ((sdhci_read_4_t *) _m)(brdev, slot, off);
+ return (rc);
}
/** @brief Unique descriptor for the SDHCI_READ_MULTI_4() method */
@@ -141,8 +147,10 @@ static __inline int SDHCI_PLATFORM_WILL_HANDLE(device_t brdev,
struct sdhci_slot *slot)
{
kobjop_t _m;
+ int rc;
KOBJOPLOOKUP(((kobj_t)brdev)->ops,sdhci_platform_will_handle);
- return ((sdhci_platform_will_handle_t *) _m)(brdev, slot);
+ rc = ((sdhci_platform_will_handle_t *) _m)(brdev, slot);
+ return (rc);
}
/** @brief Unique descriptor for the SDHCI_PLATFORM_START_TRANSFER() method */
@@ -183,8 +191,10 @@ typedef uint32_t sdhci_min_freq_t(device_t brdev, struct sdhci_slot *slot);
static __inline uint32_t SDHCI_MIN_FREQ(device_t brdev, struct sdhci_slot *slot)
{
kobjop_t _m;
+ uint32_t rc;
KOBJOPLOOKUP(((kobj_t)brdev)->ops,sdhci_min_freq);
- return ((sdhci_min_freq_t *) _m)(brdev, slot);
+ rc = ((sdhci_min_freq_t *) _m)(brdev, slot);
+ return (rc);
}
/** @brief Unique descriptor for the SDHCI_GET_CARD_PRESENT() method */
@@ -196,8 +206,10 @@ static __inline bool SDHCI_GET_CARD_PRESENT(device_t brdev,
struct sdhci_slot *slot)
{
kobjop_t _m;
+ bool rc;
KOBJOPLOOKUP(((kobj_t)brdev)->ops,sdhci_get_card_present);
- return ((sdhci_get_card_present_t *) _m)(brdev, slot);
+ rc = ((sdhci_get_card_present_t *) _m)(brdev, slot);
+ return (rc);
}
/** @brief Unique descriptor for the SDHCI_SET_UHS_TIMING() method */
diff --git a/rtemsbsd/include/rtems/bsd/local/usbdevs.h b/rtemsbsd/include/rtems/bsd/local/usbdevs.h
index 5eee5c10..ce48f040 100644
--- a/rtemsbsd/include/rtems/bsd/local/usbdevs.h
+++ b/rtemsbsd/include/rtems/bsd/local/usbdevs.h
@@ -65,7 +65,7 @@
#define USB_VENDOR_EGALAX2 0x0123 /* eGalax, Inc. */
#define USB_VENDOR_CHIPSBANK 0x0204 /* Chipsbank Microelectronics Co. */
#define USB_VENDOR_HUMAX 0x02ad /* HUMAX */
-#define USB_VENDOR_INTENSO 0x2109 /* INTENSO */
+#define USB_VENDOR_QUAN 0x01e1 /* Quan */
#define USB_VENDOR_LTS 0x0386 /* LTS */
#define USB_VENDOR_BWCT 0x03da /* Bernd Walter Computer Technology */
#define USB_VENDOR_AOX 0x03e8 /* AOX */
@@ -97,7 +97,7 @@
#define USB_VENDOR_QUANTA 0x0408 /* Quanta */
#define USB_VENDOR_NEC 0x0409 /* NEC */
#define USB_VENDOR_KODAK 0x040a /* Eastman Kodak */
-#define USB_VENDOR_WELTREND 0x040b /* Weltrend */
+#define USB_VENDOR_WELTREND 0x040b /* Weltrend Semiconductor */
#define USB_VENDOR_VIA 0x040d /* VIA */
#define USB_VENDOR_MCCI 0x040e /* MCCI */
#define USB_VENDOR_MELCO 0x0411 /* Melco */
@@ -108,7 +108,7 @@
#define USB_VENDOR_NOKIA 0x0421 /* Nokia */
#define USB_VENDOR_ADI 0x0422 /* ADI Systems */
#define USB_VENDOR_CATC 0x0423 /* Computer Access Technology */
-#define USB_VENDOR_SMC2 0x0424 /* Standard Microsystems */
+#define USB_VENDOR_SMC2 0x0424 /* Microchip (Standard Microsystems) */
#define USB_VENDOR_MOTOROLA_HK 0x0425 /* Motorola HK */
#define USB_VENDOR_GRAVIS 0x0428 /* Advanced Gravis Computer */
#define USB_VENDOR_CIRRUSLOGIC 0x0429 /* Cirrus Logic */
@@ -150,7 +150,7 @@
#define USB_VENDOR_PLANTRONICS 0x047f /* Plantronics */
#define USB_VENDOR_KYOCERA 0x0482 /* Kyocera Wireless Corp. */
#define USB_VENDOR_STMICRO 0x0483 /* STMicroelectronics */
-#define USB_VENDOR_FOXCONN 0x0489 /* Foxconn */
+#define USB_VENDOR_FOXCONN 0x0489 /* Foxconn / Hon Hai */
#define USB_VENDOR_MEIZU 0x0492 /* Meizu Electronics */
#define USB_VENDOR_YAMAHA 0x0499 /* YAMAHA */
#define USB_VENDOR_COMPAQ 0x049f /* Compaq */
@@ -202,7 +202,7 @@
#define USB_VENDOR_ANNABOOKS 0x04ed /* Annabooks */
#define USB_VENDOR_JVC 0x04f1 /* JVC */
#define USB_VENDOR_CHICONY 0x04f2 /* Chicony Electronics */
-#define USB_VENDOR_ELAN 0x04f3 /* Elan */
+#define USB_VENDOR_ELAN 0x04f3 /* ELAN Microelectronics */
#define USB_VENDOR_NEWNEX 0x04f7 /* Newnex */
#define USB_VENDOR_BROTHER 0x04f9 /* Brother Industries */
#define USB_VENDOR_DALLAS 0x04fa /* Dallas Semiconductor */
@@ -259,6 +259,7 @@
#define USB_VENDOR_BAFO 0x0576 /* BAFO/Quality Computer Accessories */
#define USB_VENDOR_YEDATA 0x057b /* Y-E Data */
#define USB_VENDOR_AVM 0x057c /* AVM */
+#define USB_VENDOR_NINTENDO 0x057e /* Nintendo */
#define USB_VENDOR_QUICKSHOT 0x057f /* Quickshot */
#define USB_VENDOR_ROLAND 0x0582 /* Roland */
#define USB_VENDOR_ROCKFIRE 0x0583 /* Rockfire */
@@ -316,6 +317,7 @@
#define USB_VENDOR_CHIC 0x05fe /* Chic Technology */
#define USB_VENDOR_BARCO 0x0600 /* Barco Display Systems */
#define USB_VENDOR_BRIDGE 0x0607 /* Bridge Information */
+#define USB_VENDOR_SMK 0x0609 /* SMK */
#define USB_VENDOR_SOLIDYEAR 0x060b /* Solid Year */
#define USB_VENDOR_BIORAD 0x0614 /* Bio-Rad Laboratories */
#define USB_VENDOR_MACALLY 0x0618 /* Macally */
@@ -370,6 +372,7 @@
#define USB_VENDOR_TECLAST 0x071b /* Teclast */
#define USB_VENDOR_SONYERICSSON 0x0731 /* Sony Ericsson */
#define USB_VENDOR_EICON 0x0734 /* Eicon Networks */
+#define USB_VENDOR_MADCATZ 0x0738 /* Mad Catz, Inc. */
#define USB_VENDOR_SYNTECH 0x0745 /* Syntech Information */
#define USB_VENDOR_DIGITALSTREAM 0x074e /* Digital Stream */
#define USB_VENDOR_AUREAL 0x0755 /* Aureal Semiconductor */
@@ -399,6 +402,7 @@
#define USB_VENDOR_GENERALINSTMNTS 0x07b2 /* General Instruments (Motorola) */
#define USB_VENDOR_OLYMPUS 0x07b4 /* Olympus */
#define USB_VENDOR_ABOCOM 0x07b8 /* AboCom Systems */
+#define USB_VENDOR_KINGSUN 0x07c0 /* KingSun */
#define USB_VENDOR_KEISOKUGIKEN 0x07c1 /* Keisokugiken */
#define USB_VENDOR_ONSPEC 0x07c4 /* OnSpec */
#define USB_VENDOR_APG 0x07c5 /* APG Cash Drawer */
@@ -412,11 +416,13 @@
#define USB_VENDOR_ARASAN 0x07da /* Arasan Chip Systems */
#define USB_VENDOR_ALLIEDCABLE 0x07e6 /* Allied Cable */
#define USB_VENDOR_STSN 0x07ef /* STSN */
+#define USB_VENDOR_BEWAN 0x07fa /* Bewan */
#define USB_VENDOR_CENTURY 0x07f7 /* Century Corp */
#define USB_VENDOR_NEWLINK 0x07ff /* NEWlink */
#define USB_VENDOR_MAGTEK 0x0801 /* Mag-Tek */
#define USB_VENDOR_ZOOM 0x0803 /* Zoom Telephonics */
#define USB_VENDOR_PCS 0x0810 /* Personal Communication Systems */
+#define USB_VENDOR_SYNET 0x0812 /* Synet Electronics */
#define USB_VENDOR_ALPHASMART 0x081e /* AlphaSmart, Inc. */
#define USB_VENDOR_BROADLOGIC 0x0827 /* BroadLogic */
#define USB_VENDOR_HANDSPRING 0x082d /* Handspring */
@@ -466,6 +472,7 @@
#define USB_VENDOR_INTREPIDCS 0x093c /* Intrepid */
#define USB_VENDOR_YANO 0x094f /* Yano */
#define USB_VENDOR_KINGSTON 0x0951 /* Kingston Technology */
+#define USB_VENDOR_NVIDIA 0x0955 /* NVIDIA Corporation */
#define USB_VENDOR_BLUEWATER 0x0956 /* BlueWater Systems */
#define USB_VENDOR_AGILENT 0x0957 /* Agilent Technologies */
#define USB_VENDOR_GUDE 0x0959 /* Gude ADS */
@@ -474,8 +481,10 @@
#define USB_VENDOR_ADIRONDACK 0x0976 /* Adirondack Wire & Cable */
#define USB_VENDOR_BECKHOFF 0x0978 /* Beckhoff */
#define USB_VENDOR_MINDSATWORK 0x097a /* Minds At Work */
+#define USB_VENDOR_ZIPPY 0x099a /* Zippy Technology Corporation */
#define USB_VENDOR_POINTCHIPS 0x09a6 /* PointChips */
#define USB_VENDOR_INTERSIL 0x09aa /* Intersil */
+#define USB_VENDOR_TRIPPLITE2 0x09ae /* Tripp Lite */
#define USB_VENDOR_ALTIUS 0x09b3 /* Altius Solutions */
#define USB_VENDOR_ARRIS 0x09c1 /* Arris Interactive */
#define USB_VENDOR_ACTIVCARD 0x09c3 /* ACTIVCARD */
@@ -512,7 +521,7 @@
#define USB_VENDOR_EMS 0x0b43 /* EMS Production */
#define USB_VENDOR_NEC2 0x0b62 /* NEC */
#define USB_VENDOR_ADLINK 0x0b63 /* ADLINK Technoligy, Inc. */
-#define USB_VENDOR_ATI2 0x0b6f /* ATI */
+#define USB_VENDOR_ATI2 0x0b6f /* ATI Technologies */
#define USB_VENDOR_ZEEVO 0x0b7a /* Zeevo, Inc. */
#define USB_VENDOR_KURUSUGAWA 0x0b7e /* Kurusugawa Electronics, Inc. */
#define USB_VENDOR_SMART 0x0b8c /* Smart Technologies */
@@ -578,12 +587,14 @@
#define USB_VENDOR_LARSENBRUSGAARD 0x0fd8 /* Larsen and Brusgaard */
#define USB_VENDOR_OWL 0x0fde /* OWL */
#define USB_VENDOR_KONTRON 0x0fe6 /* Kontron AG */
+#define USB_VENDOR_DVICO 0x0fe9 /* DViCO */
#define USB_VENDOR_QUALCOMM 0x1004 /* Qualcomm */
#define USB_VENDOR_APACER 0x1005 /* Apacer */
#define USB_VENDOR_MOTOROLA4 0x100d /* Motorola */
#define USB_VENDOR_HP3 0x103c /* Hewlett Packard */
#define USB_VENDOR_AIRPLUS 0x1011 /* Airplus */
#define USB_VENDOR_DESKNOTE 0x1019 /* Desknote */
+#define USB_VENDOR_AMD2 0x1022 /* Advanced Micro Devices */
#define USB_VENDOR_NEC3 0x1033 /* NEC */
#define USB_VENDOR_TTI 0x103e /* Thurlby Thandar Instruments */
#define USB_VENDOR_GIGABYTE 0x1044 /* GIGABYTE */
@@ -618,6 +629,7 @@
#define USB_VENDOR_NETINDEX 0x11f6 /* NetIndex */
#define USB_VENDOR_ALCATEL 0x11f7 /* Alcatel */
#define USB_VENDOR_INTERBIOMETRICS 0x1209 /* Interbiometrics */
+#define USB_VENDOR_FUJITSU3 0x1221 /* Fujitsu Ltd. */
#define USB_VENDOR_UNKNOWN3 0x1233 /* Unknown vendor */
#define USB_VENDOR_TSUNAMI 0x1241 /* Tsunami */
#define USB_VENDOR_PHEENET 0x124a /* Pheenet */
@@ -635,6 +647,7 @@
#define USB_VENDOR_MOBILITY 0x1342 /* Mobility */
#define USB_VENDOR_DICKSMITH 0x1371 /* Dick Smith Electronics */
#define USB_VENDOR_NETGEAR3 0x1385 /* Netgear */
+#define USB_VENDOR_VALIDITY 0x138a /* Validity Sensors, Inc. */
#define USB_VENDOR_BALTECH 0x13ad /* Baltech */
#define USB_VENDOR_CISCOLINKSYS 0x13b1 /* Cisco-Linksys */
#define USB_VENDOR_SHARK 0x13d2 /* Shark */
@@ -642,6 +655,7 @@
#define USB_VENDOR_INITIO 0x13fd /* Initio Corporation */
#define USB_VENDOR_EMTEC 0x13fe /* Emtec */
#define USB_VENDOR_NOVATEL 0x1410 /* Novatel Wireless */
+#define USB_VENDOR_OMNIVISION2 0x1415 /* OmniVision Technologies, Inc. */
#define USB_VENDOR_MERLIN 0x1416 /* Merlin */
#define USB_VENDOR_REDOCTANE 0x1430 /* RedOctane */
#define USB_VENDOR_WISTRONNEWEB 0x1435 /* Wistron NeWeb */
@@ -696,17 +710,24 @@
#define USB_VENDOR_SWEEX2 0x177f /* Sweex */
#define USB_VENDOR_METAGEEK 0x1781 /* MetaGeek */
#define USB_VENDOR_KAMSTRUP 0x17a8 /* Kamstrup A/S */
+#define USB_VENDOR_MISC 0x1781 /* Misc Vendors */
#define USB_VENDOR_DISPLAYLINK 0x17e9 /* DisplayLink */
#define USB_VENDOR_LENOVO 0x17ef /* Lenovo */
#define USB_VENDOR_WAVESENSE 0x17f4 /* WaveSense */
#define USB_VENDOR_VAISALA 0x1843 /* Vaisala */
+#define USB_VENDOR_E3C 0x18b4 /* E3C Technologies */
#define USB_VENDOR_AMIT 0x18c5 /* AMIT */
#define USB_VENDOR_GOOGLE 0x18d1 /* Google */
#define USB_VENDOR_QCOM 0x18e8 /* Qcom */
#define USB_VENDOR_ELV 0x18ef /* ELV */
#define USB_VENDOR_LINKSYS3 0x1915 /* Linksys */
+#define USB_VENDOR_MEINBERG 0x1938 /* Meinberg Funkuhren */
+#define USB_VENDOR_BECEEM 0x198f /* Beceem Communications */
+#define USB_VENDOR_ZTE 0x19d2 /* ZTE */
#define USB_VENDOR_QUALCOMMINC 0x19d2 /* Qualcomm, Incorporated */
#define USB_VENDOR_QUALCOMM3 0x19f5 /* Qualcomm, Inc. */
+#define USB_VENDOR_QUANTA2 0x1a32 /* Quanta */
+#define USB_VENDOR_TERMINUS 0x1a40 /* Terminus Technology */
#define USB_VENDOR_ABBOTT 0x1a61 /* Abbott Diabetics */
#define USB_VENDOR_BAYER 0x1a79 /* Bayer */
#define USB_VENDOR_WCH2 0x1a86 /* QinHeng Electronics */
@@ -745,17 +766,22 @@
#define USB_VENDOR_PARA 0x20b8 /* PARA Industrial */
#define USB_VENDOR_SIMTEC 0x20df /* Simtec Electronics */
#define USB_VENDOR_TRENDNET 0x20f4 /* TRENDnet */
-#define USB_VENDOR_RTSYSTEMS 0x2100 /* RTSYSTEMS */
+#define USB_VENDOR_RTSYSTEMS 0x2100 /* RT Systems */
+#define USB_VENDOR_DLINK4 0x2101 /* D-Link */
+#define USB_VENDOR_INTENSO 0x2109 /* INTENSO */
#define USB_VENDOR_VIALABS 0x2109 /* VIA Labs */
#define USB_VENDOR_ERICSSON 0x2282 /* Ericsson */
#define USB_VENDOR_MOTOROLA2 0x22b8 /* Motorola */
#define USB_VENDOR_WETELECOM 0x22de /* WeTelecom */
+#define USB_VENDOR_PINNACLE 0x2304 /* Pinnacle Systems */
+#define USB_VENDOR_ARDUINO 0x2341 /* Arduino SA */
#define USB_VENDOR_TPLINK 0x2357 /* TP-Link */
#define USB_VENDOR_WESTMOUNTAIN 0x2405 /* West Mountain Radio */
#define USB_VENDOR_TRIPPLITE 0x2478 /* Tripp-Lite */
#define USB_VENDOR_HIROSE 0x2631 /* Hirose Electric */
#define USB_VENDOR_NHJ 0x2770 /* NHJ */
#define USB_VENDOR_THINGM 0x27b8 /* ThingM */
+#define USB_VENDOR_PERASO 0x2932 /* Peraso Technologies, Inc. */
#define USB_VENDOR_PLANEX 0x2c02 /* Planex Communications */
#define USB_VENDOR_QUECTEL 0x2c7c /* Quectel Wireless Solutions */
#define USB_VENDOR_VIDZMEDIA 0x3275 /* VidzMedia Pte Ltd */
@@ -778,7 +804,9 @@
#define USB_VENDOR_PROLIFIC2 0x5372 /* Prolific Technologies */
#define USB_VENDOR_ONSPEC2 0x55aa /* OnSpec Electronic Inc. */
#define USB_VENDOR_ZINWELL 0x5a57 /* Zinwell */
+#define USB_VENDOR_INGENIC 0x601a /* Ingenic Semiconductor Ltd. */
#define USB_VENDOR_SITECOM 0x6189 /* Sitecom */
+#define USB_VENDOR_SPRINGERDESIGN 0x6400 /* Springer Design, Inc. */
#define USB_VENDOR_ARKMICRO 0x6547 /* Arkmicro Technologies Inc. */
#define USB_VENDOR_3COM2 0x6891 /* 3Com */
#define USB_VENDOR_EDIMAX 0x7392 /* Edimax */
@@ -791,8 +819,10 @@
#define USB_VENDOR_MARVELL 0x9e88 /* Marvell Technology Group Ltd. */
#define USB_VENDOR_3COM3 0xa727 /* 3Com */
#define USB_VENDOR_CACE 0xcace /* CACE Technologies */
-#define USB_VENDOR_EVOLUTION 0xdeee /* Evolution Robotics products */
+#define USB_VENDOR_COMPARE 0xcdab /* Compare */
#define USB_VENDOR_DATAAPEX 0xdaae /* DataApex */
+#define USB_VENDOR_EVOLUTION 0xdeee /* Evolution Robotics */
+#define USB_VENDOR_EMPIA 0xeb1a /* eMPIA Technology */
#define USB_VENDOR_HP2 0xf003 /* Hewlett Packard */
#define USB_VENDOR_LOGILINK 0xfc08 /* LogiLink */
#define USB_VENDOR_USRP 0xfffe /* GNU Radio USRP */
@@ -802,7 +832,7 @@
*/
/* 3Com products */
-#define USB_PRODUCT_3COM_HOMECONN 0x009d /* HomeConnect Camera */
+#define USB_PRODUCT_3COM_HOMECONN 0x009d /* HomeConnect USB Camera */
#define USB_PRODUCT_3COM_3CREB96 0x00a0 /* Bluetooth USB Adapter */
#define USB_PRODUCT_3COM_3C19250 0x03e8 /* 3C19250 Ethernet Adapter */
#define USB_PRODUCT_3COM_3CRSHEW696 0x0a01 /* 3CRSHEW696 Wireless Adapter */
@@ -826,6 +856,10 @@
/* ABIT products */
#define USB_PRODUCT_ABIT_AK_020 0x7d0e /* 3G modem */
+#define USB_PRODUCT_ACDC_HUB 0x2315 /* USB Pen Drive HUB */
+#define USB_PRODUCT_ACDC_SECWRITE 0x2316 /* USB Pen Drive Secure Write */
+#define USB_PRODUCT_ACDC_PEN 0x2317 /* USB Pen Drive with Secure Write */
+
/* AboCom products */
#define USB_PRODUCT_ABOCOM_XX1 0x110c /* XX1 */
#define USB_PRODUCT_ABOCOM_XX2 0x200c /* XX2 */
@@ -933,6 +967,9 @@
/* Adaptec products */
#define USB_PRODUCT_ADAPTEC_AWN8020 0x0020 /* AWN-8020 WLAN */
+/* Addonics products */
+#define USB_PRODUCT_ADDONICS2_205 0xa001 /* Cable 205 */
+
/* Addtron products */
#define USB_PRODUCT_ADDTRON_AWU120 0xff31 /* AWU-120 */
@@ -1025,6 +1062,7 @@
/* Alink products */
#define USB_PRODUCT_ALINK_DWM652U5 0xce16 /* DWM-652 */
#define USB_PRODUCT_ALINK_3G 0x9000 /* 3G modem */
+#define USB_PRODUCT_ALINK_SIM7600E 0x9001 /* LTE modem */
#define USB_PRODUCT_ALINK_3GU 0x9200 /* 3G modem */
/* Altec Lansing products */
@@ -1672,6 +1710,7 @@
#define USB_PRODUCT_DLINK_RT2870 0x3c09 /* RT2870 */
#define USB_PRODUCT_DLINK_RT3072 0x3c0a /* RT3072 */
#define USB_PRODUCT_DLINK_DWA140B3 0x3c15 /* DWA-140 rev B3 */
+#define USB_PRODUCT_DLINK_DWA125A3 0x3c19 /* DWA-125 rev A3 */
#define USB_PRODUCT_DLINK_DWA160B2 0x3c1a /* DWA-160 rev B2 */
#define USB_PRODUCT_DLINK_DWA127 0x3c1b /* DWA-127 Wireless Adapter */
#define USB_PRODUCT_DLINK_DWA162 0x3c1f /* DWA-162 Wireless Adapter */
@@ -2204,9 +2243,12 @@
#define USB_PRODUCT_GENESYS_GL650 0x0604 /* GL650 HUB */
#define USB_PRODUCT_GENESYS_GL606 0x0606 /* GL606 USB 2.0 HUB */
#define USB_PRODUCT_GENESYS_GL850G 0x0608 /* GL850G USB 2.0 HUB */
+#define USB_PRODUCT_GENESYS_GL3520_2 0x0610 /* GL3520 4-Port USB 2.0 DataPath */
+#define USB_PRODUCT_GENESYS_GL3520_SS 0x0616 /* GL3520 4-Port USB 3.0 DataPath */
#define USB_PRODUCT_GENESYS_GL641USB 0x0700 /* GL641USB CompactFlash Card Reader */
#define USB_PRODUCT_GENESYS_GL641USB2IDE_2 0x0701 /* GL641USB USB-IDE Bridge No 2 */
#define USB_PRODUCT_GENESYS_GL641USB2IDE 0x0702 /* GL641USB USB-IDE Bridge */
+#define USB_PRODUCT_GENESYS_GL3233 0x0743 /* GL3233 USB 3.0 AiO Card Reader */
#define USB_PRODUCT_GENESYS_GL641USB_2 0x0760 /* GL641USB 6-in-1 Card Reader */
/* GIGABYTE products */
@@ -2237,6 +2279,7 @@
#define USB_PRODUCT_GLOBALSUN_AR5523_2_NF 0x7812 /* AR5523 (no firmware) */
/* Globespan products */
+#define USB_PRODUCT_GLOBESPAN_MODEM_1 0x1329 /* USB Modem */
#define USB_PRODUCT_GLOBESPAN_PRISM_GT_1 0x2000 /* PrismGT USB 2.0 WLAN */
#define USB_PRODUCT_GLOBESPAN_PRISM_GT_2 0x2002 /* PrismGT USB 2.0 WLAN */
@@ -2525,6 +2568,10 @@
#define USB_PRODUCT_INTEL2_IRMH2 0x0024 /* Integrated Rate Matching Hub */
#define USB_PRODUCT_INTEL2_IRMH3 0x8000 /* Integrated Rate Matching Hub */
#define USB_PRODUCT_INTEL2_IRMH4 0x8008 /* Integrated Rate Matching Hub */
+#define USB_PRODUCT_INTEL2_SFP 0x0aa7 /* Sandy Peak (3168) Bluetooth Module */
+#define USB_PRODUCT_INTEL2_JFP 0x0aaa /* Jefferson Peak (9460/9560) Bluetooth Module */
+#define USB_PRODUCT_INTEL2_THP 0x0025 /* Thunder Peak (9160/9260) Bluetooth Module */
+#define USB_PRODUCT_INTEL2_HSP 0x0026 /* Harrison Peak (22560) Bluetooth Module */
/* Interbiometric products */
#define USB_PRODUCT_INTERBIOMETRICS_IOBOARD 0x1002 /* FTDI compatible adapter */
@@ -3415,6 +3462,9 @@
#define USB_PRODUCT_NOVATEL_MC679 0x7031 /* Novatel MC679 */
#define USB_PRODUCT_NOVATEL2_FLEXPACKGPS 0x0100 /* NovAtel FlexPack GPS receiver */
+/* NVIDIA products */
+#define USB_PRODUCT_NVIDIA_RTL8153 0x09ff /* USB 3.0 Ethernet */
+
/* Merlin products */
#define USB_PRODUCT_MERLIN_V620 0x1110 /* Merlin V620 */
@@ -3587,12 +3637,16 @@
#define USB_PRODUCT_PERACOM_ENET3 0x0003 /* At Home Ethernet */
#define USB_PRODUCT_PERACOM_ENET2 0x0005 /* Ethernet */
+/* Peraso Technologies, Inc products */
+#define USB_PRODUCT_PERASO_PRS4001 0x4001 /* PRS4001 WLAN */
+
/* Philips products */
#define USB_PRODUCT_PHILIPS_DSS350 0x0101 /* DSS 350 Digital Speaker System */
#define USB_PRODUCT_PHILIPS_DSS 0x0104 /* DSS XXX Digital Speaker System */
#define USB_PRODUCT_PHILIPS_HUB 0x0201 /* hub */
#define USB_PRODUCT_PHILIPS_PCA646VC 0x0303 /* PCA646VC PC Camera */
#define USB_PRODUCT_PHILIPS_PCVC680K 0x0308 /* PCVC680K Vesta Pro PC Camera */
+#define USB_PRODUCT_PHILIPS_SPC900NC 0x0329 /* SPC 900NC CCD PC Camera */
#define USB_PRODUCT_PHILIPS_DSS150 0x0471 /* DSS 150 Digital Speaker System */
#define USB_PRODUCT_PHILIPS_ACE1001 0x066a /* AKTAKOM ACE-1001 cable */
#define USB_PRODUCT_PHILIPS_SPE3030CC 0x083a /* USB 2.0 External Disk */
@@ -3856,6 +3910,7 @@
#define USB_PRODUCT_RALINK_RT3572 0x3572 /* RT3572 */
#define USB_PRODUCT_RALINK_RT3573 0x3573 /* RT3573 */
#define USB_PRODUCT_RALINK_RT5370 0x5370 /* RT5370 */
+#define USB_PRODUCT_RALINK_RT5372 0x5372 /* RT5372 */
#define USB_PRODUCT_RALINK_RT5572 0x5572 /* RT5572 */
#define USB_PRODUCT_RALINK_RT8070 0x8070 /* RT8070 */
#define USB_PRODUCT_RALINK_RT2570_3 0x9020 /* RT2500USB Wireless Adapter */
@@ -4325,6 +4380,9 @@
#define USB_PRODUCT_SMC2_2020HUB 0x2020 /* USB Hub */
#define USB_PRODUCT_SMC2_2514HUB 0x2514 /* USB Hub */
#define USB_PRODUCT_SMC3_2662WUSB 0xa002 /* 2662W-AR Wireless */
+#define USB_PRODUCT_SMC2_LAN7800_ETH 0x7800 /* USB/Ethernet */
+#define USB_PRODUCT_SMC2_LAN7801_ETH 0x7801 /* USB/Ethernet */
+#define USB_PRODUCT_SMC2_LAN7850_ETH 0x7850 /* USB/Ethernet */
#define USB_PRODUCT_SMC2_LAN9500_ETH 0x9500 /* USB/Ethernet */
#define USB_PRODUCT_SMC2_LAN9505_ETH 0x9505 /* USB/Ethernet */
#define USB_PRODUCT_SMC2_LAN9530_ETH 0x9530 /* USB/Ethernet */
@@ -4743,7 +4801,18 @@
/* Yamaha products */
#define USB_PRODUCT_YAMAHA_UX256 0x1000 /* UX256 MIDI I/F */
+#define USB_PRODUCT_YAMAHA_MU1000 0x1001 /* MU1000 MIDI Synth. */
+#define USB_PRODUCT_YAMAHA_MU2000 0x1002 /* MU2000 MIDI Synth. */
+#define USB_PRODUCT_YAMAHA_MU500 0x1003 /* MU500 MIDI Synth. */
+#define USB_PRODUCT_YAMAHA_UW500 0x1004 /* UW500 USB Audio I/F */
+#define USB_PRODUCT_YAMAHA_MOTIF6 0x1005 /* MOTIF6 MIDI Synth. Workstation */
+#define USB_PRODUCT_YAMAHA_MOTIF7 0x1006 /* MOTIF7 MIDI Synth. Workstation */
+#define USB_PRODUCT_YAMAHA_MOTIF8 0x1007 /* MOTIF8 MIDI Synth. Workstation */
#define USB_PRODUCT_YAMAHA_UX96 0x1008 /* UX96 MIDI I/F */
+#define USB_PRODUCT_YAMAHA_UX16 0x1009 /* UX16 MIDI I/F */
+#define USB_PRODUCT_YAMAHA_S08 0x100e /* S08 MIDI Keyboard */
+#define USB_PRODUCT_YAMAHA_CLP150 0x100f /* CLP-150 digital piano */
+#define USB_PRODUCT_YAMAHA_CLP170 0x1010 /* CLP-170 digital piano */
#define USB_PRODUCT_YAMAHA_RPU200 0x3104 /* RP-U200 */
#define USB_PRODUCT_YAMAHA_RTA54I 0x4000 /* NetVolante RTA54i Broadband&ISDN Router */
#define USB_PRODUCT_YAMAHA_RTW65B 0x4001 /* NetVolante RTW65b Broadband Wireless Router */
@@ -4778,6 +4847,9 @@
#define USB_PRODUCT_ZCOM_RT2870_2 0x0025 /* RT2870 */
#define USB_PRODUCT_ZCOM_UB82 0x0026 /* UB82 */
+/* Zeevo, Inc. products */
+#define USB_PRODUCT_ZEEVO_BLUETOOTH 0x07d0 /* BT-500 Bluetooth USB Adapter */
+
/* Zinwell products */
#define USB_PRODUCT_ZINWELL_RT2570 0x0260 /* RT2570 */
#define USB_PRODUCT_ZINWELL_RT2870_1 0x0280 /* RT2870 */
@@ -4788,14 +4860,28 @@
/* Zoom Telephonics, Inc. products */
#define USB_PRODUCT_ZOOM_2986L 0x9700 /* 2986L Fax modem */
+#define USB_PRODUCT_ZOOM_3095 0x3095 /* 3095 USB Fax modem */
/* Zoran Microelectronics products */
#define USB_PRODUCT_ZORAN_EX20DSC 0x4343 /* Digital Camera EX-20 DSC */
+/* ZTE products */
+#define USB_PRODUCT_ZTE_MF622 0x0001 /* MF622 modem */
+#define USB_PRODUCT_ZTE_MF628 0x0015 /* MF628 modem */
+#define USB_PRODUCT_ZTE_MF626 0x0031 /* MF626 modem */
+#define USB_PRODUCT_ZTE_MF820D_INSTALLER 0x0166 /* MF820D CD */
+#define USB_PRODUCT_ZTE_MF820D 0x0167 /* MF820D modem */
+#define USB_PRODUCT_ZTE_INSTALLER 0x2000 /* UMTS CD */
+#define USB_PRODUCT_ZTE_MC2718 0xffe8 /* MC2718 modem */
+#define USB_PRODUCT_ZTE_AC8700 0xfffe /* CDMA 1xEVDO USB modem */
+
/* Zydas Technology Corporation products */
+#define USB_PRODUCT_ZYDAS_ZD1201 0x1201 /* ZD1201 */
#define USB_PRODUCT_ZYDAS_ZD1211 0x1211 /* ZD1211 WLAN abg */
#define USB_PRODUCT_ZYDAS_ZD1211B 0x1215 /* ZD1211B */
#define USB_PRODUCT_ZYDAS_ZD1221 0x1221 /* ZD1221 */
+#define USB_PRODUCT_ZYDAS_ALL0298 0xa211 /* ALL0298 */
+#define USB_PRODUCT_ZYDAS_ZD1211B_2 0xb215 /* ZD1211B */
/* ZyXEL Communication Co. products */
#define USB_PRODUCT_ZYXEL_OMNI56K 0x1500 /* Omni 56K Plus */
@@ -4804,8 +4890,10 @@
#define USB_PRODUCT_ZYXEL_G200V2 0x3407 /* G-200 v2 */
#define USB_PRODUCT_ZYXEL_AG225H 0x3409 /* AG-225H */
#define USB_PRODUCT_ZYXEL_M202 0x340a /* M-202 */
+#define USB_PRODUCT_ZYXEL_G270S 0x340c /* G-270S */
#define USB_PRODUCT_ZYXEL_G220V2 0x340f /* G-220 v2 */
#define USB_PRODUCT_ZYXEL_G202 0x3410 /* G-202 */
+#define USB_PRODUCT_ZYXEL_RT2573 0x3415 /* RT2573 */
#define USB_PRODUCT_ZYXEL_RT2870_1 0x3416 /* RT2870 */
#define USB_PRODUCT_ZYXEL_NWD271N 0x3417 /* NWD-271N */
#define USB_PRODUCT_ZYXEL_NWD211AN 0x3418 /* NWD-211AN */
@@ -4813,4 +4901,5 @@
#define USB_PRODUCT_ZYXEL_RT3070 0x341e /* NWD2105 */
#define USB_PRODUCT_ZYXEL_RTL8192CU 0x341f /* RTL8192CU */
#define USB_PRODUCT_ZYXEL_NWD2705 0x3421 /* NWD2705 */
-#define USB_PRODUCT_ZYXEL_NWD6605 0x3426 /* NWD6605 */
+#define USB_PRODUCT_ZYXEL_NWD6605 0x3426 /* ND6605 */
+#define USB_PRODUCT_ZYXEL_PRESTIGE 0x401a /* Prestige */
diff --git a/rtemsbsd/include/rtems/bsd/local/usbdevs_data.h b/rtemsbsd/include/rtems/bsd/local/usbdevs_data.h
index 49ac75d7..6317c2d1 100644
--- a/rtemsbsd/include/rtems/bsd/local/usbdevs_data.h
+++ b/rtemsbsd/include/rtems/bsd/local/usbdevs_data.h
@@ -41,7 +41,7 @@ const struct usb_knowndev usb_knowndevs[] = {
USB_VENDOR_3COM, USB_PRODUCT_3COM_HOMECONN,
0,
"3Com",
- "HomeConnect Camera",
+ "HomeConnect USB Camera",
},
{
USB_VENDOR_3COM, USB_PRODUCT_3COM_3CREB96,
@@ -146,6 +146,24 @@ const struct usb_knowndev usb_knowndevs[] = {
"3G modem",
},
{
+ USB_VENDOR_ACDC, USB_PRODUCT_ACDC_HUB,
+ 0,
+ "American Computer & Digital Components",
+ "USB Pen Drive HUB",
+ },
+ {
+ USB_VENDOR_ACDC, USB_PRODUCT_ACDC_SECWRITE,
+ 0,
+ "American Computer & Digital Components",
+ "USB Pen Drive Secure Write",
+ },
+ {
+ USB_VENDOR_ACDC, USB_PRODUCT_ACDC_PEN,
+ 0,
+ "American Computer & Digital Components",
+ "USB Pen Drive with Secure Write",
+ },
+ {
USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_XX1,
0,
"AboCom Systems",
@@ -632,6 +650,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"AWN-8020 WLAN",
},
{
+ USB_VENDOR_ADDONICS2, USB_PRODUCT_ADDONICS2_205,
+ 0,
+ "Addonics Technology",
+ "Cable 205",
+ },
+ {
USB_VENDOR_ADDTRON, USB_PRODUCT_ADDTRON_AWU120,
0,
"Addtron",
@@ -950,6 +974,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"3G modem",
},
{
+ USB_VENDOR_ALINK, USB_PRODUCT_ALINK_SIM7600E,
+ 0,
+ "Alink",
+ "LTE modem",
+ },
+ {
USB_VENDOR_ALINK, USB_PRODUCT_ALINK_3GU,
0,
"Alink",
@@ -3752,6 +3782,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"DWA-140 rev B3",
},
{
+ USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA125A3,
+ 0,
+ "D-Link",
+ "DWA-125 rev A3",
+ },
+ {
USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA160B2,
0,
"D-Link",
@@ -4774,19 +4810,19 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_EVOLUTION, USB_PRODUCT_EVOLUTION_ER1,
0,
- "Evolution Robotics products",
+ "Evolution Robotics",
"FTDI compatible adapter",
},
{
USB_VENDOR_EVOLUTION, USB_PRODUCT_EVOLUTION_HYBRID,
0,
- "Evolution Robotics products",
+ "Evolution Robotics",
"FTDI compatible adapter",
},
{
USB_VENDOR_EVOLUTION, USB_PRODUCT_EVOLUTION_RCM4,
0,
- "Evolution Robotics products",
+ "Evolution Robotics",
"FTDI compatible adapter",
},
{
@@ -4876,13 +4912,13 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_FOXCONN, USB_PRODUCT_FOXCONN_TCOM_TC_300,
0,
- "Foxconn",
+ "Foxconn / Hon Hai",
"T-Com TC 300",
},
{
USB_VENDOR_FOXCONN, USB_PRODUCT_FOXCONN_PIRELLI_DP_L10,
0,
- "Foxconn",
+ "Foxconn / Hon Hai",
"Pirelli DP-L10",
},
{
@@ -6398,6 +6434,18 @@ const struct usb_knowndev usb_knowndevs[] = {
"GL850G USB 2.0 HUB",
},
{
+ USB_VENDOR_GENESYS, USB_PRODUCT_GENESYS_GL3520_2,
+ 0,
+ "Genesys Logic",
+ "GL3520 4-Port USB 2.0 DataPath",
+ },
+ {
+ USB_VENDOR_GENESYS, USB_PRODUCT_GENESYS_GL3520_SS,
+ 0,
+ "Genesys Logic",
+ "GL3520 4-Port USB 3.0 DataPath",
+ },
+ {
USB_VENDOR_GENESYS, USB_PRODUCT_GENESYS_GL641USB,
0,
"Genesys Logic",
@@ -6416,6 +6464,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"GL641USB USB-IDE Bridge",
},
{
+ USB_VENDOR_GENESYS, USB_PRODUCT_GENESYS_GL3233,
+ 0,
+ "Genesys Logic",
+ "GL3233 USB 3.0 AiO Card Reader",
+ },
+ {
USB_VENDOR_GENESYS, USB_PRODUCT_GENESYS_GL641USB_2,
0,
"Genesys Logic",
@@ -6548,6 +6602,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"AR5523 (no firmware)",
},
{
+ USB_VENDOR_GLOBESPAN, USB_PRODUCT_GLOBESPAN_MODEM_1,
+ 0,
+ "Globespan",
+ "USB Modem",
+ },
+ {
USB_VENDOR_GLOBESPAN, USB_PRODUCT_GLOBESPAN_PRISM_GT_1,
0,
"Globespan",
@@ -7904,6 +7964,30 @@ const struct usb_knowndev usb_knowndevs[] = {
"Integrated Rate Matching Hub",
},
{
+ USB_VENDOR_INTEL2, USB_PRODUCT_INTEL2_SFP,
+ 0,
+ "Intel",
+ "Sandy Peak (3168) Bluetooth Module",
+ },
+ {
+ USB_VENDOR_INTEL2, USB_PRODUCT_INTEL2_JFP,
+ 0,
+ "Intel",
+ "Jefferson Peak (9460/9560) Bluetooth Module",
+ },
+ {
+ USB_VENDOR_INTEL2, USB_PRODUCT_INTEL2_THP,
+ 0,
+ "Intel",
+ "Thunder Peak (9160/9260) Bluetooth Module",
+ },
+ {
+ USB_VENDOR_INTEL2, USB_PRODUCT_INTEL2_HSP,
+ 0,
+ "Intel",
+ "Harrison Peak (22560) Bluetooth Module",
+ },
+ {
USB_VENDOR_INTERBIOMETRICS, USB_PRODUCT_INTERBIOMETRICS_IOBOARD,
0,
"Interbiometrics",
@@ -12128,6 +12212,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"NovAtel FlexPack GPS receiver",
},
{
+ USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_RTL8153,
+ 0,
+ "NVIDIA Corporation",
+ "USB 3.0 Ethernet",
+ },
+ {
USB_VENDOR_MERLIN, USB_PRODUCT_MERLIN_V620,
0,
"Merlin",
@@ -12920,6 +13010,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"Ethernet",
},
{
+ USB_VENDOR_PERASO, USB_PRODUCT_PERASO_PRS4001,
+ 0,
+ "Peraso Technologies, Inc.",
+ "PRS4001 WLAN",
+ },
+ {
USB_VENDOR_PHILIPS, USB_PRODUCT_PHILIPS_DSS350,
0,
"Philips",
@@ -12950,6 +13046,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"PCVC680K Vesta Pro PC Camera",
},
{
+ USB_VENDOR_PHILIPS, USB_PRODUCT_PHILIPS_SPC900NC,
+ 0,
+ "Philips",
+ "SPC 900NC CCD PC Camera",
+ },
+ {
USB_VENDOR_PHILIPS, USB_PRODUCT_PHILIPS_DSS150,
0,
"Philips",
@@ -14240,6 +14342,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"RT5370",
},
{
+ USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT5372,
+ 0,
+ "Ralink Technology",
+ "RT5372",
+ },
+ {
USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT5572,
0,
"Ralink Technology",
@@ -14686,13 +14794,13 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_RTSYSTEMS, USB_PRODUCT_RTSYSTEMS_CT29B,
0,
- "RTSYSTEMS",
+ "RT Systems",
"FTDI compatible adapter",
},
{
USB_VENDOR_RTSYSTEMS, USB_PRODUCT_RTSYSTEMS_SERIAL_VX7,
0,
- "RTSYSTEMS",
+ "RT Systems",
"FTDI compatible adapter",
},
{
@@ -16570,13 +16678,13 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_2020HUB,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB Hub",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_2514HUB,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB Hub",
},
{
@@ -16586,111 +16694,129 @@ const struct usb_knowndev usb_knowndevs[] = {
"2662W-AR Wireless",
},
{
+ USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7800_ETH,
+ 0,
+ "Microchip (Standard Microsystems)",
+ "USB/Ethernet",
+ },
+ {
+ USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7801_ETH,
+ 0,
+ "Microchip (Standard Microsystems)",
+ "USB/Ethernet",
+ },
+ {
+ USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN7850_ETH,
+ 0,
+ "Microchip (Standard Microsystems)",
+ "USB/Ethernet",
+ },
+ {
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9505_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9530_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9730_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500_SAL10,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9505_SAL10,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500A_SAL10,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9505A_SAL10,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9514_SAL10,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500A_HAL,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9505A_HAL,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500_ETH_2,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500A_ETH_2,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9514_ETH_2,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9500A_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9505A_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN89530_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
USB_VENDOR_SMC2, USB_PRODUCT_SMC2_LAN9514_ETH,
0,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
"USB/Ethernet",
},
{
@@ -18140,12 +18266,78 @@ const struct usb_knowndev usb_knowndevs[] = {
"UX256 MIDI I/F",
},
{
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_MU1000,
+ 0,
+ "YAMAHA",
+ "MU1000 MIDI Synth.",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_MU2000,
+ 0,
+ "YAMAHA",
+ "MU2000 MIDI Synth.",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_MU500,
+ 0,
+ "YAMAHA",
+ "MU500 MIDI Synth.",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_UW500,
+ 0,
+ "YAMAHA",
+ "UW500 USB Audio I/F",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_MOTIF6,
+ 0,
+ "YAMAHA",
+ "MOTIF6 MIDI Synth. Workstation",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_MOTIF7,
+ 0,
+ "YAMAHA",
+ "MOTIF7 MIDI Synth. Workstation",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_MOTIF8,
+ 0,
+ "YAMAHA",
+ "MOTIF8 MIDI Synth. Workstation",
+ },
+ {
USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_UX96,
0,
"YAMAHA",
"UX96 MIDI I/F",
},
{
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_UX16,
+ 0,
+ "YAMAHA",
+ "UX16 MIDI I/F",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_S08,
+ 0,
+ "YAMAHA",
+ "S08 MIDI Keyboard",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_CLP150,
+ 0,
+ "YAMAHA",
+ "CLP-150 digital piano",
+ },
+ {
+ USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_CLP170,
+ 0,
+ "YAMAHA",
+ "CLP-170 digital piano",
+ },
+ {
USB_VENDOR_YAMAHA, USB_PRODUCT_YAMAHA_RPU200,
0,
"YAMAHA",
@@ -18284,6 +18476,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"UB82",
},
{
+ USB_VENDOR_ZEEVO, USB_PRODUCT_ZEEVO_BLUETOOTH,
+ 0,
+ "Zeevo, Inc.",
+ "BT-500 Bluetooth USB Adapter",
+ },
+ {
USB_VENDOR_ZINWELL, USB_PRODUCT_ZINWELL_RT2570,
0,
"Zinwell",
@@ -18326,12 +18524,72 @@ const struct usb_knowndev usb_knowndevs[] = {
"2986L Fax modem",
},
{
+ USB_VENDOR_ZOOM, USB_PRODUCT_ZOOM_3095,
+ 0,
+ "Zoom Telephonics",
+ "3095 USB Fax modem",
+ },
+ {
USB_VENDOR_ZORAN, USB_PRODUCT_ZORAN_EX20DSC,
0,
"Zoran Microelectronics",
"Digital Camera EX-20 DSC",
},
{
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_MF622,
+ 0,
+ "ZTE",
+ "MF622 modem",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_MF628,
+ 0,
+ "ZTE",
+ "MF628 modem",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_MF626,
+ 0,
+ "ZTE",
+ "MF626 modem",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_MF820D_INSTALLER,
+ 0,
+ "ZTE",
+ "MF820D CD",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_MF820D,
+ 0,
+ "ZTE",
+ "MF820D modem",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_INSTALLER,
+ 0,
+ "ZTE",
+ "UMTS CD",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_MC2718,
+ 0,
+ "ZTE",
+ "MC2718 modem",
+ },
+ {
+ USB_VENDOR_ZTE, USB_PRODUCT_ZTE_AC8700,
+ 0,
+ "ZTE",
+ "CDMA 1xEVDO USB modem",
+ },
+ {
+ USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1201,
+ 0,
+ "Zydas Technology Corporation",
+ "ZD1201",
+ },
+ {
USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1211,
0,
"Zydas Technology Corporation",
@@ -18350,6 +18608,18 @@ const struct usb_knowndev usb_knowndevs[] = {
"ZD1221",
},
{
+ USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ALL0298,
+ 0,
+ "Zydas Technology Corporation",
+ "ALL0298",
+ },
+ {
+ USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1211B_2,
+ 0,
+ "Zydas Technology Corporation",
+ "ZD1211B",
+ },
+ {
USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_OMNI56K,
0,
"ZyXEL Communication",
@@ -18386,6 +18656,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"M-202",
},
{
+ USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_G270S,
+ 0,
+ "ZyXEL Communication",
+ "G-270S",
+ },
+ {
USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_G220V2,
0,
"ZyXEL Communication",
@@ -18398,6 +18674,12 @@ const struct usb_knowndev usb_knowndevs[] = {
"G-202",
},
{
+ USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RT2573,
+ 0,
+ "ZyXEL Communication",
+ "RT2573",
+ },
+ {
USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RT2870_1,
0,
"ZyXEL Communication",
@@ -18443,7 +18725,13 @@ const struct usb_knowndev usb_knowndevs[] = {
USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD6605,
0,
"ZyXEL Communication",
- "NWD6605",
+ "ND6605",
+ },
+ {
+ USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_PRESTIGE,
+ 0,
+ "ZyXEL Communication",
+ "Prestige",
},
{
USB_VENDOR_UNKNOWN1, 0,
@@ -18476,9 +18764,9 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
- USB_VENDOR_INTENSO, 0,
+ USB_VENDOR_QUAN, 0,
USB_KNOWNDEV_NOPROD,
- "INTENSO",
+ "Quan",
NULL,
},
{
@@ -18670,7 +18958,7 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_WELTREND, 0,
USB_KNOWNDEV_NOPROD,
- "Weltrend",
+ "Weltrend Semiconductor",
NULL,
},
{
@@ -18736,7 +19024,7 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_SMC2, 0,
USB_KNOWNDEV_NOPROD,
- "Standard Microsystems",
+ "Microchip (Standard Microsystems)",
NULL,
},
{
@@ -18988,7 +19276,7 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_FOXCONN, 0,
USB_KNOWNDEV_NOPROD,
- "Foxconn",
+ "Foxconn / Hon Hai",
NULL,
},
{
@@ -19300,7 +19588,7 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_ELAN, 0,
USB_KNOWNDEV_NOPROD,
- "Elan",
+ "ELAN Microelectronics",
NULL,
},
{
@@ -19640,6 +19928,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_NINTENDO, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Nintendo",
+ NULL,
+ },
+ {
USB_VENDOR_QUICKSHOT, 0,
USB_KNOWNDEV_NOPROD,
"Quickshot",
@@ -19982,6 +20276,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_SMK, 0,
+ USB_KNOWNDEV_NOPROD,
+ "SMK",
+ NULL,
+ },
+ {
USB_VENDOR_SOLIDYEAR, 0,
USB_KNOWNDEV_NOPROD,
"Solid Year",
@@ -20306,6 +20606,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_MADCATZ, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Mad Catz, Inc.",
+ NULL,
+ },
+ {
USB_VENDOR_SYNTECH, 0,
USB_KNOWNDEV_NOPROD,
"Syntech Information",
@@ -20480,6 +20786,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_KINGSUN, 0,
+ USB_KNOWNDEV_NOPROD,
+ "KingSun",
+ NULL,
+ },
+ {
USB_VENDOR_KEISOKUGIKEN, 0,
USB_KNOWNDEV_NOPROD,
"Keisokugiken",
@@ -20558,6 +20870,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_BEWAN, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Bewan",
+ NULL,
+ },
+ {
USB_VENDOR_CENTURY, 0,
USB_KNOWNDEV_NOPROD,
"Century Corp",
@@ -20588,6 +20906,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_SYNET, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Synet Electronics",
+ NULL,
+ },
+ {
USB_VENDOR_ALPHASMART, 0,
USB_KNOWNDEV_NOPROD,
"AlphaSmart, Inc.",
@@ -20882,6 +21206,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_NVIDIA, 0,
+ USB_KNOWNDEV_NOPROD,
+ "NVIDIA Corporation",
+ NULL,
+ },
+ {
USB_VENDOR_BLUEWATER, 0,
USB_KNOWNDEV_NOPROD,
"BlueWater Systems",
@@ -20930,6 +21260,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_ZIPPY, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Zippy Technology Corporation",
+ NULL,
+ },
+ {
USB_VENDOR_POINTCHIPS, 0,
USB_KNOWNDEV_NOPROD,
"PointChips",
@@ -20942,6 +21278,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_TRIPPLITE2, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Tripp Lite",
+ NULL,
+ },
+ {
USB_VENDOR_ALTIUS, 0,
USB_KNOWNDEV_NOPROD,
"Altius Solutions",
@@ -21160,7 +21502,7 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_ATI2, 0,
USB_KNOWNDEV_NOPROD,
- "ATI",
+ "ATI Technologies",
NULL,
},
{
@@ -21554,6 +21896,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_DVICO, 0,
+ USB_KNOWNDEV_NOPROD,
+ "DViCO",
+ NULL,
+ },
+ {
USB_VENDOR_QUALCOMM, 0,
USB_KNOWNDEV_NOPROD,
"Qualcomm",
@@ -21590,6 +21938,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_AMD2, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Advanced Micro Devices",
+ NULL,
+ },
+ {
USB_VENDOR_NEC3, 0,
USB_KNOWNDEV_NOPROD,
"NEC",
@@ -21794,6 +22148,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_FUJITSU3, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Fujitsu Ltd.",
+ NULL,
+ },
+ {
USB_VENDOR_UNKNOWN3, 0,
USB_KNOWNDEV_NOPROD,
"Unknown vendor",
@@ -21896,6 +22256,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_VALIDITY, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Validity Sensors, Inc.",
+ NULL,
+ },
+ {
USB_VENDOR_BALTECH, 0,
USB_KNOWNDEV_NOPROD,
"Baltech",
@@ -21938,6 +22304,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_OMNIVISION2, 0,
+ USB_KNOWNDEV_NOPROD,
+ "OmniVision Technologies, Inc.",
+ NULL,
+ },
+ {
USB_VENDOR_MERLIN, 0,
USB_KNOWNDEV_NOPROD,
"Merlin",
@@ -22262,6 +22634,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_MISC, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Misc Vendors",
+ NULL,
+ },
+ {
USB_VENDOR_DISPLAYLINK, 0,
USB_KNOWNDEV_NOPROD,
"DisplayLink",
@@ -22286,6 +22664,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_E3C, 0,
+ USB_KNOWNDEV_NOPROD,
+ "E3C Technologies",
+ NULL,
+ },
+ {
USB_VENDOR_AMIT, 0,
USB_KNOWNDEV_NOPROD,
"AMIT",
@@ -22316,6 +22700,24 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_MEINBERG, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Meinberg Funkuhren",
+ NULL,
+ },
+ {
+ USB_VENDOR_BECEEM, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Beceem Communications",
+ NULL,
+ },
+ {
+ USB_VENDOR_ZTE, 0,
+ USB_KNOWNDEV_NOPROD,
+ "ZTE",
+ NULL,
+ },
+ {
USB_VENDOR_QUALCOMMINC, 0,
USB_KNOWNDEV_NOPROD,
"Qualcomm, Incorporated",
@@ -22328,6 +22730,18 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_QUANTA2, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Quanta",
+ NULL,
+ },
+ {
+ USB_VENDOR_TERMINUS, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Terminus Technology",
+ NULL,
+ },
+ {
USB_VENDOR_ABBOTT, 0,
USB_KNOWNDEV_NOPROD,
"Abbott Diabetics",
@@ -22558,7 +22972,19 @@ const struct usb_knowndev usb_knowndevs[] = {
{
USB_VENDOR_RTSYSTEMS, 0,
USB_KNOWNDEV_NOPROD,
- "RTSYSTEMS",
+ "RT Systems",
+ NULL,
+ },
+ {
+ USB_VENDOR_DLINK4, 0,
+ USB_KNOWNDEV_NOPROD,
+ "D-Link",
+ NULL,
+ },
+ {
+ USB_VENDOR_INTENSO, 0,
+ USB_KNOWNDEV_NOPROD,
+ "INTENSO",
NULL,
},
{
@@ -22586,6 +23012,18 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_PINNACLE, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Pinnacle Systems",
+ NULL,
+ },
+ {
+ USB_VENDOR_ARDUINO, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Arduino SA",
+ NULL,
+ },
+ {
USB_VENDOR_TPLINK, 0,
USB_KNOWNDEV_NOPROD,
"TP-Link",
@@ -22622,6 +23060,12 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_PERASO, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Peraso Technologies, Inc.",
+ NULL,
+ },
+ {
USB_VENDOR_PLANEX, 0,
USB_KNOWNDEV_NOPROD,
"Planex Communications",
@@ -22754,12 +23198,24 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_INGENIC, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Ingenic Semiconductor Ltd.",
+ NULL,
+ },
+ {
USB_VENDOR_SITECOM, 0,
USB_KNOWNDEV_NOPROD,
"Sitecom",
NULL,
},
{
+ USB_VENDOR_SPRINGERDESIGN, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Springer Design, Inc.",
+ NULL,
+ },
+ {
USB_VENDOR_ARKMICRO, 0,
USB_KNOWNDEV_NOPROD,
"Arkmicro Technologies Inc.",
@@ -22832,9 +23288,9 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
- USB_VENDOR_EVOLUTION, 0,
+ USB_VENDOR_COMPARE, 0,
USB_KNOWNDEV_NOPROD,
- "Evolution Robotics products",
+ "Compare",
NULL,
},
{
@@ -22844,6 +23300,18 @@ const struct usb_knowndev usb_knowndevs[] = {
NULL,
},
{
+ USB_VENDOR_EVOLUTION, 0,
+ USB_KNOWNDEV_NOPROD,
+ "Evolution Robotics",
+ NULL,
+ },
+ {
+ USB_VENDOR_EMPIA, 0,
+ USB_KNOWNDEV_NOPROD,
+ "eMPIA Technology",
+ NULL,
+ },
+ {
USB_VENDOR_HP2, 0,
USB_KNOWNDEV_NOPROD,
"Hewlett Packard",
diff --git a/rtemsbsd/include/sys/boot.h b/rtemsbsd/include/sys/boot.h
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/rtemsbsd/include/sys/boot.h
diff --git a/rtemsbsd/include/sys/epoch.h b/rtemsbsd/include/sys/epoch.h
index 25000a6d..d268efff 100644
--- a/rtemsbsd/include/sys/epoch.h
+++ b/rtemsbsd/include/sys/epoch.h
@@ -100,8 +100,8 @@ SYSINIT(epoch_##name, SI_SUB_TUNABLES, SI_ORDER_THIRD, \
void _bsd_epoch_init(epoch_t epoch, uintptr_t pcpu_record_offset,
int flags);
-void epoch_enter_preempt(epoch_t epoch);
-void epoch_exit_preempt(epoch_t epoch);
+void epoch_enter_preempt(epoch_t epoch, epoch_tracker_t et);
+void epoch_exit_preempt(epoch_t epoch, epoch_tracker_t et);
void epoch_wait(epoch_t epoch);
void epoch_wait_preempt(epoch_t epoch);
diff --git a/rtemsbsd/include/sys/kpilite.h b/rtemsbsd/include/sys/kpilite.h
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/rtemsbsd/include/sys/kpilite.h
diff --git a/rtemsbsd/include/vm/vm_pager.h b/rtemsbsd/include/vm/vm_pager.h
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/rtemsbsd/include/vm/vm_pager.h
diff --git a/rtemsbsd/local/cryptodev_if.c b/rtemsbsd/local/cryptodev_if.c
index 648003d8..a989d0e8 100644
--- a/rtemsbsd/local/cryptodev_if.c
+++ b/rtemsbsd/local/cryptodev_if.c
@@ -20,35 +20,26 @@
#include <opencrypto/cryptodev.h>
#include <rtems/bsd/local/cryptodev_if.h>
-struct kobj_method cryptodev_newsession_method_default = {
- &cryptodev_newsession_desc, (kobjop_t) kobj_error_method
-};
-struct kobjop_desc cryptodev_newsession_desc = {
- 0, &cryptodev_newsession_method_default
-};
+static int null_freesession(device_t dev,
+ crypto_session_t crypto_session)
+{
+ return 0;
+}
-struct kobj_method cryptodev_freesession_method_default = {
- &cryptodev_freesession_desc, (kobjop_t) kobj_error_method
+struct kobjop_desc cryptodev_newsession_desc = {
+ 0, { &cryptodev_newsession_desc, (kobjop_t)kobj_error_method }
};
struct kobjop_desc cryptodev_freesession_desc = {
- 0, &cryptodev_freesession_method_default
-};
-
-struct kobj_method cryptodev_process_method_default = {
- &cryptodev_process_desc, (kobjop_t) kobj_error_method
+ 0, { &cryptodev_freesession_desc, (kobjop_t)null_freesession }
};
struct kobjop_desc cryptodev_process_desc = {
- 0, &cryptodev_process_method_default
-};
-
-struct kobj_method cryptodev_kprocess_method_default = {
- &cryptodev_kprocess_desc, (kobjop_t) kobj_error_method
+ 0, { &cryptodev_process_desc, (kobjop_t)kobj_error_method }
};
struct kobjop_desc cryptodev_kprocess_desc = {
- 0, &cryptodev_kprocess_method_default
+ 0, { &cryptodev_kprocess_desc, (kobjop_t)kobj_error_method }
};
diff --git a/rtemsbsd/local/ifdi_if.c b/rtemsbsd/local/ifdi_if.c
index e5a81946..e9337b8d 100644
--- a/rtemsbsd/local/ifdi_if.c
+++ b/rtemsbsd/local/ifdi_if.c
@@ -26,6 +26,9 @@
#include <net/if_var.h>
#include <net/if_media.h>
#include <net/iflib.h>
+#include <net/if_clone.h>
+#include <net/if_dl.h>
+#include <net/if_types.h>
#include <rtems/bsd/local/ifdi_if.h>
@@ -35,6 +38,18 @@
{
}
+ static int
+ null_knlist_add(if_ctx_t _ctx __unused, struct knote *_kn)
+ {
+ return (0);
+ }
+
+ static int
+ null_knote_event(if_ctx_t _ctx __unused, struct knote *_kn, int _hint)
+ {
+ return (0);
+ }
+
static void
null_timer_op(if_ctx_t _ctx __unused, uint16_t _qsidx __unused)
{
@@ -47,6 +62,12 @@
}
static int
+ null_int_int_op(if_ctx_t _ctx __unused, int arg0 __unused)
+ {
+ return (ENOTSUP);
+ }
+
+ static int
null_queue_intr_enable(if_ctx_t _ctx __unused, uint16_t _qid __unused)
{
return (ENOTSUP);
@@ -98,12 +119,73 @@
return (ENOTSUP);
}
+ static void
+ null_media_status(if_ctx_t ctx __unused, struct ifmediareq *ifmr)
+ {
+ ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
+ ifmr->ifm_active = IFM_ETHER | IFM_25G_ACC | IFM_FDX;
+ }
+
+ static int
+ null_cloneattach(if_ctx_t ctx __unused, struct if_clone *ifc __unused,
+ const char *name __unused, caddr_t params __unused)
+ {
+ return (0);
+ }
+
+ static void
+ null_rx_clset(if_ctx_t _ctx __unused, uint16_t _flid __unused,
+ uint16_t _qid __unused, caddr_t *_sdcl __unused)
+ {
+ }
+ static void
+ null_object_info_get(if_ctx_t ctx __unused, void *data __unused, int size __unused)
+ {
+ }
+ static int
+ default_mac_set(if_ctx_t ctx, const uint8_t *mac)
+ {
+ struct ifnet *ifp = iflib_get_ifp(ctx);
+ struct sockaddr_dl *sdl;
+
+ if (ifp && ifp->if_addr) {
+ sdl = (struct sockaddr_dl *)ifp->if_addr->ifa_addr;
+ MPASS(sdl->sdl_type == IFT_ETHER);
+ memcpy(LLADDR(sdl), mac, ETHER_ADDR_LEN);
+ }
+ return (0);
+ }
+
+struct kobjop_desc ifdi_knlist_add_desc = {
+ 0, { &ifdi_knlist_add_desc, (kobjop_t)null_knlist_add }
+};
+
+struct kobjop_desc ifdi_knote_event_desc = {
+ 0, { &ifdi_knote_event_desc, (kobjop_t)null_knote_event }
+};
+
+struct kobjop_desc ifdi_object_info_get_desc = {
+ 0, { &ifdi_object_info_get_desc, (kobjop_t)null_object_info_get }
+};
+
struct kobjop_desc ifdi_attach_pre_desc = {
- 0, { &ifdi_attach_pre_desc, (kobjop_t)kobj_error_method }
+ 0, { &ifdi_attach_pre_desc, (kobjop_t)null_int_op }
};
struct kobjop_desc ifdi_attach_post_desc = {
- 0, { &ifdi_attach_post_desc, (kobjop_t)kobj_error_method }
+ 0, { &ifdi_attach_post_desc, (kobjop_t)null_int_op }
+};
+
+struct kobjop_desc ifdi_reinit_pre_desc = {
+ 0, { &ifdi_reinit_pre_desc, (kobjop_t)null_int_op }
+};
+
+struct kobjop_desc ifdi_reinit_post_desc = {
+ 0, { &ifdi_reinit_post_desc, (kobjop_t)null_int_op }
+};
+
+struct kobjop_desc ifdi_cloneattach_desc = {
+ 0, { &ifdi_cloneattach_desc, (kobjop_t)null_cloneattach }
};
struct kobjop_desc ifdi_detach_desc = {
@@ -131,7 +213,11 @@ struct kobjop_desc ifdi_rx_queues_alloc_desc = {
};
struct kobjop_desc ifdi_queues_free_desc = {
- 0, { &ifdi_queues_free_desc, (kobjop_t)kobj_error_method }
+ 0, { &ifdi_queues_free_desc, (kobjop_t)null_void_op }
+};
+
+struct kobjop_desc ifdi_rx_clset_desc = {
+ 0, { &ifdi_rx_clset_desc, (kobjop_t)null_rx_clset }
};
struct kobjop_desc ifdi_init_desc = {
@@ -143,7 +229,7 @@ struct kobjop_desc ifdi_stop_desc = {
};
struct kobjop_desc ifdi_msix_intr_assign_desc = {
- 0, { &ifdi_msix_intr_assign_desc, (kobjop_t)kobj_error_method }
+ 0, { &ifdi_msix_intr_assign_desc, (kobjop_t)null_int_int_op }
};
struct kobjop_desc ifdi_intr_enable_desc = {
@@ -174,6 +260,10 @@ struct kobjop_desc ifdi_mtu_set_desc = {
0, { &ifdi_mtu_set_desc, (kobjop_t)kobj_error_method }
};
+struct kobjop_desc ifdi_mac_set_desc = {
+ 0, { &ifdi_mac_set_desc, (kobjop_t)default_mac_set }
+};
+
struct kobjop_desc ifdi_media_set_desc = {
0, { &ifdi_media_set_desc, (kobjop_t)null_void_op }
};
@@ -207,11 +297,11 @@ struct kobjop_desc ifdi_update_admin_status_desc = {
};
struct kobjop_desc ifdi_media_status_desc = {
- 0, { &ifdi_media_status_desc, (kobjop_t)kobj_error_method }
+ 0, { &ifdi_media_status_desc, (kobjop_t)null_media_status }
};
struct kobjop_desc ifdi_media_change_desc = {
- 0, { &ifdi_media_change_desc, (kobjop_t)kobj_error_method }
+ 0, { &ifdi_media_change_desc, (kobjop_t)null_int_op }
};
struct kobjop_desc ifdi_get_counter_desc = {
@@ -242,6 +332,10 @@ struct kobjop_desc ifdi_watchdog_reset_desc = {
0, { &ifdi_watchdog_reset_desc, (kobjop_t)null_void_op }
};
+struct kobjop_desc ifdi_watchdog_reset_queue_desc = {
+ 0, { &ifdi_watchdog_reset_queue_desc, (kobjop_t)null_timer_op }
+};
+
struct kobjop_desc ifdi_led_func_desc = {
0, { &ifdi_led_func_desc, (kobjop_t)null_led_func }
};
diff --git a/rtemsbsd/local/sdhci_if.c b/rtemsbsd/local/sdhci_if.c
index 1d6c26d4..e50e7a47 100644
--- a/rtemsbsd/local/sdhci_if.c
+++ b/rtemsbsd/local/sdhci_if.c
@@ -16,10 +16,12 @@
#include <sys/queue.h>
#include <sys/kernel.h>
#include <sys/kobj.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
#include <sys/types.h>
-#include <sys/bus.h>
#include <sys/sysctl.h>
#include <sys/taskqueue.h>
+#include <machine/bus.h>
#include <dev/mmc/bridge.h>
#include <dev/sdhci/sdhci.h>
diff --git a/rtemsbsd/rtems/rtems-kernel-epoch.c b/rtemsbsd/rtems/rtems-kernel-epoch.c
index 9eb8487c..7d42bf32 100644
--- a/rtemsbsd/rtems/rtems-kernel-epoch.c
+++ b/rtemsbsd/rtems/rtems-kernel-epoch.c
@@ -165,8 +165,8 @@ epoch_sysinit(void)
}
SYSINIT(epoch, SI_SUB_TUNABLES, SI_ORDER_SECOND, epoch_sysinit, NULL);
-static void
-epoch_enter_preempt_next(epoch_t epoch, epoch_tracker_t et)
+void
+epoch_enter_preempt(epoch_t epoch, epoch_tracker_t et)
{
Per_CPU_Control *cpu_self;
ISR_lock_Context lock_context;
@@ -189,8 +189,8 @@ epoch_enter_preempt_next(epoch_t epoch, epoch_tracker_t et)
_Thread_Dispatch_enable(cpu_self);
}
-static void
-epoch_exit_preempt_next(epoch_t epoch, epoch_tracker_t et)
+void
+epoch_exit_preempt(epoch_t epoch, epoch_tracker_t et)
{
Per_CPU_Control *cpu_self;
ISR_lock_Context lock_context;
@@ -215,23 +215,6 @@ epoch_exit_preempt_next(epoch_t epoch, epoch_tracker_t et)
}
}
-/* FIXME: Must be removed in next FreeBSD baseline update step. */
-static __thread epoch_tracker_t et;
-
-void
-epoch_enter_preempt(epoch_t epoch)
-{
-
- epoch_enter_preempt_next(epoch, &et);
-}
-
-void
-epoch_exit_preempt(epoch_t epoch)
-{
-
- epoch_exit_preempt_next(epoch, &et);
-}
-
static void
epoch_block_handler(struct ck_epoch *g __unused, ck_epoch_record_t *c __unused,
void *arg __unused)
diff --git a/rtemsbsd/sys/arm/at91/at91_mci.c b/rtemsbsd/sys/arm/at91/at91_mci.c
new file mode 100644
index 00000000..c25983b7
--- /dev/null
+++ b/rtemsbsd/sys/arm/at91/at91_mci.c
@@ -0,0 +1,1713 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2006 Bernd Walter. All rights reserved.
+ * Copyright (c) 2006 M. Warner Losh.
+ * Copyright (c) 2010 Greg Ansley. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <rtems/bsd/local/opt_platform.h>
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <rtems/bsd/sys/resource.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <machine/intr.h>
+
+#include <arm/at91/at91var.h>
+#include <arm/at91/at91_mcireg.h>
+#include <arm/at91/at91_pdcreg.h>
+
+#include <dev/mmc/bridge.h>
+#include <dev/mmc/mmcbrvar.h>
+
+#ifdef FDT
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#endif
+
+#include <rtems/bsd/local/mmcbr_if.h>
+
+#include <rtems/bsd/local/opt_at91.h>
+
+#ifdef __rtems__
+#include <bsp.h>
+#endif /* __rtems__ */
+#if defined(__rtems__) && defined(LIBBSP_ARM_ATSAM_BSP_H)
+#ifdef __rtems__
+#include <rtems/irq-extension.h>
+#include <libchip/chip.h>
+
+#define AT91_MCI_HAS_4WIRE 1
+
+#define at91_master_clock BOARD_MCK
+
+static sXdmad *pXdmad = &XDMAD_Instance;
+#endif /* __rtems__ */
+/*
+ * About running the MCI bus above 25MHz
+ *
+ * Historically, the MCI bus has been run at 30MHz on systems with a 60MHz
+ * master clock, in part due to a bug in dev/mmc.c making always request
+ * 30MHz, and in part over clocking the bus because 15MHz was too slow.
+ * Fixing that bug causes the mmc driver to request a 25MHz clock (as it
+ * should) and the logic in at91_mci_update_ios() picks the highest speed that
+ * doesn't exceed that limit. With a 60MHz MCK that would be 15MHz, and
+ * that's a real performance buzzkill when you've been getting away with 30MHz
+ * all along.
+ *
+ * By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1
+ * device hint or sysctl) you can enable logic in at91_mci_update_ios() to
+ * overlcock the SD bus a little by running it at MCK / 2 when the requested
+ * speed is 25MHz and the next highest speed is 15MHz or less. This appears
+ * to work on virtually all SD cards, since it is what this driver has been
+ * doing prior to the introduction of this option, where the overclocking vs
+ * underclocking decision was automatically "overclock". Modern SD cards can
+ * run at 45mhz/1-bit in standard mode (high speed mode enable commands not
+ * sent) without problems.
+ *
+ * Speaking of high-speed mode, the rm9200 manual says the MCI device supports
+ * the SD v1.0 specification and can run up to 50MHz. This is interesting in
+ * that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in
+ * the v1.10 spec. Furthermore, high speed mode doesn't just crank up the
+ * clock, it alters the signal timing. The rm9200 MCI device doesn't support
+ * these altered timings. So while speeds over 25MHz may work, they only work
+ * in what the SD spec calls "default" speed mode, and it amounts to violating
+ * the spec by overclocking the bus.
+ *
+ * If you also enable 4-wire mode it's possible transfers faster than 25MHz
+ * will fail. On the AT91RM9200, due to bugs in the bus contention logic, if
+ * you have the USB host device and OHCI driver enabled will fail. Even
+ * underclocking to 15MHz, intermittant overrun and underrun errors occur.
+ * Note that you don't even need to have usb devices attached to the system,
+ * the errors begin to occur as soon as the OHCI driver sets the register bit
+ * to enable periodic transfers. It appears (based on brief investigation)
+ * that the usb host controller uses so much ASB bandwidth that sometimes the
+ * DMA for MCI transfers doesn't get a bus grant in time and data gets
+ * dropped. Adding even a modicum of network activity changes the symptom
+ * from intermittant to very frequent. Members of the AT91SAM9 family have
+ * corrected this problem, or are at least better about their use of the bus.
+ */
+#ifndef AT91_MCI_ALLOW_OVERCLOCK
+#define AT91_MCI_ALLOW_OVERCLOCK 1
+#endif
+
+/*
+ * Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200
+ * erratum. We use a pair of buffers because when reading that lets us begin
+ * endian-swapping the data in the first buffer while the DMA is reading into
+ * the second buffer. (We can't use the same trick for writing because we might
+ * not get all the data in the 2nd buffer swapped before the hardware needs it;
+ * dealing with that would add complexity to the driver.)
+ *
+ * The buffers are sized at 16K each due to the way the busdma cache sync
+ * operations work on arm. A dcache_inv_range() operation on a range larger
+ * than 16K gets turned into a dcache_wbinv_all(). That needlessly flushes the
+ * entire data cache, impacting overall system performance.
+ */
+#ifndef __rtems__
+#define BBCOUNT 2
+#define BBSIZE (32*1024)
+#define MAX_BLOCKS ((BBSIZE)/512)
+/* FIXME: It would be better to split the DMA up in that case like in the
+ * original driver. But that would need some rework. */
+#else /* __rtems__ */
+#define MAX_BLOCKS 256
+#endif /* __rtems__ */
+
+#ifndef __rtems__
+static int mci_debug;
+#else /* __rtems__ */
+#define mci_debug 0
+#endif /* __rtems__ */
+
+struct at91_mci_softc {
+ void *intrhand; /* Interrupt handle */
+ device_t dev;
+ int sc_cap;
+#define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
+#define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */
+#define CAP_MCI1_REV2XX 4 /* MCI 1 rev 2.x */
+ int flags;
+#define PENDING_CMD 0x01
+#define PENDING_STOP 0x02
+#define CMD_MULTIREAD 0x10
+#define CMD_MULTIWRITE 0x20
+ int has_4wire;
+ int allow_overclock;
+ struct resource *irq_res; /* IRQ resource */
+ struct resource *mem_res; /* Memory resource */
+ struct mtx sc_mtx;
+#ifdef __rtems__
+ RTEMS_INTERRUPT_LOCK_MEMBER(sc_lock)
+#endif /* __rtems__ */
+#ifndef __rtems__
+ bus_dma_tag_t dmatag;
+#endif /* __rtems__ */
+ struct mmc_host host;
+ int bus_busy;
+ struct mmc_request *req;
+ struct mmc_command *curcmd;
+#ifndef __rtems__
+ bus_dmamap_t bbuf_map[BBCOUNT];
+ char * bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
+ uint32_t bbuf_len[BBCOUNT]; /* len currently queued for bounce buf */
+ uint32_t bbuf_curidx; /* which bbuf is the active DMA buffer */
+ uint32_t xfer_offset; /* offset so far into caller's buf */
+#else /* __rtems__ */
+ LinkedListDescriporView1 xdma_desc;
+ uint32_t xdma_tx_channel;
+ uint32_t xdma_rx_channel;
+ uint8_t xdma_tx_perid;
+ uint8_t xdma_rx_perid;
+ sXdmadCfg xdma_tx_cfg;
+ sXdmadCfg xdma_rx_cfg;
+#endif /* __rtems__ */
+};
+
+/* bus entry points */
+static int at91_mci_probe(device_t dev);
+static int at91_mci_attach(device_t dev);
+static int at91_mci_detach(device_t dev);
+static void at91_mci_intr(void *);
+
+/* helper routines */
+static int at91_mci_activate(device_t dev);
+static void at91_mci_deactivate(device_t dev);
+static int at91_mci_is_mci1rev2xx(void);
+#ifndef __rtems__
+static void at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr);
+#endif /* __rtems__ */
+static void at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr);
+
+#ifndef __rtems__
+#define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
+#define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
+#define AT91_MCI_LOCK_INIT(_sc) \
+ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
+ "mci", MTX_DEF)
+#define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
+#define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
+#define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
+#else /* __rtems__ */
+#define AT91_MCI_LOCK(_sc) \
+ rtems_interrupt_lock_context at91_mci_lock_context; \
+ rtems_interrupt_lock_acquire(&(_sc)->sc_lock, &at91_mci_lock_context)
+#define AT91_MCI_UNLOCK(_sc) \
+ rtems_interrupt_lock_release(&(_sc)->sc_lock, &at91_mci_lock_context)
+#define AT91_MCI_LOCK_INIT(_sc) \
+ rtems_interrupt_lock_initialize(&(_sc)->sc_lock, \
+ device_get_nameunit((_sc)->dev))
+#define AT91_MCI_LOCK_DESTROY(_sc) \
+ rtems_interrupt_lock_destroy(&(_sc)->sc_mtx)
+#define AT91_MCI_BUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
+#define AT91_MCI_BUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
+#define AT91_MCI_BUS_LOCK_INIT(_sc) \
+ mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->dev), \
+ "mci", MTX_DEF)
+#endif /* __rtems__ */
+
+static inline uint32_t
+RD4(struct at91_mci_softc *sc, bus_size_t off)
+{
+ return (bus_read_4(sc->mem_res, off));
+}
+
+static inline void
+WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
+{
+ bus_write_4(sc->mem_res, off, val);
+}
+
+#ifndef __rtems__
+static void
+at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
+{
+ uint32_t * dst = (uint32_t *)dptr;
+ uint32_t * src = (uint32_t *)sptr;
+ uint32_t i;
+
+ /*
+ * If the hardware doesn't need byte-swapping, let bcopy() do the
+ * work. Use bounce buffer even if we don't need byteswap, since
+ * buffer may straddle a page boundary, and we don't handle
+ * multi-segment transfers in hardware. Seen from 'bsdlabel -w' which
+ * uses raw geom access to the volume. Greg Ansley (gja (at)
+ * ansley.com)
+ */
+ if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
+ memcpy(dptr, sptr, memsize);
+ return;
+ }
+
+ /*
+ * Nice performance boost for slightly unrolling this loop.
+ * (But very little extra boost for further unrolling it.)
+ */
+ for (i = 0; i < memsize; i += 16) {
+ *dst++ = bswap32(*src++);
+ *dst++ = bswap32(*src++);
+ *dst++ = bswap32(*src++);
+ *dst++ = bswap32(*src++);
+ }
+
+ /* Mop up the last 1-3 words, if any. */
+ for (i = 0; i < (memsize & 0x0F); i += 4) {
+ *dst++ = bswap32(*src++);
+ }
+}
+
+static void
+at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+ if (error != 0)
+ return;
+ *(bus_addr_t *)arg = segs[0].ds_addr;
+}
+#endif /* __rtems__ */
+
+static void
+at91_mci_pdc_disable(struct at91_mci_softc *sc)
+{
+#ifndef __rtems__
+ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
+ WR4(sc, PDC_RPR, 0);
+ WR4(sc, PDC_RCR, 0);
+ WR4(sc, PDC_RNPR, 0);
+ WR4(sc, PDC_RNCR, 0);
+ WR4(sc, PDC_TPR, 0);
+ WR4(sc, PDC_TCR, 0);
+ WR4(sc, PDC_TNPR, 0);
+ WR4(sc, PDC_TNCR, 0);
+#else /* __rtems__ */
+ /* On SAMV71 there is no PDC but a DMAC */
+ XDMAD_StopTransfer(pXdmad, sc->xdma_rx_channel);
+ XDMAD_StopTransfer(pXdmad, sc->xdma_tx_channel);
+ WR4(sc, MCI_DMA, 0);
+#endif /* __rtems__ */
+}
+
+/*
+ * Reset the controller, then restore most of the current state.
+ *
+ * This is called after detecting an error. It's also called after stopping a
+ * multi-block write, to un-wedge the device so that it will handle the NOTBUSY
+ * signal correctly. See comments in at91_mci_stop_done() for more details.
+ */
+static void at91_mci_reset(struct at91_mci_softc *sc)
+{
+ uint32_t mr;
+ uint32_t sdcr;
+ uint32_t dtor;
+ uint32_t imr;
+
+ at91_mci_pdc_disable(sc);
+
+ /* save current state */
+
+ imr = RD4(sc, MCI_IMR);
+#ifndef __rtems__
+ mr = RD4(sc, MCI_MR) & 0x7fff;
+#else /* __rtems__ */
+ mr = RD4(sc, MCI_MR);
+#endif /* __rtems__ */
+ sdcr = RD4(sc, MCI_SDCR);
+ dtor = RD4(sc, MCI_DTOR);
+
+ /* reset the controller */
+
+ WR4(sc, MCI_IDR, 0xffffffff);
+ WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
+
+ /* restore state */
+
+ WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
+ WR4(sc, MCI_MR, mr);
+ WR4(sc, MCI_SDCR, sdcr);
+ WR4(sc, MCI_DTOR, dtor);
+ WR4(sc, MCI_IER, imr);
+
+ /*
+ * Make sure sdio interrupts will fire. Not sure why reading
+ * SR ensures that, but this is in the linux driver.
+ */
+
+ RD4(sc, MCI_SR);
+}
+
+static void
+at91_mci_init(device_t dev)
+{
+ struct at91_mci_softc *sc = device_get_softc(dev);
+ uint32_t val;
+
+ WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
+ WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
+ WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
+#ifndef __rtems__
+ val = MCI_MR_PDCMODE;
+#else /* __rtems__ */
+ val = 0;
+ val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
+#endif /* __rtems__ */
+ val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */
+// if (sc->sc_cap & CAP_MCI1_REV2XX)
+// val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
+ WR4(sc, MCI_MR, val);
+#ifndef AT91_MCI_SLOT_B
+ WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
+#else
+ /*
+ * XXX Really should add second "unit" but nobody using using
+ * a two slot card that we know of. XXX
+ */
+ WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */
+#endif
+ /*
+ * Enable controller, including power-save. The slower clock
+ * of the power-save mode is only in effect when there is no
+ * transfer in progress, so it can be left in this mode all
+ * the time.
+ */
+ WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
+}
+
+static void
+at91_mci_fini(device_t dev)
+{
+ struct at91_mci_softc *sc = device_get_softc(dev);
+
+ WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
+ at91_mci_pdc_disable(sc);
+ WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
+}
+
+static int
+at91_mci_probe(device_t dev)
+{
+#ifdef FDT
+ if (!ofw_bus_is_compatible(dev, "atmel,hsmci"))
+ return (ENXIO);
+#endif
+ device_set_desc(dev, "MCI mmc/sd host bridge");
+ return (0);
+}
+
+static int
+at91_mci_attach(device_t dev)
+{
+ struct at91_mci_softc *sc = device_get_softc(dev);
+ struct sysctl_ctx_list *sctx;
+ struct sysctl_oid *soid;
+ device_t child;
+#ifndef __rtems__
+ int err, i;
+#else /* __rtems__ */
+ int err;
+#endif /* __rtems__ */
+
+#ifdef __rtems__
+#ifdef LIBBSP_ARM_ATSAM_BSP_H
+ PMC_EnablePeripheral(ID_HSMCI);
+ sc->xdma_tx_channel = XDMAD_ALLOC_FAILED;
+ sc->xdma_rx_channel = XDMAD_ALLOC_FAILED;
+#endif /* LIBBSP_ARM_ATSAM_BSP_H */
+#endif /* __rtems__ */
+ sctx = device_get_sysctl_ctx(dev);
+ soid = device_get_sysctl_tree(dev);
+
+ sc->dev = dev;
+ sc->sc_cap = 0;
+#ifndef __rtems__
+ if (at91_is_rm92())
+ sc->sc_cap |= CAP_NEEDS_BYTESWAP;
+#endif /* __rtems__ */
+ /*
+ * MCI1 Rev 2 controllers need some workarounds, flag if so.
+ */
+ if (at91_mci_is_mci1rev2xx())
+ sc->sc_cap |= CAP_MCI1_REV2XX;
+
+ err = at91_mci_activate(dev);
+ if (err)
+ goto out;
+
+#ifdef __rtems__
+ eXdmadRC rc;
+
+ /* Prepare some configurations so they don't have to be fetched on every
+ * setup */
+ sc->xdma_rx_perid = XDMAIF_Get_ChannelNumber(ID_HSMCI,
+ XDMAD_TRANSFER_RX);
+ sc->xdma_tx_perid = XDMAIF_Get_ChannelNumber(ID_HSMCI,
+ XDMAD_TRANSFER_TX);
+ memset(&sc->xdma_rx_cfg, 0, sizeof(sc->xdma_rx_cfg));
+ sc->xdma_rx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
+ XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_PER2MEM |
+ XDMAC_CC_SWREQ_HWR_CONNECTED | XDMAC_CC_MEMSET_NORMAL_MODE |
+ XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD |
+ XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 |
+ XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_INCREMENTED_AM |
+ XDMAC_CC_PERID(
+ XDMAIF_Get_ChannelNumber(ID_HSMCI,XDMAD_TRANSFER_RX));
+ memset(&sc->xdma_tx_cfg, 0, sizeof(sc->xdma_tx_cfg));
+ sc->xdma_tx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
+ XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER |
+ XDMAC_CC_SWREQ_HWR_CONNECTED | XDMAC_CC_MEMSET_NORMAL_MODE |
+ XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD |
+ XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 |
+ XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM |
+ XDMAC_CC_PERID(
+ XDMAIF_Get_ChannelNumber(ID_HSMCI,XDMAD_TRANSFER_TX));
+
+ sc->xdma_tx_channel = XDMAD_AllocateChannel(pXdmad,
+ XDMAD_TRANSFER_MEMORY, ID_HSMCI);
+ if (sc->xdma_tx_channel == XDMAD_ALLOC_FAILED)
+ goto out;
+
+ /* FIXME: The two DMA channels are not really necessary for the driver.
+ * But the XDMAD interface does not allow to allocate one and use it
+ * into two directions. The current (2017-07-11) implementation of
+ * the XDMAD interface should work with it. So we might could try it. */
+ sc->xdma_rx_channel = XDMAD_AllocateChannel(pXdmad, ID_HSMCI,
+ XDMAD_TRANSFER_MEMORY);
+ if (sc->xdma_rx_channel == XDMAD_ALLOC_FAILED)
+ goto out;
+
+ rc = XDMAD_PrepareChannel(pXdmad, sc->xdma_rx_channel);
+ if (rc != XDMAD_OK)
+ goto out;
+
+ rc = XDMAD_PrepareChannel(pXdmad, sc->xdma_tx_channel);
+ if (rc != XDMAD_OK)
+ goto out;
+
+ AT91_MCI_BUS_LOCK_INIT(sc);
+#endif /* __rtems__ */
+ AT91_MCI_LOCK_INIT(sc);
+
+ at91_mci_fini(dev);
+ at91_mci_init(dev);
+
+#ifndef __rtems__
+ /*
+ * Allocate DMA tags and maps and bounce buffers.
+ *
+ * The parms in the tag_create call cause the dmamem_alloc call to
+ * create each bounce buffer as a single contiguous buffer of BBSIZE
+ * bytes aligned to a 4096 byte boundary.
+ *
+ * Do not use DMA_COHERENT for these buffers because that maps the
+ * memory as non-cachable, which prevents cache line burst fills/writes,
+ * which is something we need since we're trying to overlap the
+ * byte-swapping with the DMA operations.
+ */
+ err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
+ BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
+ BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
+ if (err != 0)
+ goto out;
+
+ for (i = 0; i < BBCOUNT; ++i) {
+ err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
+ BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
+ if (err != 0)
+ goto out;
+ }
+
+ /*
+ * Activate the interrupt
+ */
+ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, at91_mci_intr, sc, &sc->intrhand);
+#else /* __rtems__ */
+ err = rtems_interrupt_handler_install(rman_get_start(sc->irq_res),
+ device_get_nameunit(dev), RTEMS_INTERRUPT_SHARED, at91_mci_intr,
+ sc);
+#endif /* __rtems__ */
+ if (err) {
+ AT91_MCI_LOCK_DESTROY(sc);
+ goto out;
+ }
+
+ /*
+ * Allow 4-wire to be initially set via #define.
+ * Allow a device hint to override that.
+ * Allow a sysctl to override that.
+ */
+#if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
+ sc->has_4wire = 1;
+#endif
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "4wire", &sc->has_4wire);
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
+ CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
+ if (sc->has_4wire)
+ sc->sc_cap |= CAP_HAS_4WIRE;
+
+ sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "allow_overclock", &sc->allow_overclock);
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
+ CTLFLAG_RW, &sc->allow_overclock, 0,
+ "Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
+
+#ifndef __rtems__
+ SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
+ CTLFLAG_RWTUN, &mci_debug, 0, "enable debug output");
+#endif /* __rtems__ */
+
+ /*
+ * Our real min freq is master_clock/512, but upper driver layers are
+ * going to set the min speed during card discovery, and the right speed
+ * for that is 400kHz, so advertise a safe value just under that.
+ *
+ * For max speed, while the rm9200 manual says the max is 50mhz, it also
+ * says it supports only the SD v1.0 spec, which means the real limit is
+ * 25mhz. On the other hand, historical use has been to slightly violate
+ * the standard by running the bus at 30MHz. For more information on
+ * that, see the comments at the top of this file.
+ */
+ sc->host.f_min = 375000;
+ sc->host.f_max = at91_master_clock / 2;
+ if (sc->host.f_max > 25000000)
+ sc->host.f_max = 25000000;
+ sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
+ sc->host.caps = 0;
+ if (sc->sc_cap & CAP_HAS_4WIRE)
+ sc->host.caps |= MMC_CAP_4_BIT_DATA;
+
+ child = device_add_child(dev, "mmc", 0);
+#ifdef __rtems__
+ (void)child;
+#endif /* __rtems__ */
+ device_set_ivars(dev, &sc->host);
+ err = bus_generic_attach(dev);
+out:
+ if (err)
+ at91_mci_deactivate(dev);
+ return (err);
+}
+
+static int
+at91_mci_detach(device_t dev)
+{
+#ifndef __rtems__
+ struct at91_mci_softc *sc = device_get_softc(dev);
+#endif /* __rtems__ */
+
+ at91_mci_fini(dev);
+ at91_mci_deactivate(dev);
+
+#ifndef __rtems__
+ bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
+ bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
+ bus_dma_tag_destroy(sc->dmatag);
+#endif /* __rtems__ */
+
+ return (EBUSY); /* XXX */
+}
+
+static int
+at91_mci_activate(device_t dev)
+{
+ struct at91_mci_softc *sc;
+ int rid;
+
+ sc = device_get_softc(dev);
+ rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->mem_res == NULL)
+ goto errout;
+
+ rid = 0;
+ sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->irq_res == NULL)
+ goto errout;
+
+ return (0);
+errout:
+ at91_mci_deactivate(dev);
+ return (ENOMEM);
+}
+
+static void
+at91_mci_deactivate(device_t dev)
+{
+ struct at91_mci_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (sc->intrhand)
+ bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
+ sc->intrhand = NULL;
+ bus_generic_detach(sc->dev);
+ if (sc->mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY,
+ rman_get_rid(sc->mem_res), sc->mem_res);
+ sc->mem_res = NULL;
+ if (sc->irq_res)
+ bus_release_resource(dev, SYS_RES_IRQ,
+ rman_get_rid(sc->irq_res), sc->irq_res);
+ sc->irq_res = NULL;
+#ifdef __rtems__
+ if (sc->xdma_rx_channel != XDMAD_ALLOC_FAILED) {
+ XDMAD_FreeChannel(pXdmad, sc->xdma_rx_channel);
+ }
+ if (sc->xdma_tx_channel != XDMAD_ALLOC_FAILED) {
+ XDMAD_FreeChannel(pXdmad, sc->xdma_tx_channel);
+ }
+#endif /* __rtems__ */
+ return;
+}
+
+static int
+at91_mci_is_mci1rev2xx(void)
+{
+
+#ifndef __rtems__
+ switch (soc_info.type) {
+ case AT91_T_SAM9260:
+ case AT91_T_SAM9263:
+ case AT91_T_CAP9:
+ case AT91_T_SAM9G10:
+ case AT91_T_SAM9G20:
+ case AT91_T_SAM9RL:
+ return(1);
+ default:
+ return (0);
+ }
+#else /* __rtems__ */
+ /* Currently only supports the SAM V71 */
+ return (1);
+#endif /* __rtems__ */
+}
+
+static int
+at91_mci_update_ios(device_t brdev, device_t reqdev)
+{
+ struct at91_mci_softc *sc;
+ struct mmc_ios *ios;
+ uint32_t clkdiv;
+ uint32_t freq;
+
+ sc = device_get_softc(brdev);
+ ios = &sc->host.ios;
+
+ /*
+ * Calculate our closest available clock speed that doesn't exceed the
+ * requested speed.
+ *
+ * When overclocking is allowed, the requested clock is 25MHz, the
+ * computed frequency is 15MHz or smaller and clockdiv is 1, use
+ * clockdiv of 0 to double that. If less than 12.5MHz, double
+ * regardless of the overclocking setting.
+ *
+ * Whatever we come up with, store it back into ios->clock so that the
+ * upper layer drivers can report the actual speed of the bus.
+ */
+ if (ios->clock == 0) {
+ WR4(sc, MCI_CR, MCI_CR_MCIDIS);
+ clkdiv = 0;
+ } else {
+ WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
+ if ((at91_master_clock % (ios->clock * 2)) == 0)
+ clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
+ else
+ clkdiv = (at91_master_clock / ios->clock) / 2;
+ freq = at91_master_clock / ((clkdiv+1) * 2);
+ if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
+ if (sc->allow_overclock || freq <= 12500000) {
+ clkdiv = 0;
+ freq = at91_master_clock / ((clkdiv+1) * 2);
+ }
+ }
+ ios->clock = freq;
+ }
+ if (ios->bus_width == bus_width_4)
+ WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
+ else
+ WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
+ WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
+ /* Do we need a settle time here? */
+ /* XXX We need to turn the device on/off here with a GPIO pin */
+ return (0);
+}
+
+#ifdef __rtems__
+static void
+at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, void *data,
+ uint32_t len)
+{
+ const uint32_t xdma_cndc = XDMAC_CNDC_NDVIEW_NDV1 |
+ XDMAC_CNDC_NDE_DSCR_FETCH_EN |
+ XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |
+ XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED;
+ const uint32_t xdma_interrupt = XDMAC_CIE_BIE | XDMAC_CIE_DIE |
+ XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE;
+ sXdmadCfg *xdma_cfg;
+ uint32_t xdma_channel;
+ eXdmadRC rc;
+
+ if (len % 4 != 0)
+ panic("invalid XDMA transfer length");
+
+ if (read) {
+ xdma_cfg = &sc->xdma_rx_cfg;
+ xdma_channel = sc->xdma_rx_channel;
+ sc->xdma_desc.mbr_sa = (uint32_t)(sc->mem_res->r_bushandle +
+ MCI_RDR);
+ sc->xdma_desc.mbr_da = (uint32_t)data;
+ rtems_cache_invalidate_multiple_data_lines(data, len);
+ } else {
+ xdma_cfg = &sc->xdma_tx_cfg;
+ xdma_channel = sc->xdma_tx_channel;
+ sc->xdma_desc.mbr_sa = (uint32_t)data;
+ sc->xdma_desc.mbr_da = (uint32_t)(sc->mem_res->r_bushandle +
+ MCI_TDR);
+ rtems_cache_flush_multiple_data_lines(data, len);
+ }
+
+ sc->xdma_desc.mbr_ubc = XDMA_UBC_NVIEW_NDV1 |
+ XDMA_UBC_NDEN_UPDATED | (len / 4);
+ sc->xdma_desc.mbr_ubc |= XDMA_UBC_NDE_FETCH_DIS;
+ sc->xdma_desc.mbr_nda = 0;
+
+ rc = XDMAD_ConfigureTransfer(pXdmad, xdma_channel, xdma_cfg, xdma_cndc,
+ (uint32_t)&sc->xdma_desc, xdma_interrupt);
+ if (rc != XDMAD_OK)
+ panic("configure XDMA failed: %d", rc);
+
+ rtems_cache_flush_multiple_data_lines(&sc->xdma_desc, sizeof(sc->xdma_desc));
+
+ rc = XDMAD_StartTransfer(pXdmad, xdma_channel);
+ if (rc != XDMAD_OK)
+ panic("start XDMA failed: %d", rc);
+}
+#endif /* __rtems__ */
+static void
+at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
+{
+ uint32_t cmdr, mr;
+ struct mmc_data *data;
+#ifdef __rtems__
+ uint32_t block_count;
+ uint32_t block_size;
+#endif /* __rtems__ */
+
+ sc->curcmd = cmd;
+ data = cmd->data;
+
+ /* XXX Upper layers don't always set this */
+ cmd->mrq = sc->req;
+
+ /* Begin setting up command register. */
+
+ cmdr = cmd->opcode;
+
+ if (sc->host.ios.bus_mode == opendrain)
+ cmdr |= MCI_CMDR_OPDCMD;
+
+ /* Set up response handling. Allow max timeout for responses. */
+
+ if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
+ cmdr |= MCI_CMDR_RSPTYP_NO;
+ else {
+ cmdr |= MCI_CMDR_MAXLAT;
+ if (cmd->flags & MMC_RSP_136)
+ cmdr |= MCI_CMDR_RSPTYP_136;
+ else
+ cmdr |= MCI_CMDR_RSPTYP_48;
+ }
+
+ /*
+ * If there is no data transfer, just set up the right interrupt mask
+ * and start the command.
+ *
+ * The interrupt mask needs to be CMDRDY plus all non-data-transfer
+ * errors. It's important to leave the transfer-related errors out, to
+ * avoid spurious timeout or crc errors on a STOP command following a
+ * multiblock read. When a multiblock read is in progress, sending a
+ * STOP in the middle of a block occasionally triggers such errors, but
+ * we're totally disinterested in them because we've already gotten all
+ * the data we wanted without error before sending the STOP command.
+ */
+
+ if (data == NULL) {
+ uint32_t ier = MCI_SR_CMDRDY |
+ MCI_SR_RTOE | MCI_SR_RENDE |
+ MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE;
+
+ at91_mci_pdc_disable(sc);
+
+ if (cmd->opcode == MMC_STOP_TRANSMISSION)
+ cmdr |= MCI_CMDR_TRCMD_STOP;
+
+ /* Ignore response CRC on CMD2 and ACMD41, per standard. */
+
+ if (cmd->opcode == MMC_SEND_OP_COND ||
+ cmd->opcode == ACMD_SD_SEND_OP_COND)
+ ier &= ~MCI_SR_RCRCE;
+
+ if (mci_debug)
+ printf("CMDR %x (opcode %d) ARGR %x no data\n",
+ cmdr, cmd->opcode, cmd->arg);
+
+ WR4(sc, MCI_ARGR, cmd->arg);
+ WR4(sc, MCI_CMDR, cmdr);
+ WR4(sc, MCI_IDR, 0xffffffff);
+ WR4(sc, MCI_IER, ier);
+ return;
+ }
+
+ /* There is data, set up the transfer-related parts of the command. */
+
+ if (data->flags & MMC_DATA_READ)
+ cmdr |= MCI_CMDR_TRDIR;
+
+ if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
+ cmdr |= MCI_CMDR_TRCMD_START;
+
+ if (data->flags & MMC_DATA_STREAM)
+ cmdr |= MCI_CMDR_TRTYP_STREAM;
+ else if (data->flags & MMC_DATA_MULTI) {
+ cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
+ sc->flags |= (data->flags & MMC_DATA_READ) ?
+ CMD_MULTIREAD : CMD_MULTIWRITE;
+ }
+
+ /*
+ * Disable PDC until we're ready.
+ *
+ * Set block size and turn on PDC mode for dma xfer.
+ * Note that the block size is the smaller of the amount of data to be
+ * transferred, or 512 bytes. The 512 size is fixed by the standard;
+ * smaller blocks are possible, but never larger.
+ */
+
+#ifndef __rtems__
+ WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
+
+ mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
+ mr |= min(data->len, 512) << 16;
+ WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
+
+ /*
+ * Set up DMA.
+ *
+ * Use bounce buffers even if we don't need to byteswap, because doing
+ * multi-block IO with large DMA buffers is way fast (compared to
+ * single-block IO), even after incurring the overhead of also copying
+ * from/to the caller's buffers (which may be in non-contiguous physical
+ * pages).
+ *
+ * In an ideal non-byteswap world we could create a dma tag that allows
+ * for discontiguous segments and do the IO directly from/to the
+ * caller's buffer(s), using ENDRX/ENDTX interrupts to chain the
+ * discontiguous buffers through the PDC. Someday.
+ *
+ * If a read is bigger than 2k, split it in half so that we can start
+ * byte-swapping the first half while the second half is on the wire.
+ * It would be best if we could split it into 8k chunks, but we can't
+ * always keep up with the byte-swapping due to other system activity,
+ * and if an RXBUFF interrupt happens while we're still handling the
+ * byte-swap from the prior buffer (IE, we haven't returned from
+ * handling the prior interrupt yet), then data will get dropped on the
+ * floor and we can't easily recover from that. The right fix for that
+ * would be to have the interrupt handling only keep the DMA flowing and
+ * enqueue filled buffers to be byte-swapped in a non-interrupt context.
+ * Even that won't work on the write side of things though; in that
+ * context we have to have all the data ready to go before starting the
+ * dma.
+ *
+ * XXX what about stream transfers?
+ */
+ sc->xfer_offset = 0;
+ sc->bbuf_curidx = 0;
+#else /* __rtems__ */
+ mr = RD4(sc,MCI_MR);
+ WR4(sc, MCI_MR, mr | MCI_MR_PDCPADV);
+
+ WR4(sc, MCI_DMA, MCI_DMA_DMAEN | MCI_DMA_CHKSIZE_1);
+
+ block_size = min(data->len, 512);
+ block_count = data->len / block_size;
+ WR4(sc, MCI_BLKR, (block_size << 16) | block_count);
+#endif /* __rtems__ */
+
+ if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
+#ifndef __rtems__
+ uint32_t len;
+ uint32_t remaining = data->len;
+ bus_addr_t paddr;
+ int err;
+
+ if (remaining > (BBCOUNT*BBSIZE))
+ panic("IO read size exceeds MAXDATA\n");
+#endif /* __rtems__ */
+
+ if (data->flags & MMC_DATA_READ) {
+#ifndef __rtems__
+ if (remaining > 2048) // XXX
+ len = remaining / 2;
+ else
+ len = remaining;
+ err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
+ sc->bbuf_vaddr[0], len, at91_mci_getaddr,
+ &paddr, BUS_DMA_NOWAIT);
+ if (err != 0)
+ panic("IO read dmamap_load failed\n");
+ bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
+ BUS_DMASYNC_PREREAD);
+ WR4(sc, PDC_RPR, paddr);
+ WR4(sc, PDC_RCR, len / 4);
+ sc->bbuf_len[0] = len;
+ remaining -= len;
+ if (remaining == 0) {
+ sc->bbuf_len[1] = 0;
+ } else {
+ len = remaining;
+ err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
+ sc->bbuf_vaddr[1], len, at91_mci_getaddr,
+ &paddr, BUS_DMA_NOWAIT);
+ if (err != 0)
+ panic("IO read dmamap_load failed\n");
+ bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
+ BUS_DMASYNC_PREREAD);
+ WR4(sc, PDC_RNPR, paddr);
+ WR4(sc, PDC_RNCR, len / 4);
+ sc->bbuf_len[1] = len;
+ remaining -= len;
+ }
+ WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
+#else /* __rtems__ */
+ at91_mci_setup_xdma(sc, true, data->data, data->len);
+#endif /* __rtems__ */
+ } else {
+#ifndef __rtems__
+ len = min(BBSIZE, remaining);
+ at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
+ err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
+ sc->bbuf_vaddr[0], len, at91_mci_getaddr,
+ &paddr, BUS_DMA_NOWAIT);
+ if (err != 0)
+ panic("IO write dmamap_load failed\n");
+ bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
+ BUS_DMASYNC_PREWRITE);
+ /*
+ * Erratum workaround: PDC transfer length on a write
+ * must not be smaller than 12 bytes (3 words); only
+ * blklen bytes (set above) are actually transferred.
+ */
+ WR4(sc, PDC_TPR,paddr);
+ WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4);
+ sc->bbuf_len[0] = len;
+ remaining -= len;
+ if (remaining == 0) {
+ sc->bbuf_len[1] = 0;
+ } else {
+ len = remaining;
+ at91_bswap_buf(sc, sc->bbuf_vaddr[1],
+ ((char *)data->data)+BBSIZE, len);
+ err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
+ sc->bbuf_vaddr[1], len, at91_mci_getaddr,
+ &paddr, BUS_DMA_NOWAIT);
+ if (err != 0)
+ panic("IO write dmamap_load failed\n");
+ bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
+ BUS_DMASYNC_PREWRITE);
+ WR4(sc, PDC_TNPR, paddr);
+ WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4);
+ sc->bbuf_len[1] = len;
+ remaining -= len;
+ }
+ /* do not enable PDC xfer until CMDRDY asserted */
+#else /* __rtems__ */
+ at91_mci_setup_xdma(sc, false, data->data, data->len);
+#endif /* __rtems__ */
+ }
+ data->xfer_len = 0; /* XXX what's this? appears to be unused. */
+ }
+
+ if (mci_debug)
+ printf("CMDR %x (opcode %d) ARGR %x with data len %d\n",
+ cmdr, cmd->opcode, cmd->arg, cmd->data->len);
+
+ WR4(sc, MCI_ARGR, cmd->arg);
+ WR4(sc, MCI_CMDR, cmdr);
+ WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
+}
+
+static void
+at91_mci_next_operation(struct at91_mci_softc *sc)
+{
+ struct mmc_request *req;
+
+ req = sc->req;
+ if (req == NULL)
+ return;
+
+ if (sc->flags & PENDING_CMD) {
+ sc->flags &= ~PENDING_CMD;
+ at91_mci_start_cmd(sc, req->cmd);
+ return;
+ } else if (sc->flags & PENDING_STOP) {
+ sc->flags &= ~PENDING_STOP;
+ at91_mci_start_cmd(sc, req->stop);
+ return;
+ }
+
+ WR4(sc, MCI_IDR, 0xffffffff);
+ sc->req = NULL;
+ sc->curcmd = NULL;
+ //printf("req done\n");
+ req->done(req);
+}
+
+static int
+at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
+{
+ struct at91_mci_softc *sc = device_get_softc(brdev);
+
+ AT91_MCI_LOCK(sc);
+ if (sc->req != NULL) {
+ AT91_MCI_UNLOCK(sc);
+ return (EBUSY);
+ }
+ //printf("new req\n");
+ sc->req = req;
+ sc->flags = PENDING_CMD;
+ if (sc->req->stop)
+ sc->flags |= PENDING_STOP;
+ at91_mci_next_operation(sc);
+ AT91_MCI_UNLOCK(sc);
+ return (0);
+}
+
+static int
+at91_mci_get_ro(device_t brdev, device_t reqdev)
+{
+ return (0);
+}
+
+static int
+at91_mci_acquire_host(device_t brdev, device_t reqdev)
+{
+ struct at91_mci_softc *sc = device_get_softc(brdev);
+ int err = 0;
+
+#ifndef __rtems__
+ AT91_MCI_LOCK(sc);
+#else /* __rtems__ */
+ AT91_MCI_BUS_LOCK(sc);
+#endif /* __rtems__ */
+ while (sc->bus_busy)
+ msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
+ sc->bus_busy++;
+#ifndef __rtems__
+ AT91_MCI_UNLOCK(sc);
+#else /* __rtems__ */
+ AT91_MCI_BUS_UNLOCK(sc);
+#endif /* __rtems__ */
+ return (err);
+}
+
+static int
+at91_mci_release_host(device_t brdev, device_t reqdev)
+{
+ struct at91_mci_softc *sc = device_get_softc(brdev);
+
+#ifndef __rtems__
+ AT91_MCI_LOCK(sc);
+#else /* __rtems__ */
+ AT91_MCI_BUS_LOCK(sc);
+#endif /* __rtems__ */
+ sc->bus_busy--;
+ wakeup(sc);
+#ifndef __rtems__
+ AT91_MCI_UNLOCK(sc);
+#else /* __rtems__ */
+ AT91_MCI_BUS_UNLOCK(sc);
+#endif /* __rtems__ */
+ return (0);
+}
+
+#ifndef __rtems__
+static void
+at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
+{
+ struct mmc_command *cmd = sc->curcmd;
+ char * dataptr = (char *)cmd->data->data;
+ uint32_t curidx = sc->bbuf_curidx;
+ uint32_t len = sc->bbuf_len[curidx];
+
+ /*
+ * We arrive here when a DMA transfer for a read is done, whether it's
+ * a single or multi-block read.
+ *
+ * We byte-swap the buffer that just completed, and if that is the
+ * last buffer that's part of this read then we move on to the next
+ * operation, otherwise we wait for another ENDRX for the next bufer.
+ */
+
+ bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
+
+ at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
+
+ if (mci_debug) {
+ printf("read done sr %x curidx %d len %d xfer_offset %d\n",
+ sr, curidx, len, sc->xfer_offset);
+ }
+
+ sc->xfer_offset += len;
+ sc->bbuf_curidx = !curidx; /* swap buffers */
+
+ /*
+ * If we've transferred all the data, move on to the next operation.
+ *
+ * If we're still transferring the last buffer, RNCR is already zero but
+ * we have to write a zero anyway to clear the ENDRX status so we don't
+ * re-interrupt until the last buffer is done.
+ */
+ if (sc->xfer_offset == cmd->data->len) {
+ WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
+ cmd->error = MMC_ERR_NONE;
+ at91_mci_next_operation(sc);
+ } else {
+ WR4(sc, PDC_RNCR, 0);
+ WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
+ }
+}
+#endif /* __rtems__ */
+
+static void
+at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
+{
+ struct mmc_command *cmd = sc->curcmd;
+
+ /*
+ * We arrive here when the entire DMA transfer for a write is done,
+ * whether it's a single or multi-block write. If it's multi-block we
+ * have to immediately move on to the next operation which is to send
+ * the stop command. If it's a single-block transfer we need to wait
+ * for NOTBUSY, but if that's already asserted we can avoid another
+ * interrupt and just move on to completing the request right away.
+ */
+
+ WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
+
+#ifndef __rtems__
+ bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
+#endif /* __rtems__ */
+
+ if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
+ cmd->error = MMC_ERR_NONE;
+ at91_mci_next_operation(sc);
+ } else {
+ WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
+ }
+}
+
+static void
+at91_mci_notbusy(struct at91_mci_softc *sc)
+{
+ struct mmc_command *cmd = sc->curcmd;
+
+ /*
+ * We arrive here by either completion of a single-block write, or
+ * completion of the stop command that ended a multi-block write (and,
+ * I suppose, after a card-select or erase, but I haven't tested
+ * those). Anyway, we're done and it's time to move on to the next
+ * command.
+ */
+
+ cmd->error = MMC_ERR_NONE;
+ at91_mci_next_operation(sc);
+}
+
+static void
+at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr)
+{
+ struct mmc_command *cmd = sc->curcmd;
+
+ /*
+ * We arrive here after receiving CMDRDY for a MMC_STOP_TRANSMISSION
+ * command. Depending on the operation being stopped, we may have to
+ * do some unusual things to work around hardware bugs.
+ */
+
+ /*
+ * This is known to be true of at91rm9200 hardware; it may or may not
+ * apply to more recent chips:
+ *
+ * After stopping a multi-block write, the NOTBUSY bit in MCI_SR does
+ * not properly reflect the actual busy state of the card as signaled
+ * on the DAT0 line; it always claims the card is not-busy. If we
+ * believe that and let operations continue, following commands will
+ * fail with response timeouts (except of course MMC_SEND_STATUS -- it
+ * indicates the card is busy in the PRG state, which was the smoking
+ * gun that showed MCI_SR NOTBUSY was not tracking DAT0 correctly).
+ *
+ * The atmel docs are emphatic: "This flag [NOTBUSY] must be used only
+ * for Write Operations." I guess technically since we sent a stop
+ * it's not a write operation anymore. But then just what did they
+ * think it meant for the stop command to have "...an optional busy
+ * signal transmitted on the data line" according to the SD spec?
+ *
+ * I tried a variety of things to un-wedge the MCI and get the status
+ * register to reflect NOTBUSY correctly again, but the only thing
+ * that worked was a full device reset. It feels like an awfully big
+ * hammer, but doing a full reset after every multiblock write is
+ * still faster than doing single-block IO (by almost two orders of
+ * magnitude: 20KB/sec improves to about 1.8MB/sec best case).
+ *
+ * After doing the reset, wait for a NOTBUSY interrupt before
+ * continuing with the next operation.
+ *
+ * This workaround breaks multiwrite on the rev2xx parts, but some other
+ * workaround is needed.
+ */
+ if ((sc->flags & CMD_MULTIWRITE) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
+ at91_mci_reset(sc);
+ WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
+ return;
+ }
+
+ /*
+ * This is known to be true of at91rm9200 hardware; it may or may not
+ * apply to more recent chips:
+ *
+ * After stopping a multi-block read, loop to read and discard any
+ * data that coasts in after we sent the stop command. The docs don't
+ * say anything about it, but empirical testing shows that 1-3
+ * additional words of data get buffered up in some unmentioned
+ * internal fifo and if we don't read and discard them here they end
+ * up on the front of the next read DMA transfer we do.
+ *
+ * This appears to be unnecessary for rev2xx parts.
+ */
+ if ((sc->flags & CMD_MULTIREAD) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
+ uint32_t sr;
+ int count = 0;
+
+ do {
+ sr = RD4(sc, MCI_SR);
+ if (sr & MCI_SR_RXRDY) {
+ RD4(sc, MCI_RDR);
+ ++count;
+ }
+ } while (sr & MCI_SR_RXRDY);
+ at91_mci_reset(sc);
+ }
+
+ cmd->error = MMC_ERR_NONE;
+ at91_mci_next_operation(sc);
+
+}
+
+static void
+at91_mci_cmdrdy(struct at91_mci_softc *sc, uint32_t sr)
+{
+ struct mmc_command *cmd = sc->curcmd;
+ int i;
+
+ if (cmd == NULL)
+ return;
+
+ /*
+ * We get here at the end of EVERY command. We retrieve the command
+ * response (if any) then decide what to do next based on the command.
+ */
+
+ if (cmd->flags & MMC_RSP_PRESENT) {
+ for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); i++) {
+ cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
+ if (mci_debug)
+ printf("RSPR[%d] = %x sr=%x\n", i, cmd->resp[i], sr);
+ }
+ }
+
+ /*
+ * If this was a stop command, go handle the various special
+ * conditions (read: bugs) that have to be dealt with following a stop.
+ */
+ if (cmd->opcode == MMC_STOP_TRANSMISSION) {
+ at91_mci_stop_done(sc, sr);
+ return;
+ }
+
+ /*
+ * If this command can continue to assert BUSY beyond the response then
+ * we need to wait for NOTBUSY before the command is really done.
+ *
+ * Note that this may not work properly on the at91rm9200. It certainly
+ * doesn't work for the STOP command that follows a multi-block write,
+ * so post-stop CMDRDY is handled separately; see the special handling
+ * in at91_mci_stop_done().
+ *
+ * Beside STOP, there are other R1B-type commands that use the busy
+ * signal after CMDRDY: CMD7 (card select), CMD28-29 (write protect),
+ * CMD38 (erase). I haven't tested any of them, but I rather expect
+ * them all to have the same sort of problem with MCI_SR not actually
+ * reflecting the state of the DAT0-line busy indicator. So this code
+ * may need to grow some sort of special handling for them too. (This
+ * just in: CMD7 isn't a problem right now because dev/mmc.c incorrectly
+ * sets the response flags to R1 rather than R1B.) XXX
+ */
+ if ((cmd->flags & MMC_RSP_BUSY)) {
+ WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
+ return;
+ }
+
+ /*
+ * If there is a data transfer with this command, then...
+ * - If it's a read, we need to wait for ENDRX.
+ * - If it's a write, now is the time to enable the PDC, and we need
+ * to wait for a BLKE that follows a TXBUFE, because if we're doing
+ * a split transfer we get a BLKE after the first half (when TPR/TCR
+ * get loaded from TNPR/TNCR). So first we wait for the TXBUFE, and
+ * the handling for that interrupt will then invoke the wait for the
+ * subsequent BLKE which indicates actual completion.
+ */
+ if (cmd->data) {
+ uint32_t ier;
+#ifndef __rtems__
+ if (cmd->data->flags & MMC_DATA_READ) {
+ ier = MCI_SR_ENDRX;
+ } else {
+ ier = MCI_SR_TXBUFE;
+ WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
+ }
+#else /* __rtems__ */
+ ier = MCI_SR_XFRDONE;
+#endif /* __rtems__ */
+ WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
+ return;
+ }
+
+ /*
+ * If we made it to here, we don't need to wait for anything more for
+ * the current command, move on to the next command (will complete the
+ * request if there is no next command).
+ */
+ cmd->error = MMC_ERR_NONE;
+ at91_mci_next_operation(sc);
+}
+
+static void
+at91_mci_intr(void *arg)
+{
+ struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
+ struct mmc_command *cmd = sc->curcmd;
+ uint32_t sr, isr;
+
+ AT91_MCI_LOCK(sc);
+
+ sr = RD4(sc, MCI_SR);
+ isr = sr & RD4(sc, MCI_IMR);
+
+ if (mci_debug)
+ printf("i 0x%x sr 0x%x\n", isr, sr);
+
+ /*
+ * All interrupts are one-shot; disable it now.
+ * The next operation will re-enable whatever interrupts it wants.
+ */
+ WR4(sc, MCI_IDR, isr);
+ if (isr & MCI_SR_ERROR) {
+ if (isr & (MCI_SR_RTOE | MCI_SR_DTOE))
+ cmd->error = MMC_ERR_TIMEOUT;
+ else if (isr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
+ cmd->error = MMC_ERR_BADCRC;
+ else if (isr & (MCI_SR_OVRE | MCI_SR_UNRE))
+ cmd->error = MMC_ERR_FIFO;
+ else
+ cmd->error = MMC_ERR_FAILED;
+ /*
+ * CMD8 is used to probe for SDHC cards, a standard SD card
+ * will get a response timeout; don't report it because it's a
+ * normal and expected condition. One might argue that all
+ * error reporting should be left to higher levels, but when
+ * they report at all it's always EIO, which isn't very
+ * helpful. XXX bootverbose?
+ */
+ if (cmd->opcode != 8) {
+ device_printf(sc->dev,
+ "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n",
+ sr, MCI_SR_BITSTRING, cmd->opcode,
+ (cmd->opcode != 12) ? "" :
+ (sc->flags & CMD_MULTIREAD) ? " after read" : " after write");
+ /* XXX not sure RTOE needs a full reset, just a retry */
+ at91_mci_reset(sc);
+ }
+ at91_mci_next_operation(sc);
+ } else {
+#ifndef __rtems__
+ if (isr & MCI_SR_TXBUFE) {
+// printf("TXBUFE\n");
+ /*
+ * We need to wait for a BLKE that follows TXBUFE
+ * (intermediate BLKEs might happen after ENDTXes if
+ * we're chaining multiple buffers). If BLKE is also
+ * asserted at the time we get TXBUFE, we can avoid
+ * another interrupt and process it right away, below.
+ */
+ if (sr & MCI_SR_BLKE)
+ isr |= MCI_SR_BLKE;
+ else
+ WR4(sc, MCI_IER, MCI_SR_BLKE);
+ }
+ if (isr & MCI_SR_RXBUFF) {
+// printf("RXBUFF\n");
+ }
+ if (isr & MCI_SR_ENDTX) {
+// printf("ENDTX\n");
+ }
+ if (isr & MCI_SR_ENDRX) {
+// printf("ENDRX\n");
+ at91_mci_read_done(sc, sr);
+ }
+#else /* __rtems__ */
+ if (isr & MCI_SR_XFRDONE) {
+ if (cmd->data->flags & MMC_DATA_READ) {
+ WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS |
+ PDC_PTCR_TXTDIS);
+ cmd->error = MMC_ERR_NONE;
+ at91_mci_next_operation(sc);
+ } else {
+ if (sr & MCI_SR_BLKE)
+ isr |= MCI_SR_BLKE;
+ else
+ WR4(sc, MCI_IER, MCI_SR_BLKE);
+ }
+ }
+#endif /* __rtems__ */
+ if (isr & MCI_SR_NOTBUSY) {
+// printf("NOTBUSY\n");
+ at91_mci_notbusy(sc);
+ }
+ if (isr & MCI_SR_DTIP) {
+// printf("Data transfer in progress\n");
+ }
+ if (isr & MCI_SR_BLKE) {
+// printf("Block transfer end\n");
+ at91_mci_write_done(sc, sr);
+ }
+ if (isr & MCI_SR_TXRDY) {
+// printf("Ready to transmit\n");
+ }
+ if (isr & MCI_SR_RXRDY) {
+// printf("Ready to receive\n");
+ }
+ if (isr & MCI_SR_CMDRDY) {
+// printf("Command ready\n");
+ at91_mci_cmdrdy(sc, sr);
+ }
+ }
+ AT91_MCI_UNLOCK(sc);
+}
+
+static int
+at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
+{
+ struct at91_mci_softc *sc = device_get_softc(bus);
+
+ switch (which) {
+ default:
+ return (EINVAL);
+ case MMCBR_IVAR_BUS_MODE:
+ *(int *)result = sc->host.ios.bus_mode;
+ break;
+ case MMCBR_IVAR_BUS_WIDTH:
+ *(int *)result = sc->host.ios.bus_width;
+ break;
+ case MMCBR_IVAR_CHIP_SELECT:
+ *(int *)result = sc->host.ios.chip_select;
+ break;
+ case MMCBR_IVAR_CLOCK:
+ *(int *)result = sc->host.ios.clock;
+ break;
+ case MMCBR_IVAR_F_MIN:
+ *(int *)result = sc->host.f_min;
+ break;
+ case MMCBR_IVAR_F_MAX:
+ *(int *)result = sc->host.f_max;
+ break;
+ case MMCBR_IVAR_HOST_OCR:
+ *(int *)result = sc->host.host_ocr;
+ break;
+ case MMCBR_IVAR_MODE:
+ *(int *)result = sc->host.mode;
+ break;
+ case MMCBR_IVAR_OCR:
+ *(int *)result = sc->host.ocr;
+ break;
+ case MMCBR_IVAR_POWER_MODE:
+ *(int *)result = sc->host.ios.power_mode;
+ break;
+ case MMCBR_IVAR_VDD:
+ *(int *)result = sc->host.ios.vdd;
+ break;
+ case MMCBR_IVAR_CAPS:
+ if (sc->has_4wire) {
+ sc->sc_cap |= CAP_HAS_4WIRE;
+ sc->host.caps |= MMC_CAP_4_BIT_DATA;
+ } else {
+ sc->sc_cap &= ~CAP_HAS_4WIRE;
+ sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
+ }
+ *(int *)result = sc->host.caps;
+ break;
+#ifdef __rtems__
+ case MMCBR_IVAR_TIMING:
+ *result = sc->host.ios.timing;
+ break;
+#endif /* __rtems__ */
+ case MMCBR_IVAR_MAX_DATA:
+ /*
+ * Something is wrong with the 2x parts and multiblock, so
+ * just do 1 block at a time for now, which really kills
+ * performance.
+ */
+ if (sc->sc_cap & CAP_MCI1_REV2XX)
+ *(int *)result = 1;
+ else
+ *(int *)result = MAX_BLOCKS;
+ break;
+ }
+ return (0);
+}
+
+static int
+at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
+{
+ struct at91_mci_softc *sc = device_get_softc(bus);
+
+ switch (which) {
+ default:
+ return (EINVAL);
+ case MMCBR_IVAR_BUS_MODE:
+ sc->host.ios.bus_mode = value;
+ break;
+ case MMCBR_IVAR_BUS_WIDTH:
+ sc->host.ios.bus_width = value;
+ break;
+ case MMCBR_IVAR_CHIP_SELECT:
+ sc->host.ios.chip_select = value;
+ break;
+ case MMCBR_IVAR_CLOCK:
+ sc->host.ios.clock = value;
+ break;
+ case MMCBR_IVAR_MODE:
+ sc->host.mode = value;
+ break;
+ case MMCBR_IVAR_OCR:
+ sc->host.ocr = value;
+ break;
+ case MMCBR_IVAR_POWER_MODE:
+ sc->host.ios.power_mode = value;
+ break;
+ case MMCBR_IVAR_VDD:
+ sc->host.ios.vdd = value;
+ break;
+#ifdef __rtems__
+ case MMCBR_IVAR_TIMING:
+ sc->host.ios.timing = value;
+ break;
+#endif /* __rtems__ */
+ /* These are read-only */
+ case MMCBR_IVAR_CAPS:
+ case MMCBR_IVAR_HOST_OCR:
+ case MMCBR_IVAR_F_MIN:
+ case MMCBR_IVAR_F_MAX:
+ case MMCBR_IVAR_MAX_DATA:
+ return (EINVAL);
+ }
+ return (0);
+}
+
+static device_method_t at91_mci_methods[] = {
+ /* device_if */
+ DEVMETHOD(device_probe, at91_mci_probe),
+ DEVMETHOD(device_attach, at91_mci_attach),
+ DEVMETHOD(device_detach, at91_mci_detach),
+
+ /* Bus interface */
+ DEVMETHOD(bus_read_ivar, at91_mci_read_ivar),
+ DEVMETHOD(bus_write_ivar, at91_mci_write_ivar),
+
+ /* mmcbr_if */
+ DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
+ DEVMETHOD(mmcbr_request, at91_mci_request),
+ DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
+ DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
+ DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
+
+ DEVMETHOD_END
+};
+
+static driver_t at91_mci_driver = {
+ "at91_mci",
+ at91_mci_methods,
+ sizeof(struct at91_mci_softc),
+};
+
+static devclass_t at91_mci_devclass;
+
+#ifndef __rtems__
+#ifdef FDT
+DRIVER_MODULE(at91_mci, simplebus, at91_mci_driver, at91_mci_devclass, NULL,
+ NULL);
+#else
+DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,
+ NULL);
+#endif
+
+MMC_DECLARE_BRIDGE(at91_mci);
+#else /* __rtems__ */
+DRIVER_MODULE(at91_mci, nexus, at91_mci_driver, at91_mci_devclass, NULL, NULL);
+#endif /* __rtems__ */
+DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL);
+MODULE_DEPEND(at91_mci, mmc, 1, 1, 1);
+#endif /* __rtems__ && LIBBSP_ARM_ATSAM_BSP_H */
diff --git a/rtemsbsd/sys/arm/at91/at91_mcireg.h b/rtemsbsd/sys/arm/at91/at91_mcireg.h
new file mode 100644
index 00000000..80acf48d
--- /dev/null
+++ b/rtemsbsd/sys/arm/at91/at91_mcireg.h
@@ -0,0 +1,183 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2006 Berndt Walter. All rights reserved.
+ * Copyright (c) 2006 M. Warner Losh.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef ARM_AT91_AT91_MCIREG_H
+#define ARM_AT91_AT91_MCIREG_H
+
+#define MMC_MAX 30
+
+#define MCI_CR 0x00 /* MCI Control Register */
+#define MCI_MR 0x04 /* MCI Mode Register */
+#define MCI_DTOR 0x08 /* MCI Data Timeout Register */
+#define MCI_SDCR 0x0c /* MCI SD Card Register */
+#define MCI_ARGR 0x10 /* MCI Argument Register */
+#define MCI_CMDR 0x14 /* MCI Command Register */
+#ifdef __rtems__
+#define MCI_BLKR 0x18 /* MCI Block Register */
+#endif /* __rtems__ */
+#define MCI_RSPR 0x20 /* MCI Response Registers - 4 of them */
+#define MCI_RDR 0x30 /* MCI Receive Data Register */
+#define MCI_TDR 0x34 /* MCI Transmit Data Register */
+#define MCI_SR 0x40 /* MCI Status Register */
+#define MCI_IER 0x44 /* MCI Interrupt Enable Register */
+#define MCI_IDR 0x48 /* MCI Interrupt Disable Register */
+#define MCI_IMR 0x4c /* MCI Interrupt Mask Register */
+#ifdef __rtems__
+#define MCI_DMA 0x50 /* MCI DMA Control Register */
+#endif /* __rtems__ */
+
+/* -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- */
+#define MCI_CR_MCIEN (0x1u << 0) /* (MCI) Multimedia Interface Enable */
+#define MCI_CR_MCIDIS (0x1u << 1) /* (MCI) Multimedia Interface Disable */
+#define MCI_CR_PWSEN (0x1u << 2) /* (MCI) Power Save Mode Enable */
+#define MCI_CR_PWSDIS (0x1u << 3) /* (MCI) Power Save Mode Disable */
+#define MCI_CR_SWRST (0x1u << 7) /* (MCI) Software Reset */
+/* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- */
+#define MCI_MR_CLKDIV (0xffu << 0) /* (MCI) Clock Divider */
+#define MCI_MR_PWSDIV (0x3fu << 8) /* (MCI) Power Saving Divider */
+#define MCI_MR_RDPROOF (0x1u << 11) /* (MCI) Read Proof Enable */
+#define MCI_MR_WRPROOF (0x1u << 12) /* (MCI) Write Proof Enable */
+#define MCI_MR_PDCFBYTE (0x1u << 13) /* (MCI) PDC Force Byte Transfer */
+#define MCI_MR_PDCPADV (0x1u << 14) /* (MCI) PDC Padding Value */
+#define MCI_MR_PDCMODE (0x1u << 15) /* (MCI) PDC Oriented Mode */
+#define MCI_MR_CLKODD (0x1u << 16) /* (MCI) Clock Divider is Odd */
+#define MCI_MR_BLKLEN 0x3fff0000ul /* (MCI) Data Block Length */
+/* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- */
+#define MCI_DTOR_DTOCYC (0xfu << 0) /* (MCI) Data Timeout Cycle Number */
+#define MCI_DTOR_DTOMUL (0x7u << 4) /* (MCI) Data Timeout Multiplier */
+#define MCI_DTOR_DTOMUL_1 (0x0u << 4) /* (MCI) DTOCYC x 1 */
+#define MCI_DTOR_DTOMUL_16 (0x1u << 4) /* (MCI) DTOCYC x 16 */
+#define MCI_DTOR_DTOMUL_128 (0x2u << 4) /* (MCI) DTOCYC x 128 */
+#define MCI_DTOR_DTOMUL_256 (0x3u << 4) /* (MCI) DTOCYC x 256 */
+#define MCI_DTOR_DTOMUL_1k (0x4u << 4) /* (MCI) DTOCYC x 1024 */
+#define MCI_DTOR_DTOMUL_4k (0x5u << 4) /* (MCI) DTOCYC x 4096 */
+#define MCI_DTOR_DTOMUL_64k (0x6u << 4) /* (MCI) DTOCYC x 65536 */
+#define MCI_DTOR_DTOMUL_1M (0x7u << 4) /* (MCI) DTOCYC x 1048576 */
+/* -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- */
+#define MCI_SDCR_SDCSEL (0x1u << 0) /* (MCI) SD Card Selector */
+#define MCI_SDCR_SDCBUS (0x1u << 7) /* (MCI) SD Card Bus Width */
+/* -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- */
+#define MCI_CMDR_CMDNB (0x1Fu << 0) /* (MCI) Command Number */
+#define MCI_CMDR_RSPTYP (0x3u << 6) /* (MCI) Response Type */
+#define MCI_CMDR_RSPTYP_NO (0x0u << 6) /* (MCI) No response */
+#define MCI_CMDR_RSPTYP_48 (0x1u << 6) /* (MCI) 48-bit response */
+#define MCI_CMDR_RSPTYP_136 (0x2u << 6) /* (MCI) 136-bit response */
+#define MCI_CMDR_SPCMD (0x7u << 8) /* (MCI) Special CMD */
+#define MCI_CMDR_SPCMD_NONE (0x0u << 8) /* (MCI) Not a special CMD */
+#define MCI_CMDR_SPCMD_INIT (0x1u << 8) /* (MCI) Initialization CMD */
+#define MCI_CMDR_SPCMD_SYNC (0x2u << 8) /* (MCI) Synchronized CMD */
+#define MCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /* (MCI) Interrupt command */
+#define MCI_CMDR_SPCMD_IT_REP (0x5u << 8) /* (MCI) Interrupt response */
+#define MCI_CMDR_OPDCMD (0x1u << 11) /* (MCI) Open Drain Command */
+#define MCI_CMDR_MAXLAT (0x1u << 12) /* (MCI) Maximum Latency for Command to respond */
+#define MCI_CMDR_TRCMD (0x3u << 16) /* (MCI) Transfer CMD */
+#define MCI_CMDR_TRCMD_NO (0x0u << 16) /* (MCI) No transfer */
+#define MCI_CMDR_TRCMD_START (0x1u << 16) /* (MCI) Start transfer */
+#define MCI_CMDR_TRCMD_STOP (0x2u << 16) /* (MCI) Stop transfer */
+#define MCI_CMDR_TRDIR (0x1u << 18) /* (MCI) Transfer Direction */
+#define MCI_CMDR_TRTYP (0x3u << 19) /* (MCI) Transfer Type */
+#define MCI_CMDR_TRTYP_BLOCK (0x0u << 19) /* (MCI) Block Transfer type */
+#define MCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /* (MCI) Multiple Block transfer type */
+#define MCI_CMDR_TRTYP_STREAM (0x2u << 19) /* (MCI) Stream transfer type */
+#ifdef __rtems__
+/* -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- */
+#define MCI_BLKR_BCNT (0xFFFFu << 0)
+#define MCI_BLKR_BLKLEN (0xFFFFu << 16)
+#endif /* __rtems__ */
+/* -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- */
+#define MCI_SR_CMDRDY (0x1u << 0) /* (MCI) Command Ready flag */
+#define MCI_SR_RXRDY (0x1u << 1) /* (MCI) RX Ready flag */
+#define MCI_SR_TXRDY (0x1u << 2) /* (MCI) TX Ready flag */
+#define MCI_SR_BLKE (0x1u << 3) /* (MCI) Data Block Transfer Ended flag */
+#define MCI_SR_DTIP (0x1u << 4) /* (MCI) Data Transfer in Progress flag */
+#define MCI_SR_NOTBUSY (0x1u << 5) /* (MCI) Data Line Not Busy flag */
+#define MCI_SR_ENDRX (0x1u << 6) /* (MCI) End of RX Buffer flag */
+#define MCI_SR_ENDTX (0x1u << 7) /* (MCI) End of TX Buffer flag */
+#define MCI_SR_RXBUFF (0x1u << 14) /* (MCI) RX Buffer Full flag */
+#define MCI_SR_TXBUFE (0x1u << 15) /* (MCI) TX Buffer Empty flag */
+#define MCI_SR_RINDE (0x1u << 16) /* (MCI) Response Index Error flag */
+#define MCI_SR_RDIRE (0x1u << 17) /* (MCI) Response Direction Error flag */
+#define MCI_SR_RCRCE (0x1u << 18) /* (MCI) Response CRC Error flag */
+#define MCI_SR_RENDE (0x1u << 19) /* (MCI) Response End Bit Error flag */
+#define MCI_SR_RTOE (0x1u << 20) /* (MCI) Response Time-out Error flag */
+#define MCI_SR_DCRCE (0x1u << 21) /* (MCI) data CRC Error flag */
+#define MCI_SR_DTOE (0x1u << 22) /* (MCI) Data timeout Error flag */
+#define MCI_SR_OVRE (0x1u << 30) /* (MCI) Overrun flag */
+#define MCI_SR_UNRE (0x1u << 31) /* (MCI) Underrun flag */
+#ifdef __rtems__
+#define MCI_SR_XFRDONE (0x1u << 27) /* (MCI) Underrun flag */
+#endif /* __rtems__ */
+#ifdef __rtems__
+/* -------- MCI_DMA : (MCI Offset: 0x50) MCI DMA Control Register -------- */
+#define MCI_DMA_DMAEN (0x1u << 8)
+#define MCI_DMA_CHKSIZE (0x7u << 4)
+#define MCI_DMA_CHKSIZE_1 (0x0u << 4)
+#define MCI_DMA_CHKSIZE_2 (0x1u << 4)
+#define MCI_DMA_CHKSIZE_4 (0x2u << 4)
+#define MCI_DMA_CHKSIZE_8 (0x3u << 4)
+#define MCI_DMA_CHKSIZE_16 (0x4u << 4)
+#endif /* __rtems__ */
+
+/* TXRDY,DTIP,ENDTX,TXBUFE,RTOE */
+
+#define MCI_SR_BITSTRING \
+ "\020" \
+ "\001CMDRDY" \
+ "\002RXRDY" \
+ "\003TXRDY" \
+ "\004BLKE" \
+ "\005DTIP" \
+ "\006NOTBUSY" \
+ "\007ENDRX" \
+ "\010ENDTX" \
+ "\017RXBUFF" \
+ "\020TXBUFE" \
+ "\021RINDE" \
+ "\022RDIRE" \
+ "\023RCRCE" \
+ "\024RENDE" \
+ "\025RTOE" \
+ "\026DCRCE" \
+ "\027DTOE" \
+ "\037OVRE" \
+ "\040UNRE"
+
+/* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- */
+/* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- */
+/* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- */
+
+#define MCI_SR_ERROR (MCI_SR_UNRE | MCI_SR_OVRE | MCI_SR_DTOE | \
+ MCI_SR_DCRCE | MCI_SR_RTOE | MCI_SR_RENDE | \
+ MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE)
+
+#define AT91C_BUS_WIDTH_1BIT 0x00
+#define AT91C_BUS_WIDTH_4BITS 0x02
+
+#endif /* ARM_AT91_AT91_MCIREG_H */
diff --git a/rtemsbsd/sys/arm/at91/at91_pdcreg.h b/rtemsbsd/sys/arm/at91/at91_pdcreg.h
new file mode 100644
index 00000000..659804bd
--- /dev/null
+++ b/rtemsbsd/sys/arm/at91/at91_pdcreg.h
@@ -0,0 +1,50 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2006 M. Warner Losh.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef ARM_AT91_AT91_PDCREG_H
+#define ARM_AT91_AT91_PDCREG_H
+
+#define PDC_RPR 0x100 /* PDC Receive Pointer Register */
+#define PDC_RCR 0x104 /* PDC Receive Counter Register */
+#define PDC_TPR 0x108 /* PDC Transmit Pointer Register */
+#define PDC_TCR 0x10c /* PDC Transmit Counter Register */
+#define PDC_RNPR 0x110 /* PDC Receive Next Pointer Register */
+#define PDC_RNCR 0x114 /* PDC Receive Next Counter Register */
+#define PDC_TNPR 0x118 /* PDC Transmit Next Pointer Reg */
+#define PDC_TNCR 0x11c /* PDC Transmit Next Counter Reg */
+#define PDC_PTCR 0x120 /* PDC Transfer Control Register */
+#define PDC_PTSR 0x124 /* PDC Transfer Status Register */
+
+/* PTCR/PTSR */
+#define PDC_PTCR_RXTEN (1UL << 0) /* RXTEN: Receiver Transfer Enable */
+#define PDC_PTCR_RXTDIS (1UL << 1) /* RXTDIS: Receiver Transfer Disable */
+#define PDC_PTCR_TXTEN (1UL << 8) /* TXTEN: Transmitter Transfer En */
+#define PDC_PTCR_TXTDIS (1UL << 9) /* TXTDIS: Transmitter Transmit Dis */
+
+#endif /* ARM_AT91_AT91_PDCREG_H */
diff --git a/rtemsbsd/sys/arm/at91/at91reg.h b/rtemsbsd/sys/arm/at91/at91reg.h
new file mode 100644
index 00000000..f5791bd7
--- /dev/null
+++ b/rtemsbsd/sys/arm/at91/at91reg.h
@@ -0,0 +1,92 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2009 Greg Ansley All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * $FreeBSD$
+ */
+
+#ifndef _AT91REG_H_
+#define _AT91REG_H_
+
+#include <rtems/bsd/local/opt_at91.h>
+
+/* Where builtin peripherals start in KVM */
+#define AT91_BASE 0xd0000000
+
+/* Where builtin peripherals start PA */
+#define AT91_PA_BASE 0xf0000000
+
+/* A few things that we count on being the same
+ * throughout the whole family of SOCs */
+
+/* SYSC System Controller */
+/* System Registers */
+#define AT91_SYS_BASE 0xffff000
+#define AT91_SYS_SIZE 0x1000
+
+#define AT91_DBGU0 0x0ffff200 /* Most */
+#define AT91_DBGU1 0x0fffee00 /* SAM9263, CAP9, and SAM9G45 */
+
+#define AT91_DBGU_SIZE 0x200
+#define DBGU_C1R (64) /* Chip ID1 Register */
+#define DBGU_C2R (68) /* Chip ID2 Register */
+#define DBGU_FNTR (72) /* Force NTRST Register */
+
+#define AT91_CPU_VERSION_MASK 0x0000001f
+#define AT91_CPU_FAMILY_MASK 0x0ff00000
+
+#define AT91_CPU_RM9200 0x09290780
+#define AT91_CPU_SAM9260 0x019803a0
+#define AT91_CPU_SAM9261 0x019703a0
+#define AT91_CPU_SAM9263 0x019607a0
+#define AT91_CPU_SAM9G10 0x819903a0
+#define AT91_CPU_SAM9G20 0x019905a0
+#define AT91_CPU_SAM9G45 0x819b05a0
+#define AT91_CPU_SAM9N12 0x819a07a0
+#define AT91_CPU_SAM9RL64 0x019b03a0
+#define AT91_CPU_SAM9X5 0x819a05a0
+
+#define AT91_CPU_SAM9XE128 0x329973a0
+#define AT91_CPU_SAM9XE256 0x329a93a0
+#define AT91_CPU_SAM9XE512 0x329aa3a0
+
+#define AT91_CPU_CAP9 0x039a03a0
+
+#define AT91_EXID_SAM9M11 0x00000001
+#define AT91_EXID_SAM9M10 0x00000002
+#define AT91_EXID_SAM9G46 0x00000003
+#define AT91_EXID_SAM9G45 0x00000004
+
+#define AT91_EXID_SAM9G15 0x00000000
+#define AT91_EXID_SAM9G35 0x00000001
+#define AT91_EXID_SAM9X35 0x00000002
+#define AT91_EXID_SAM9G25 0x00000003
+#define AT91_EXID_SAM9X25 0x00000004
+
+#define AT91_IRQ_SYSTEM 1
+
+#endif /* _AT91REG_H_ */
diff --git a/rtemsbsd/sys/arm/at91/at91var.h b/rtemsbsd/sys/arm/at91/at91var.h
new file mode 100644
index 00000000..84c898fb
--- /dev/null
+++ b/rtemsbsd/sys/arm/at91/at91var.h
@@ -0,0 +1,175 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2005 Olivier Houchard. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* $FreeBSD$ */
+
+#ifndef _AT91VAR_H_
+#define _AT91VAR_H_
+
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <arm/at91/at91reg.h>
+
+struct at91_softc {
+ device_t dev;
+ bus_space_tag_t sc_st;
+ bus_space_handle_t sc_sh;
+ bus_space_handle_t sc_aic_sh;
+ struct rman sc_irq_rman;
+ struct rman sc_mem_rman;
+};
+
+struct at91_ivar {
+ struct resource_list resources;
+};
+
+struct cpu_devs
+{
+ const char *name;
+ int unit;
+ bus_addr_t mem_base;
+ bus_size_t mem_len;
+ int irq0;
+ int irq1;
+ int irq2;
+ const char *parent_clk;
+};
+
+enum at91_soc_type {
+ AT91_T_NONE = 0,
+ AT91_T_CAP9,
+ AT91_T_RM9200,
+ AT91_T_SAM9260,
+ AT91_T_SAM9261,
+ AT91_T_SAM9263,
+ AT91_T_SAM9G10,
+ AT91_T_SAM9G20,
+ AT91_T_SAM9G45,
+ AT91_T_SAM9N12,
+ AT91_T_SAM9RL,
+ AT91_T_SAM9X5,
+};
+
+enum at91_soc_subtype {
+ AT91_ST_ANY = -1, /* Match any type */
+ AT91_ST_NONE = 0,
+ /* AT91RM9200 */
+ AT91_ST_RM9200_BGA,
+ AT91_ST_RM9200_PQFP,
+ /* AT91SAM9260 */
+ AT91_ST_SAM9XE,
+ /* AT91SAM9G45 */
+ AT91_ST_SAM9G45,
+ AT91_ST_SAM9M10,
+ AT91_ST_SAM9G46,
+ AT91_ST_SAM9M11,
+ /* AT91SAM9X5 */
+ AT91_ST_SAM9G15,
+ AT91_ST_SAM9G25,
+ AT91_ST_SAM9G35,
+ AT91_ST_SAM9X25,
+ AT91_ST_SAM9X35,
+};
+
+enum at91_soc_family {
+ AT91_FAMILY_SAM9 = 0x19,
+ AT91_FAMILY_SAM9XE = 0x29,
+ AT91_FAMILY_RM92 = 0x92,
+};
+
+#define AT91_SOC_NAME_MAX 50
+
+typedef void (*DELAY_t)(int);
+typedef void (*cpu_reset_t)(void);
+typedef void (*clk_init_t)(void);
+
+struct at91_soc_data {
+ DELAY_t soc_delay; /* SoC specific delay function */
+ cpu_reset_t soc_reset; /* SoC specific reset function */
+ clk_init_t soc_clock_init; /* SoC specific clock init function */
+ const int *soc_irq_prio; /* SoC specific IRQ priorities */
+ const struct cpu_devs *soc_children; /* SoC specific children list */
+ const uint32_t *soc_pio_base; /* SoC specific PIO base registers */
+ size_t soc_pio_count; /* Count of PIO units (not pins) in SoC */
+};
+
+struct at91_soc_info {
+ enum at91_soc_type type;
+ enum at91_soc_subtype subtype;
+ enum at91_soc_family family;
+ uint32_t cidr;
+ uint32_t exid;
+ char name[AT91_SOC_NAME_MAX];
+ uint32_t dbgu_base;
+ struct at91_soc_data *soc_data;
+};
+
+extern struct at91_soc_info soc_info;
+
+static inline int at91_is_rm92(void);
+static inline int at91_is_sam9(void);
+static inline int at91_is_sam9xe(void);
+static inline int at91_cpu_is(u_int cpu);
+
+static inline int
+at91_is_rm92(void)
+{
+
+ return (soc_info.type == AT91_T_RM9200);
+}
+
+static inline int
+at91_is_sam9(void)
+{
+
+ return (soc_info.family == AT91_FAMILY_SAM9);
+}
+
+static inline int
+at91_is_sam9xe(void)
+{
+
+ return (soc_info.family == AT91_FAMILY_SAM9XE);
+}
+
+static inline int
+at91_cpu_is(u_int cpu)
+{
+
+ return (soc_info.type == cpu);
+}
+
+void at91_add_child(device_t dev, int prio, const char *name, int unit,
+ bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2);
+
+extern uint32_t at91_irq_system;
+extern uint32_t at91_master_clock;
+void at91_pmc_init_clock(void);
+void at91_soc_id(void);
+
+#endif /* _AT91VAR_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-28 04:41:48 +0000