diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-02-09 07:14:11 -0600 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-03-10 08:57:59 -0600 |
| commit | e256668d6e902dece2e18ae106303ba24085c07f (patch) | |
| tree | ba2157acb23f9a07e32c0050b0532bd9b42122c6 /freebsd | |
| parent | nexus: Switch ZynqMP platforms to CGEM3 (diff) | |
| download | rtems-libbsd-e256668d6e902dece2e18ae106303ba24085c07f.tar.bz2 | |
nexus: Add ZynqMP SLCR driver
Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
Diffstat (limited to 'freebsd')
| -rw-r--r-- | freebsd/sys/arm/xilinx/zy7_slcr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/freebsd/sys/arm/xilinx/zy7_slcr.c b/freebsd/sys/arm/xilinx/zy7_slcr.c index 79fccee5..4bbdb626 100644 --- a/freebsd/sys/arm/xilinx/zy7_slcr.c +++ b/freebsd/sys/arm/xilinx/zy7_slcr.c @@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$"); #include <sys/systm.h> #ifdef __rtems__ #include <sys/bus.h> +#include <bsp.h> #endif /* __rtems__ */ #include <sys/conf.h> #include <sys/kernel.h> @@ -217,6 +218,7 @@ zy7_slcr_postload_pl(int en_level_shifters) ZSLCR_UNLOCK(sc); } +#if defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) /* Override cgem_set_refclk() in gigabit ethernet driver * (sys/dev/cadence/if_cgem.c). This function is called to * request a change in the gem's reference clock speed. @@ -264,6 +266,7 @@ cgem_set_ref_clk(int unit, int frequency) return (0); } +#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */ /* * PL clocks management function |