From e256668d6e902dece2e18ae106303ba24085c07f Mon Sep 17 00:00:00 2001
From: Kinsey Moore <kinsey.moore@oarcorp.com>
Date: Tue, 9 Feb 2021 07:14:11 -0600
Subject: nexus: Add ZynqMP SLCR driver

Add a System Level Control Register driver for the Xilinx Zynq
Ultrascale+ MPSoC with basic clock control functionality for use with
the Cadence GEM. This also removes the Zynq-7000 clock control weakref
from compilation depending on the BSP in use.
---
 freebsd/sys/arm/xilinx/zy7_slcr.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'freebsd')

diff --git a/freebsd/sys/arm/xilinx/zy7_slcr.c b/freebsd/sys/arm/xilinx/zy7_slcr.c
index 79fccee5..4bbdb626 100644
--- a/freebsd/sys/arm/xilinx/zy7_slcr.c
+++ b/freebsd/sys/arm/xilinx/zy7_slcr.c
@@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/systm.h>
 #ifdef __rtems__
 #include <sys/bus.h>
+#include <bsp.h>
 #endif /* __rtems__ */
 #include <sys/conf.h>
 #include <sys/kernel.h>
@@ -217,6 +218,7 @@ zy7_slcr_postload_pl(int en_level_shifters)
 	ZSLCR_UNLOCK(sc);
 }
 
+#if defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H)
 /* Override cgem_set_refclk() in gigabit ethernet driver
  * (sys/dev/cadence/if_cgem.c).  This function is called to
  * request a change in the gem's reference clock speed.
@@ -264,6 +266,7 @@ cgem_set_ref_clk(int unit, int frequency)
 
 	return (0);
 }
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */
 
 /* 
  * PL clocks management function
-- 
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