Move files to match FreeBSD layout

4 files changed, 855 insertions, 0 deletions

diff --git a/freebsd/sys/sparc64/include/machine/asi.h b/freebsd/sys/sparc64/include/machine/asi.h
new file mode 100644
index 00000000..83a42ff3
--- /dev/null
+++ b/freebsd/sys/sparc64/include/machine/asi.h
@@ -0,0 +1,260 @@
+/*-
+ * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Berkeley Software Design Inc's name may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	from: BSDI: asi.h,v 1.3 1997/08/08 14:31:42 torek
+ * $FreeBSD$
+ */
+
+#ifndef	_MACHINE_ASI_HH_
+#define	_MACHINE_ASI_HH_
+
+/*
+ * Standard v9 ASIs
+ */
+#define	ASI_N					0x4
+#define	ASI_NL					0xc
+#define	ASI_AIUP				0x10
+#define	ASI_AIUS				0x11
+#define	ASI_AIUPL				0x18
+#define	ASI_AIUSL				0x19
+#define	ASI_P					0x80
+#define	ASI_S					0x81
+#define	ASI_PNF					0x82
+#define	ASI_SNF					0x83
+#define	ASI_PL					0x88
+#define	ASI_SL					0x89
+#define	ASI_PNFL				0x8a
+#define	ASI_SNFL				0x8b
+
+/*
+ * UltraSPARC extensions - ASIs limited to a certain family are annotated.
+ */
+#define	ASI_PHYS_USE_EC				0x14
+#define	ASI_PHYS_BYPASS_EC_WITH_EBIT		0x15
+#define	ASI_PHYS_USE_EC_L			0x1c
+#define	ASI_PHYS_BYPASS_EC_WITH_EBIT_L		0x1d
+
+#define	ASI_NUCLEUS_QUAD_LDD			0x24
+#define	ASI_NUCLEUS_QUAD_LDD_L			0x2c
+
+#define	ASI_PCACHE_STATUS_DATA			0x30	/* US-III Cu */
+#define	ASI_PCACHE_DATA				0x31	/* US-III Cu */
+#define	ASI_PCACHE_TAG				0x32	/* US-III Cu */
+#define	ASI_PCACHE_SNOOP_TAG			0x33	/* US-III Cu */
+
+#define	ASI_ATOMIC_QUAD_LDD_PHYS		0x34	/* US-III Cu */
+
+#define	ASI_WCACHE_VALID_BITS			0x38	/* US-III Cu */
+#define	ASI_WCACHE_DATA				0x39	/* US-III Cu */
+#define	ASI_WCACHE_TAG				0x3a	/* US-III Cu */
+#define	ASI_WCACHE_SNOOP_TAG			0x3b	/* US-III Cu */
+
+#define	ASI_ATOMIC_QUAD_LDD_PHYS_L		0x3c	/* US-III Cu */
+
+#define	ASI_SRAM_FAST_INIT			0x40	/* US-III Cu */
+
+#define	ASI_DCACHE_INVALIDATE			0x42	/* US-III Cu */
+#define	ASI_DCACHE_UTAG				0x43	/* US-III Cu */
+#define	ASI_DCACHE_SNOOP_TAG			0x44	/* US-III Cu */
+
+/* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */
+#define	ASI_LSU_CTL_REG				0x45	/* US only */
+
+#define	ASI_MCNTL				0x45	/* SPARC64 only */
+#define		AA_MCNTL			0x08
+
+#define	ASI_DCACHE_DATA				0x46
+#define	ASI_DCACHE_TAG				0x47
+
+#define	ASI_INTR_DISPATCH_STATUS		0x48
+#define	ASI_INTR_RECEIVE			0x49
+#define	ASI_UPA_CONFIG_REG			0x4a	/* US-I, II */
+
+#define	ASI_FIREPLANE_CONFIG_REG		0x4a	/* US-III{,+}, IV{,+} */
+#define		AA_FIREPLANE_CONFIG		0x0	/* US-III{,+}, IV{,+} */
+#define		AA_FIREPLANE_ADDRESS		0x8	/* US-III{,+}, IV{,+} */
+#define		AA_FIREPLANE_CONFIG_2		0x10	/* US-IV{,+} */
+
+#define	ASI_JBUS_CONFIG_REG			0x4a	/* US-IIIi{,+} */
+
+#define	ASI_ESTATE_ERROR_EN_REG			0x4b
+#define		AA_ESTATE_CEEN			0x1
+#define		AA_ESTATE_NCEEN			0x2
+#define		AA_ESTATE_ISAPEN		0x4
+
+#define	ASI_AFSR				0x4c
+#define	ASI_AFAR				0x4d
+
+#define	ASI_ECACHE_TAG_DATA			0x4e
+
+#define	ASI_IMMU_TAG_TARGET_REG			0x50
+#define	ASI_IMMU				0x50
+#define		AA_IMMU_TTR			0x0
+#define		AA_IMMU_SFSR			0x18
+#define		AA_IMMU_TSB			0x28
+#define		AA_IMMU_TAR			0x30
+#define		AA_IMMU_TSB_PEXT_REG		0x48	/* US-III family */
+#define		AA_IMMU_TSB_SEXT_REG		0x50	/* US-III family */
+#define		AA_IMMU_TSB_NEXT_REG		0x58	/* US-III family */
+
+#define	ASI_IMMU_TSB_8KB_PTR_REG		0x51
+#define	ASI_IMMU_TSB_64KB_PTR_REG		0x52
+
+#define	ASI_SERIAL_ID				0x53	/* US-III family */
+
+#define	ASI_ITLB_DATA_IN_REG			0x54
+/* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */
+#define	ASI_ITLB_DATA_ACCESS_REG		0x55
+#define	ASI_ITLB_TAG_READ_REG			0x56
+#define	ASI_IMMU_DEMAP				0x57
+
+#define	ASI_DMMU_TAG_TARGET_REG			0x58
+#define	ASI_DMMU				0x58
+#define		AA_DMMU_TTR			0x0
+#define		AA_DMMU_PCXR			0x8
+#define		AA_DMMU_SCXR			0x10
+#define		AA_DMMU_SFSR			0x18
+#define		AA_DMMU_SFAR			0x20
+#define		AA_DMMU_TSB			0x28
+#define		AA_DMMU_TAR			0x30
+#define		AA_DMMU_VWPR			0x38
+#define		AA_DMMU_PWPR			0x40
+#define		AA_DMMU_TSB_PEXT_REG		0x48
+#define		AA_DMMU_TSB_SEXT_REG		0x50
+#define		AA_DMMU_TSB_NEXT_REG		0x58
+#define		AA_DMMU_TAG_ACCESS_EXT		0x60	/* US-III family */
+
+#define	ASI_DMMU_TSB_8KB_PTR_REG		0x59
+#define	ASI_DMMU_TSB_64KB_PTR_REG		0x5a
+#define	ASI_DMMU_TSB_DIRECT_PTR_REG		0x5b
+#define	ASI_DTLB_DATA_IN_REG			0x5c
+/* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */
+#define	ASI_DTLB_DATA_ACCESS_REG		0x5d
+#define	ASI_DTLB_TAG_READ_REG			0x5e
+#define	ASI_DMMU_DEMAP				0x5f
+
+#define	ASI_IIU_INST_TRAP			0x60	/* US-III family */
+
+#define	ASI_INTR_ID				0x63	/* US-IV{,+} */
+#define		AA_INTR_ID			0x0	/* US-IV{,+} */
+#define		AA_CORE_ID			0x10	/* US-IV{,+} */
+#define		AA_CESR_ID			0x40	/* US-IV{,+} */
+
+#define	ASI_ICACHE_INSTR			0x66
+#define	ASI_ICACHE_TAG				0x67
+#define	ASI_ICACHE_SNOOP_TAG			0x68	/* US-III family */
+#define	ASI_ICACHE_PRE_DECODE			0x6e	/* US-I, II */
+#define	ASI_ICACHE_PRE_NEXT_FIELD		0x6f	/* US-I, II */
+
+#define	ASI_FLUSH_L1I				0x67	/* SPARC64 only */
+
+#define	ASI_BLK_AUIP				0x70
+#define	ASI_BLK_AIUS				0x71
+
+#define	ASI_MCU_CONFIG_REG			0x72	/* US-III Cu */
+#define		AA_MCU_TIMING1_REG		0x0	/* US-III Cu */
+#define		AA_MCU_TIMING2_REG		0x8	/* US-III Cu */
+#define		AA_MCU_TIMING3_REG		0x10	/* US-III Cu */
+#define		AA_MCU_TIMING4_REG		0x18	/* US-III Cu */
+#define		AA_MCU_DEC1_REG			0x20	/* US-III Cu */
+#define		AA_MCU_DEC2_REG			0x28	/* US-III Cu */
+#define		AA_MCU_DEC3_REG			0x30	/* US-III Cu */
+#define		AA_MCU_DEC4_REG			0x38	/* US-III Cu */
+#define		AA_MCU_ADDR_CNTL_REG		0x40	/* US-III Cu */
+
+#define	ASI_ECACHE_DATA				0x74	/* US-III Cu */
+#define	ASI_ECACHE_CONTROL			0x75	/* US-III Cu */
+#define	ASI_ECACHE_W				0x76
+
+/*
+ * With the advent of the US-III, the numbering has changed, as additional
+ * registers were inserted in between.  We retain the original ordering for
+ * now, and append an A to the inserted registers.
+ * Exceptions are AA_SDB_INTR_D6 and AA_SDB_INTR_D7, which were appended
+ * at the end.
+ */
+#define	ASI_SDB_ERROR_W				0x77
+#define	ASI_SDB_CONTROL_W			0x77
+#define	ASI_SDB_INTR_W				0x77
+#define		AA_SDB_ERR_HIGH			0x0
+#define		AA_SDB_ERR_LOW			0x18
+#define		AA_SDB_CNTL_HIGH		0x20
+#define		AA_SDB_CNTL_LOW			0x38
+#define		AA_SDB_INTR_D0			0x40
+#define		AA_SDB_INTR_D0A			0x48	/* US-III family */
+#define		AA_SDB_INTR_D1			0x50
+#define		AA_SDB_INTR_D1A			0x5A	/* US-III family */
+#define		AA_SDB_INTR_D2			0x60
+#define		AA_SDB_INTR_D2A			0x68	/* US-III family */
+#define		AA_INTR_SEND			0x70
+#define		AA_SDB_INTR_D6			0x80	/* US-III family */
+#define		AA_SDB_INTR_D7			0x88	/* US-III family */
+
+#define	ASI_BLK_AIUPL				0x78
+#define	ASI_BLK_AIUSL				0x79
+
+#define	ASI_ECACHE_R				0x7e
+
+/*
+ * These have the same registers as their corresponding write versions
+ * except for AA_INTR_SEND.
+ */
+#define	ASI_SDB_ERROR_R				0x7f
+#define	ASI_SDB_CONTROL_R			0x7f
+#define	ASI_SDB_INTR_R				0x7f
+
+#define	ASI_PST8_P				0xc0
+#define	ASI_PST8_S				0xc1
+#define	ASI_PST16_P				0xc2
+#define	ASI_PST16_S				0xc3
+#define	ASI_PST32_P				0xc4
+#define	ASI_PST32_S				0xc5
+
+#define	ASI_PST8_PL				0xc8
+#define	ASI_PST8_SL				0xc9
+#define	ASI_PST16_PL				0xca
+#define	ASI_PST16_SL				0xcb
+#define	ASI_PST32_PL				0xcc
+#define	ASI_PST32_SL				0xcd
+
+#define	ASI_FL8_P				0xd0
+#define	ASI_FL8_S				0xd1
+#define	ASI_FL16_P				0xd2
+#define	ASI_FL16_S				0xd3
+#define	ASI_FL8_PL				0xd8
+#define	ASI_FL8_SL				0xd9
+#define	ASI_FL16_PL				0xda
+#define	ASI_FL16_SL				0xdb
+
+#define	ASI_BLK_COMMIT_P			0xe0
+#define	ASI_BLK_COMMIT_S			0xe1
+#define	ASI_BLK_P				0xf0
+#define	ASI_BLK_S				0xf1
+#define	ASI_BLK_PL				0xf8
+#define	ASI_BLK_SL				0xf9
+
+#endif /* !_MACHINE_ASI_HH_ */
diff --git a/freebsd/sys/sparc64/include/machine/cpufunc.h b/freebsd/sys/sparc64/include/machine/cpufunc.h
new file mode 100644
index 00000000..7805abc4
--- /dev/null
+++ b/freebsd/sys/sparc64/include/machine/cpufunc.h
@@ -0,0 +1,268 @@
+/*-
+ * Copyright (c) 2001 Jake Burkholder.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_MACHINE_CPUFUNC_HH_
+#define	_MACHINE_CPUFUNC_HH_
+
+#include <freebsd/machine/asi.h>
+#include <freebsd/machine/pstate.h>
+
+struct thread;
+
+/*
+ * Membar operand macros for use in other macros when # is a special
+ * character.  Keep these in sync with what the hardware expects.
+ */
+#define	C_Lookaside	(0)
+#define	C_MemIssue	(1)
+#define	C_Sync		(2)
+#define	M_LoadLoad	(0)
+#define	M_StoreLoad	(1)
+#define	M_LoadStore	(2)
+#define	M_StoreStore	(3)
+
+#define	CMASK_SHIFT	(4)
+#define	MMASK_SHIFT	(0)
+
+#define	CMASK_GEN(bit)	((1 << (bit)) << CMASK_SHIFT)
+#define	MMASK_GEN(bit)	((1 << (bit)) << MMASK_SHIFT)
+
+#define	Lookaside	CMASK_GEN(C_Lookaside)
+#define	MemIssue	CMASK_GEN(C_MemIssue)
+#define	Sync		CMASK_GEN(C_Sync)
+#define	LoadLoad	MMASK_GEN(M_LoadLoad)
+#define	StoreLoad	MMASK_GEN(M_StoreLoad)
+#define	LoadStore	MMASK_GEN(M_LoadStore)
+#define	StoreStore	MMASK_GEN(M_StoreStore)
+
+#define	casa(rs1, rs2, rd, asi) ({					\
+	u_int __rd = (uint32_t)(rd);					\
+	__asm __volatile("casa [%2] %3, %4, %0"				\
+	    : "+r" (__rd), "=m" (*rs1)					\
+	    : "r" (rs1), "n" (asi), "r" (rs2), "m" (*rs1));		\
+	__rd;								\
+})
+
+#define	casxa(rs1, rs2, rd, asi) ({					\
+	u_long __rd = (uint64_t)(rd);					\
+	__asm __volatile("casxa [%2] %3, %4, %0"			\
+	    : "+r" (__rd), "=m" (*rs1)					\
+	    : "r" (rs1), "n" (asi), "r" (rs2), "m" (*rs1));		\
+	__rd;								\
+})
+
+#define	flush(va) do {							\
+	__asm __volatile("flush %0" : : "r" (va));			\
+} while (0)
+
+#define	flushw() do {							\
+	__asm __volatile("flushw" : :);					\
+} while (0)
+
+#define	mov(val, reg) do {						\
+	__asm __volatile("mov %0, %" __XSTRING(reg) : : "r" (val));	\
+} while (0)
+
+/* Generate ld*a/st*a functions for non-constant ASIs. */
+#define	LDNC_GEN(tp, o)							\
+	static __inline tp						\
+	o ## _nc(caddr_t va, int asi)					\
+	{								\
+		tp r;							\
+		__asm __volatile("wr %2, 0, %%asi;" #o " [%1] %%asi, %0"\
+		    : "=r" (r) : "r" (va), "r" (asi));			\
+		return (r);						\
+	}
+
+LDNC_GEN(u_char, lduba);
+LDNC_GEN(u_short, lduha);
+LDNC_GEN(u_int, lduwa);
+LDNC_GEN(u_long, ldxa);
+
+#define	LD_GENERIC(va, asi, op, type) ({				\
+	type __r;							\
+	__asm __volatile(#op " [%1] %2, %0"				\
+	    : "=r" (__r) : "r" (va), "n" (asi));			\
+	__r;								\
+})
+
+#define	lduba(va, asi)	LD_GENERIC(va, asi, lduba, u_char)
+#define	lduha(va, asi)	LD_GENERIC(va, asi, lduha, u_short)
+#define	lduwa(va, asi)	LD_GENERIC(va, asi, lduwa, u_int)
+#define	ldxa(va, asi)	LD_GENERIC(va, asi, ldxa, u_long)
+
+#define	STNC_GEN(tp, o)							\
+	static __inline void						\
+	o ## _nc(caddr_t va, int asi, tp val)				\
+	{								\
+		__asm __volatile("wr %2, 0, %%asi;" #o " %0, [%1] %%asi"\
+		    : : "r" (val), "r" (va), "r" (asi));		\
+	}
+
+STNC_GEN(u_char, stba);
+STNC_GEN(u_short, stha);
+STNC_GEN(u_int, stwa);
+STNC_GEN(u_long, stxa);
+
+#define	ST_GENERIC(va, asi, val, op)					\
+	__asm __volatile(#op " %0, [%1] %2"				\
+	    : : "r" (val), "r" (va), "n" (asi));			\
+
+#define	stba(va, asi, val)	ST_GENERIC(va, asi, val, stba)
+#define	stha(va, asi, val)	ST_GENERIC(va, asi, val, stha)
+#define	stwa(va, asi, val)	ST_GENERIC(va, asi, val, stwa)
+#define	stxa(va, asi, val)	ST_GENERIC(va, asi, val, stxa)
+
+/*
+ * Attempt to read from addr, val.  If a Data Access Error trap happens,
+ * they return -1 and the contents of val is undefined.  A return of 0
+ * means no trap happened, and the contents of val is valid.
+ */
+int fasword8(u_long asi, void *addr, uint8_t *val);
+int fasword16(u_long asi, void *addr, uint16_t *val);
+int fasword32(u_long asi, void *addr, uint32_t *val);
+
+#define	membar(mask) do {						\
+	__asm __volatile("membar %0" : : "n" (mask) : "memory");	\
+} while (0)
+
+#define	rd(name) ({							\
+	uint64_t __sr;							\
+	__asm __volatile("rd %%" #name ", %0" : "=r" (__sr) :);		\
+	__sr;								\
+})
+
+#define	wr(name, val, xor) do {						\
+	__asm __volatile("wr %0, %1, %%" #name				\
+	    : : "r" (val), "rI" (xor));					\
+} while (0)
+
+#define	rdpr(name) ({							\
+	uint64_t __pr;							\
+	__asm __volatile("rdpr %%" #name", %0" : "=r" (__pr) :);	\
+	__pr;								\
+})
+
+#define	wrpr(name, val, xor) do {					\
+	__asm __volatile("wrpr %0, %1, %%" #name			\
+	    : : "r" (val), "rI" (xor));					\
+} while (0)
+
+/*
+ * Trick GAS/GCC into compiling access to STICK/STICK_COMPARE independently
+ * of the selected instruction set.
+ */
+#define	rdstick()		rd(asr24)
+#define	rdstickcmpr()		rd(asr25)
+#define	wrstick(val, xor)	wr(asr24, (val), (xor))
+#define	wrstickcmpr(val, xor)	wr(asr25, (val), (xor))
+
+/*
+ * Macro intended to be used instead of wr(asr23, val, xor) for writing to
+ * the TICK_COMPARE register in order to avoid a bug in BlackBird CPUs that
+ * can cause these writes to fail under certain condidtions which in turn
+ * causes the hardclock to stop.  The workaround is to read the TICK_COMPARE
+ * register back immediately after writing to it with these two instructions
+ * aligned to a quadword boundary in order to ensure that I$ misses won't
+ * split them up.
+ */
+#define	wrtickcmpr(val, xor) ({						\
+	__asm __volatile(						\
+	"	ba,pt	%%xcc, 1f ;		"			\
+	"	 nop	 ;			"			\
+	"	.align	128 ;			"			\
+	"1:	wr	%0, %1, %%asr23 ;	"			\
+	"	rd	%%asr23, %%g0 ;		"			\
+	: : "r" (val), "rI" (xor));					\
+})
+
+static __inline void
+breakpoint(void)
+{
+
+	__asm __volatile("ta %%xcc, 1" : :);
+}
+
+static __inline register_t
+intr_disable(void)
+{
+	register_t s;
+
+	s = rdpr(pstate);
+	wrpr(pstate, s & ~PSTATE_IE, 0);
+	return (s);
+}
+#define	intr_restore(s)	wrpr(pstate, (s), 0)
+
+/*
+ * In some places, it is required that the store is directly followed by a
+ * membar #Sync.  Don't trust the compiler to not insert instructions in
+ * between.  We also need to disable interrupts completely.
+ */
+#define	stxa_sync(va, asi, val) do {					\
+	register_t s;							\
+	s = intr_disable();						\
+	__asm __volatile("stxa %0, [%1] %2; membar #Sync"		\
+	    : : "r" (val), "r" (va), "n" (asi));			\
+	intr_restore(s);						\
+} while (0)
+
+void ascopy(u_long asi, vm_offset_t src, vm_offset_t dst, size_t len);
+void ascopyfrom(u_long sasi, vm_offset_t src, caddr_t dst, size_t len);
+void ascopyto(caddr_t src, u_long dasi, vm_offset_t dst, size_t len);
+void aszero(u_long asi, vm_offset_t dst, size_t len);
+
+/*
+ * Ultrasparc II doesn't implement popc in hardware.
+ */
+#if 0
+#define	HAVE_INLINE_FFS
+/*
+ * See page 202 of the SPARC v9 Architecture Manual.
+ */
+static __inline int
+ffs(int mask)
+{
+	int result;
+	int neg;
+	int tmp;
+
+	__asm __volatile(
+	"	neg	%3, %1 ;	"
+	"	xnor	%3, %1, %2 ;	"
+	"	popc	%2, %0 ;	"
+	"	movrz	%3, %%g0, %0 ;	"
+	: "=r" (result), "=r" (neg), "=r" (tmp) : "r" (mask));
+	return (result);
+}
+#endif
+
+#undef LDNC_GEN
+#undef STNC_GEN
+
+#endif /* !_MACHINE_CPUFUNC_HH_ */
diff --git a/freebsd/sys/sparc64/include/machine/pstate.h b/freebsd/sys/sparc64/include/machine/pstate.h
new file mode 100644
index 00000000..19d98be5
--- /dev/null
+++ b/freebsd/sys/sparc64/include/machine/pstate.h
@@ -0,0 +1,63 @@
+/*-
+ * Copyright (c) 2001 Jake Burkholder.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_MACHINE_PSTATE_HH_
+#define	_MACHINE_PSTATE_HH_
+
+#define	PSTATE_AG		(1<<0)
+#define	PSTATE_IE		(1<<1)
+#define	PSTATE_PRIV		(1<<2)
+#define	PSTATE_AM		(1<<3)
+#define	PSTATE_PEF		(1<<4)
+#define	PSTATE_RED		(1<<5)
+
+#define	PSTATE_MM_SHIFT		(6)
+#define	PSTATE_MM_SIZE		(2)
+#define	PSTATE_MM_MASK		(((1<<PSTATE_MM_SIZE)-1)<<PSTATE_MM_SHIFT)
+#define	PSTATE_MM_TSO		(0<<PSTATE_MM_SHIFT)
+#define	PSTATE_MM_PSO		(1<<PSTATE_MM_SHIFT)
+#define	PSTATE_MM_RMO		(2<<PSTATE_MM_SHIFT)
+
+#define	PSTATE_TLE		(1<<8)
+#define	PSTATE_CLE		(1<<9)
+#define	PSTATE_MG		(1<<10)
+#define	PSTATE_IG		(1<<11)
+
+#define	PSTATE_MM		PSTATE_MM_TSO
+
+#define	PSTATE_NORMAL		(PSTATE_MM | PSTATE_PEF | PSTATE_PRIV)
+#define	PSTATE_ALT		(PSTATE_NORMAL | PSTATE_AG)
+#define	PSTATE_INTR		(PSTATE_NORMAL | PSTATE_IG)
+#define	PSTATE_MMU		(PSTATE_NORMAL | PSTATE_MG)
+
+#define	PSTATE_KERNEL		(PSTATE_NORMAL | PSTATE_IE)
+
+#define	PSTATE_SECURE(pstate) \
+	(((pstate) & ~(PSTATE_AM|PSTATE_MM_MASK)) == (PSTATE_IE|PSTATE_PEF))
+
+#endif /* !_MACHINE_PSTATE_HH_ */
diff --git a/freebsd/sys/sparc64/sparc64/in_cksum.c b/freebsd/sys/sparc64/sparc64/in_cksum.c
new file mode 100644
index 00000000..5490d005
--- /dev/null
+++ b/freebsd/sys/sparc64/sparc64/in_cksum.c
@@ -0,0 +1,264 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+/*-
+ * Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	from tahoe:	in_cksum.c	1.2	86/01/05
+ *	from:		@(#)in_cksum.c	1.3 (Berkeley) 1/19/91
+ * 	from: FreeBSD: src/sys/i386/i386/in_cksum.c,v 1.22 2000/11/25
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/mbuf.h>
+
+#include <freebsd/netinet/in.h>
+#include <freebsd/netinet/in_systm.h>
+#include <freebsd/netinet/ip.h>
+
+#include <freebsd/machine/in_cksum.h>
+
+/*
+ * Checksum routine for Internet Protocol family headers.
+ *
+ * This routine is very heavily used in the network
+ * code and should be modified for each CPU to be as fast as possible.
+ *
+ * This implementation is a sparc64 version.  Most code was taken over
+ * and adapted from the i386.  Some optimizations were changed to achieve
+ * (hopefully) better performance.
+ * This uses 64-bit loads, but 32-bit additions due to the lack of a 64-bit
+ * add-with-carry operation.
+ */
+
+/*
+ * REDUCE() is actually not used that frequently... maybe a C implementation
+ * would suffice.
+ */
+#define	REDUCE(sum, tmp) __asm(						\
+	"sll %2, 16, %1\n"						\
+	"addcc %2, %1, %0\n"						\
+	"srl %0, 16, %0\n"						\
+	"addc %0, 0, %0" : "=r" (sum), "=&r" (tmp) : "0" (sum) : "cc")
+
+/*
+ * Note that some of these macros depend on the flags being preserved
+ * between calls, thus they have to be used within a single __asm().
+ */
+#define	LD64_ADD32(n, mod)						\
+	"ldx [%3 + " #n "], %1\n"					\
+	"add" #mod " %2, %1, %0\n"					\
+	"srlx %1, 32, %1\n"						\
+	"addccc %0, %1, %0\n"
+
+#define	LD32_ADD32(n, mod)						\
+	"lduw [%3 + " #n "], %1\n"					\
+	"add" #mod " %2, %1, %0\n"
+
+#define	MOP(sum, tmp, addr)						\
+	"addc %2, 0, %0"						\
+	: "=r" (sum), "=&r" (tmp) : "0" (sum), "r" (addr) : "cc"
+
+u_short
+in_cksum_skip(struct mbuf *m, int len, int skip)
+{
+	u_short *w;
+	unsigned long tmp, sum = 0;
+	int mlen = 0;
+	int byte_swapped = 0;
+	u_short	su = 0;
+
+	len -= skip;
+	for (; skip > 0 && m != NULL; m = m->m_next) {
+		if (m->m_len > skip) {
+			mlen = m->m_len - skip;
+			w = (u_short *)(mtod(m, u_char *) + skip);
+			goto skip_start;
+		} else
+			skip -= m->m_len;
+	}
+
+	for (; m != NULL && len > 0; m = m->m_next) {
+		if (m->m_len == 0)
+			continue;
+		w = mtod(m, u_short *);
+		if (mlen == -1) {
+			/*
+			 * The first byte of this mbuf is the continuation
+			 * of a word spanning between this mbuf and the
+			 * last mbuf.
+			 *
+			 * The high order byte of su is already saved when
+			 * scanning previous mbuf.  sum was REDUCEd when we
+			 * found mlen == -1
+			 */
+			sum += su | *(u_char *)w;
+			w = (u_short *)((u_char *)w + 1);
+			mlen = m->m_len - 1;
+			len--;
+		} else
+			mlen = m->m_len;
+skip_start:
+		if (len < mlen)
+			mlen = len;
+		len -= mlen;
+		/*
+		 * Force to a 8-byte boundary first so that we can use
+		 * LD64_ADD32.
+		 */
+		if (((u_long)w & 7) != 0) {
+			REDUCE(sum, tmp);
+			if (((u_long)w & 1) != 0 && mlen >= 1) {
+				sum <<= 8;
+				su = *(u_char *)w << 8;
+				w = (u_short *)((u_char *)w + 1);
+				mlen--;
+				byte_swapped = 1;
+			}
+			if (((u_long)w & 2) != 0 && mlen >= 2) {
+				sum += *w++;
+				mlen -= 2;
+			}
+			if (((u_long)w & 4) != 0 && mlen >= 4) {
+				__asm(
+				    LD32_ADD32(0, cc)
+				    MOP(sum, tmp, w)
+				);
+				w += 2;
+				mlen -= 4;
+			}
+		}
+		/*
+		 * Do as much of the checksum as possible 64 bits at at time.
+		 * In fact, this loop is unrolled to make overhead from
+		 * branches &c small.
+		 */
+		for (; mlen >= 64; mlen -= 64) {
+			__asm(
+			    LD64_ADD32(0, cc)
+			    LD64_ADD32(8, ccc)
+			    LD64_ADD32(16, ccc)
+			    LD64_ADD32(24, ccc)
+			    LD64_ADD32(32, ccc)
+			    LD64_ADD32(40, ccc)
+			    LD64_ADD32(48, ccc)
+			    LD64_ADD32(56, ccc)
+			    MOP(sum, tmp, w)
+			);
+			w += 32;
+		}
+		if (mlen >= 32) {
+			__asm(
+			    LD64_ADD32(0, cc)
+			    LD64_ADD32(8, ccc)
+			    LD64_ADD32(16, ccc)
+			    LD64_ADD32(24, ccc)
+			    MOP(sum, tmp, w)
+			);
+			w += 16;
+			mlen -= 32;
+		}
+		if (mlen >= 16) {
+			__asm(
+			    LD64_ADD32(0, cc)
+			    LD64_ADD32(8, ccc)
+			    MOP(sum, tmp, w)
+			);
+			w += 8;
+			mlen -= 16;
+		}
+		if (mlen >= 8) {
+			__asm(
+			    LD64_ADD32(0, cc)
+			    MOP(sum, tmp, w)
+			);
+			w += 4;
+			mlen -= 8;
+		}
+		REDUCE(sum, tmp);
+		while ((mlen -= 2) >= 0)
+			sum += *w++;
+		if (byte_swapped) {
+			sum <<= 8;
+			byte_swapped = 0;
+			if (mlen == -1) {
+				su |= *(u_char *)w;
+				sum += su;
+				mlen = 0;
+			} else
+				mlen = -1;
+		} else if (mlen == -1) {
+			/*
+			 * This mbuf has odd number of bytes.
+			 * There could be a word split between
+			 * this mbuf and the next mbuf.
+			 * Save the last byte (to prepend to next mbuf).
+			 */
+			su = *(u_char *)w << 8;
+		}
+	}
+
+	if (len)
+		printf("%s: out of data by %d\n", __func__, len);
+	if (mlen == -1) {
+		/*
+		 * The last mbuf has odd # of bytes.  Follow the
+		 * standard (the odd byte is shifted left by 8 bits).
+		 */
+		sum += su & 0xff00;
+	}
+	REDUCE(sum, tmp);
+	return (~sum & 0xffff);
+}