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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-04-04 09:36:57 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-04-04 14:46:23 +0200 |
commit | de8a76da2f374792594ce03a203b3f30e4889f6f (patch) | |
tree | 12b5e1e59358005c3c522955c08aee4795e4829c /freebsd/sys/powerpc | |
parent | Enable bridging by default (diff) | |
download | rtems-libbsd-de8a76da2f374792594ce03a203b3f30e4889f6f.tar.bz2 |
Update to FreeBSD head 2017-04-04
Git mirror commit 642b174daddbd0efd9bb5f242c43f4ab4db6869f.
Diffstat (limited to 'freebsd/sys/powerpc')
-rw-r--r-- | freebsd/sys/powerpc/include/machine/cpufunc.h | 2 | ||||
-rw-r--r-- | freebsd/sys/powerpc/include/machine/intr_machdep.h | 64 | ||||
-rw-r--r-- | freebsd/sys/powerpc/include/machine/psl.h | 8 | ||||
-rw-r--r-- | freebsd/sys/powerpc/include/machine/spr.h | 15 |
4 files changed, 88 insertions, 1 deletions
diff --git a/freebsd/sys/powerpc/include/machine/cpufunc.h b/freebsd/sys/powerpc/include/machine/cpufunc.h index 378274b6..c70a94d3 100644 --- a/freebsd/sys/powerpc/include/machine/cpufunc.h +++ b/freebsd/sys/powerpc/include/machine/cpufunc.h @@ -201,7 +201,7 @@ intr_restore(register_t msr) } static __inline struct pcpu * -powerpc_get_pcpup(void) +get_pcpu(void) { struct pcpu *ret; diff --git a/freebsd/sys/powerpc/include/machine/intr_machdep.h b/freebsd/sys/powerpc/include/machine/intr_machdep.h new file mode 100644 index 00000000..5fbf9ee0 --- /dev/null +++ b/freebsd/sys/powerpc/include/machine/intr_machdep.h @@ -0,0 +1,64 @@ +/*- + * Copyright (C) 2002 Benno Rice. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_INTR_MACHDEP_H_ +#define _MACHINE_INTR_MACHDEP_H_ + +#define INTR_VECTORS 256 + +#define MAX_PICS 16 +#define MAP_IRQ(node, pin) powerpc_get_irq(node, pin) + +/* + * Default base address for MSI messages on PowerPC + */ +#define MSI_INTEL_ADDR_BASE 0xfee00000 + +extern device_t root_pic; + +struct trapframe; + +driver_filter_t powerpc_ipi_handler; + +void intrcnt_add(const char *name, u_long **countp); + +void powerpc_register_pic(device_t, uint32_t, u_int, u_int, u_int); +u_int powerpc_get_irq(uint32_t, u_int); + +void powerpc_dispatch_intr(u_int, struct trapframe *); +int powerpc_enable_intr(void); +int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t, + void *, enum intr_type, void **); +int powerpc_teardown_intr(void *); +int powerpc_bind_intr(u_int irq, u_char cpu); +int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity); +int powerpc_fw_config_intr(int irq, int sense_code); + +void powerpc_intr_mask(u_int irq); +void powerpc_intr_unmask(u_int irq); + +#endif /* _MACHINE_INTR_MACHDEP_H_ */ diff --git a/freebsd/sys/powerpc/include/machine/psl.h b/freebsd/sys/powerpc/include/machine/psl.h index f0a0fa4c..bb4756f0 100644 --- a/freebsd/sys/powerpc/include/machine/psl.h +++ b/freebsd/sys/powerpc/include/machine/psl.h @@ -50,6 +50,10 @@ #define PSL_PMM 0x00000004UL /* performance monitor mark */ /* Machine State Register - Book-E cores */ +#ifdef __powerpc64__ +#define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */ +#endif + #define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ #define PSL_WE 0x00040000UL /* Wait state enable */ #define PSL_CE 0x00020000UL /* Critical interrupt enable */ @@ -86,7 +90,11 @@ #if defined(BOOKE_E500) /* Initial kernel MSR, use IS=1 ad DS=1. */ #define PSL_KERNSET_INIT (PSL_IS | PSL_DS) +#ifdef __powerpc64__ +#define PSL_KERNSET (PSL_CM | PSL_CE | PSL_ME | PSL_EE) +#else #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) +#endif #define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */ #elif defined(BOOKE_PPC4XX) #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP) diff --git a/freebsd/sys/powerpc/include/machine/spr.h b/freebsd/sys/powerpc/include/machine/spr.h index 35bd9009..cc5d0b75 100644 --- a/freebsd/sys/powerpc/include/machine/spr.h +++ b/freebsd/sys/powerpc/include/machine/spr.h @@ -192,6 +192,18 @@ #define FSL_E5500 0x8024 #define FSL_E6500 0x8040 +#define SPR_EPCR 0x133 +#define EPCR_EXTGS 0x80000000 +#define EPCR_DTLBGS 0x40000000 +#define EPCR_ITLBGS 0x20000000 +#define EPCR_DSIGS 0x10000000 +#define EPCR_ISIGS 0x08000000 +#define EPCR_DUVGS 0x04000000 +#define EPCR_ICM 0x02000000 +#define EPCR_GICMGS 0x01000000 +#define EPCR_DGTMI 0x00800000 +#define EPCR_DMIUH 0x00400000 +#define EPCR_PMGS 0x00200000 #define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */ #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ @@ -259,6 +271,7 @@ #define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ #define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ #define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ +#define SPR_SPRG8 0x25c /* ..8 SPR General 8 */ #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ @@ -671,6 +684,8 @@ #define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ #define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ #define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ +#define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */ +#define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */ #define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */ #define MMUCR_SWOA (0x80000000 >> 7) |