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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-08-09 13:04:41 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-09-21 10:29:37 +0200 |
| commit | e4a8065910cd6b2e7e0448cc6431ca2906322389 (patch) | |
| tree | 73492991cfa40f994c20d761d476e6bc16304536 /freebsd/sys/mips | |
| parent | Update to FreeBSD head 2017-08-01 (diff) | |
| download | rtems-libbsd-e4a8065910cd6b2e7e0448cc6431ca2906322389.tar.bz2 | |
Update to FreeBSD head 2017-10-01
Git mirror commit b2f0376b45428f13151d229c5ae9d4d8f74acbd1.
Update #3472.
Diffstat (limited to 'freebsd/sys/mips')
| -rw-r--r-- | freebsd/sys/mips/include/machine/cpufunc.h | 9 | ||||
| -rw-r--r-- | freebsd/sys/mips/include/machine/cpuregs.h | 12 |
2 files changed, 21 insertions, 0 deletions
diff --git a/freebsd/sys/mips/include/machine/cpufunc.h b/freebsd/sys/mips/include/machine/cpufunc.h index 5ebaf4cc..d4150edd 100644 --- a/freebsd/sys/mips/include/machine/cpufunc.h +++ b/freebsd/sys/mips/include/machine/cpufunc.h @@ -279,6 +279,15 @@ MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); MIPS_RW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); + +#if defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \ + defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \ + defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \ + defined(CPU_PROAPTIV) +/* MIPS32/64 r2 intctl */ +MIPS_RW32_COP0_SEL(intctl, MIPS_COP_0_INTCTL, 1); +#endif + #ifdef CPU_XBURST MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0); MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1); diff --git a/freebsd/sys/mips/include/machine/cpuregs.h b/freebsd/sys/mips/include/machine/cpuregs.h index b6f2433e..ca86a1c5 100644 --- a/freebsd/sys/mips/include/machine/cpuregs.h +++ b/freebsd/sys/mips/include/machine/cpuregs.h @@ -468,6 +468,7 @@ * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). * 12 MIPS_COP_0_STATUS 3333 Status register. + * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt setup (MIPS32/64 r2). * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. @@ -548,6 +549,7 @@ /* MIPS32/64 */ #define MIPS_COP_0_USERLOCAL _(4) /* sel 2 is userlevel register */ #define MIPS_COP_0_HWRENA _(7) +#define MIPS_COP_0_INTCTL _(12) #define MIPS_COP_0_DEBUG _(23) #define MIPS_COP_0_DEPC _(24) #define MIPS_COP_0_PERFCNT _(25) @@ -562,6 +564,16 @@ #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ /* + * IntCtl Register Fields + */ +#define MIPS_INTCTL_IPTI_MASK 0xE0000000 /* bits 31..29 timer intr # */ +#define MIPS_INTCTL_IPTI_SHIFT 29 +#define MIPS_INTCTL_IPPCI_MASK 0x1C000000 /* bits 26..29 perf counter intr # */ +#define MIPS_INTCTL_IPPCI_SHIFT 26 +#define MIPS_INTCTL_VS_MASK 0x000001F0 /* bits 5..9 vector spacing */ +#define MIPS_INTCTL_VS_SHIFT 4 + +/* * Config Register Fields * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.39) */ |