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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-10-07 15:10:20 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-01-10 09:53:31 +0100 |
commit | c40e45b75eb76d79a05c7fa85c1fa9b5c728a12f (patch) | |
tree | ad4f2519067709f00ab98b3c591186c26dc3a21f /freebsd/sys/dev/tsec | |
parent | userspace-header-gen.py: Simplify program ports (diff) | |
download | rtems-libbsd-c40e45b75eb76d79a05c7fa85c1fa9b5c728a12f.tar.bz2 |
Update to FreeBSD head 2016-08-23
Git mirror commit 9fe7c416e6abb28b1398fd3e5687099846800cfd.
Diffstat (limited to 'freebsd/sys/dev/tsec')
-rw-r--r-- | freebsd/sys/dev/tsec/if_tsec.c | 62 | ||||
-rw-r--r-- | freebsd/sys/dev/tsec/if_tsec.h | 17 | ||||
-rw-r--r-- | freebsd/sys/dev/tsec/if_tsecreg.h | 13 |
3 files changed, 59 insertions, 33 deletions
diff --git a/freebsd/sys/dev/tsec/if_tsec.c b/freebsd/sys/dev/tsec/if_tsec.c index 45b4716e..5b94af9c 100644 --- a/freebsd/sys/dev/tsec/if_tsec.c +++ b/freebsd/sys/dev/tsec/if_tsec.c @@ -50,6 +50,7 @@ __FBSDID("$FreeBSD$"); #include <net/bpf.h> #include <net/ethernet.h> #include <net/if.h> +#include <net/if_var.h> #include <net/if_arp.h> #include <net/if_dl.h> #include <net/if_media.h> @@ -115,6 +116,8 @@ DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(tsec, ether, 1, 1, 1); MODULE_DEPEND(tsec, miibus, 1, 1, 1); +struct mtx tsec_phy_mtx; + int tsec_attach(struct tsec_softc *sc) { @@ -125,6 +128,10 @@ tsec_attach(struct tsec_softc *sc) int error = 0; int i; + /* Initialize global (because potentially shared) MII lock */ + if (!mtx_initialized(&tsec_phy_mtx)) + mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF); + /* Reset all TSEC counters */ TSEC_TX_RX_COUNTERS_INIT(sc); @@ -251,7 +258,6 @@ tsec_attach(struct tsec_softc *sc) ifp->if_softc = sc; if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); - ifp->if_mtu = ETHERMTU; ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; ifp->if_init = tsec_init; ifp->if_start = tsec_start; @@ -420,21 +426,24 @@ tsec_init_locked(struct tsec_softc *sc) */ TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); + TSEC_PHY_LOCK(sc); + /* Step 6: Reset the management interface */ - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); /* Step 7: Setup the MII Mgmt clock speed */ - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ timeout = TSEC_READ_RETRY; - while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & + while (--timeout && (TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & TSEC_MIIMIND_BUSY)) DELAY(TSEC_READ_DELAY); if (timeout == 0) { if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); return; } + TSEC_PHY_UNLOCK(sc); /* Step 9: Setup the MII Mgmt */ #ifdef __rtems__ @@ -568,7 +577,7 @@ tsec_set_mac_address(struct tsec_softc *sc) TSEC_GLOBAL_LOCK_ASSERT(sc); KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), - ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, + ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN, sizeof(macbuf))); macbufp = (char *)macbuf; @@ -694,7 +703,7 @@ tsec_watchdog(struct tsec_softc *sc) return; ifp = sc->tsec_ifp; - ifp->if_oerrors++; + if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if_printf(ifp, "watchdog timeout\n"); tsec_stop(sc); @@ -1372,7 +1381,7 @@ tsec_receive_intr_locked(struct tsec_softc *sc, int count) if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, &rx_data[i].mbuf, &rx_data[i].paddr)) { - ifp->if_ierrors++; + if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); /* * We ran out of mbufs; didn't consume current * descriptor and have to return it to the queue. @@ -1453,7 +1462,7 @@ tsec_transmit_intr_locked(struct tsec_softc *sc) ifp = sc->tsec_ifp; /* Update collision statistics */ - ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); + if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL)); /* Reset collision counters in hardware */ TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); @@ -1488,7 +1497,7 @@ tsec_transmit_intr_locked(struct tsec_softc *sc) TSEC_FREE_TX_MAP(sc, mapp); m_freem(m0); - ifp->if_opackets++; + if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); send = 1; } bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, @@ -1545,18 +1554,18 @@ tsec_error_intr_locked(struct tsec_softc *sc, int count) /* Check transmitter errors */ if (eflags & TSEC_IEVENT_TXE) { - ifp->if_oerrors++; + if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (eflags & TSEC_IEVENT_LC) - ifp->if_collisions++; + if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); } /* Check receiver errors */ if (eflags & TSEC_IEVENT_BSY) { - ifp->if_ierrors++; - ifp->if_iqdrops++; + if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); + if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); /* Get data from RX buffers */ tsec_receive_intr_locked(sc, count); @@ -1573,10 +1582,10 @@ tsec_error_intr_locked(struct tsec_softc *sc, int count) } if (eflags & TSEC_IEVENT_BABT) - ifp->if_oerrors++; + if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (eflags & TSEC_IEVENT_BABR) - ifp->if_ierrors++; + if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); } void @@ -1594,22 +1603,27 @@ tsec_miibus_readreg(device_t dev, int phy, int reg) { struct tsec_softc *sc; uint32_t timeout; + int rv; sc = device_get_softc(dev); - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg); - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, 0); - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); + TSEC_PHY_LOCK(); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); timeout = TSEC_READ_RETRY; - while (--timeout && TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & + while (--timeout && TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) DELAY(TSEC_READ_DELAY); if (timeout == 0) device_printf(dev, "Timeout while reading from PHY!\n"); - return (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMSTAT)); + rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT); + TSEC_PHY_UNLOCK(); + + return (rv); } int @@ -1620,13 +1634,15 @@ tsec_miibus_writereg(device_t dev, int phy, int reg, int value) sc = device_get_softc(dev); - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg); - TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCON, value); + TSEC_PHY_LOCK(); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); + TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value); timeout = TSEC_READ_RETRY; - while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & + while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & TSEC_MIIMIND_BUSY)) DELAY(TSEC_READ_DELAY); + TSEC_PHY_UNLOCK(); if (timeout == 0) device_printf(dev, "Timeout while writing to PHY!\n"); diff --git a/freebsd/sys/dev/tsec/if_tsec.h b/freebsd/sys/dev/tsec/if_tsec.h index e4bbc9ae..108b0f21 100644 --- a/freebsd/sys/dev/tsec/if_tsec.h +++ b/freebsd/sys/dev/tsec/if_tsec.h @@ -62,12 +62,12 @@ struct tsec_softc { bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ - uint32_t tsec_tx_raddr; /* real adress of TX descriptors */ + uint32_t tsec_tx_raddr; /* real address of TX descriptors */ bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ - uint32_t tsec_rx_raddr; /* real adress of RX descriptors */ + uint32_t tsec_rx_raddr; /* real address of RX descriptors */ bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ @@ -75,7 +75,7 @@ struct tsec_softc { struct rx_data_type { bus_dmamap_t map; /* mbuf map */ struct mbuf *mbuf; - uint32_t paddr; /* DMA addres of buffer */ + uint32_t paddr; /* DMA address of buffer */ } rx_data[TSEC_RX_NUM_DESC]; uint32_t tx_cur_desc_cnt; @@ -135,7 +135,8 @@ struct tsec_softc { struct mbuf *frame; int phyaddr; - struct tsec_softc *phy_sc; + bus_space_tag_t phy_bst; + bus_space_handle_t phy_bsh; }; /* interface to get/put generic objects */ @@ -255,6 +256,14 @@ struct tsec_softc { #define TSEC_WRITE(sc, reg, val) \ bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) +extern struct mtx tsec_phy_mtx; +#define TSEC_PHY_LOCK(sc) mtx_lock(&tsec_phy_mtx) +#define TSEC_PHY_UNLOCK(sc) mtx_unlock(&tsec_phy_mtx) +#define TSEC_PHY_READ(sc, reg) \ + bus_space_read_4((sc)->phy_bst, (sc)->phy_bsh, (reg)) +#define TSEC_PHY_WRITE(sc, reg, val) \ + bus_space_write_4((sc)->phy_bst, (sc)->phy_bsh, (reg), (val)) + /* Lock for transmitter */ #define TSEC_TRANSMIT_LOCK(sc) do { \ mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ diff --git a/freebsd/sys/dev/tsec/if_tsecreg.h b/freebsd/sys/dev/tsec/if_tsecreg.h index 4ba1997e..1994298c 100644 --- a/freebsd/sys/dev/tsec/if_tsecreg.h +++ b/freebsd/sys/dev/tsec/if_tsecreg.h @@ -77,12 +77,13 @@ * register */ #define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */ #define TSEC_REG_MAXFRM 0x510 /* Maximum frame length register */ -#define TSEC_REG_MIIMCFG 0x520 /* MII Management configuration register */ -#define TSEC_REG_MIIMCOM 0x524 /* MII Management command register */ -#define TSEC_REG_MIIMADD 0x528 /* MII Management address register */ -#define TSEC_REG_MIIMCON 0x52c /* MII Management control register */ -#define TSEC_REG_MIIMSTAT 0x530 /* MII Management status register */ -#define TSEC_REG_MIIMIND 0x534 /* MII Management indicator register */ +#define TSEC_REG_MIIBASE 0x520 /* MII Management base, rest offsets */ +#define TSEC_REG_MIIMCFG 0x0 /* MII Management configuration register */ +#define TSEC_REG_MIIMCOM 0x4 /* MII Management command register */ +#define TSEC_REG_MIIMADD 0x8 /* MII Management address register */ +#define TSEC_REG_MIIMCON 0xc /* MII Management control register */ +#define TSEC_REG_MIIMSTAT 0x10 /* MII Management status register */ +#define TSEC_REG_MIIMIND 0x14 /* MII Management indicator register */ #define TSEC_REG_IFSTAT 0x53c /* Interface status register */ #define TSEC_REG_MACSTNADDR1 0x540 /* Station address register, part 1 */ #define TSEC_REG_MACSTNADDR2 0x544 /* Station address register, part 2 */ |