Move files to match FreeBSD layout

8 files changed, 3631 insertions, 0 deletions

diff --git a/freebsd/sys/dev/mii/brgphy.c b/freebsd/sys/dev/mii/brgphy.c
new file mode 100644
index 00000000..9b53c83d
--- /dev/null
+++ b/freebsd/sys/dev/mii/brgphy.c
@@ -0,0 +1,1090 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*-
+ * Copyright (c) 2000
+ *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
+ */
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/kernel.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/socket.h>
+#include <freebsd/sys/bus.h>
+
+#include <freebsd/net/if.h>
+#include <freebsd/net/ethernet.h>
+#include <freebsd/net/if_media.h>
+
+#include <freebsd/dev/mii/mii.h>
+#include <freebsd/dev/mii/miivar.h>
+#include <freebsd/local/miidevs.h>
+
+#include <freebsd/dev/mii/brgphyreg.h>
+#include <freebsd/net/if_arp.h>
+#include <freebsd/machine/bus.h>
+#include <freebsd/dev/bge/if_bgereg.h>
+#include <freebsd/dev/bce/if_bcereg.h>
+
+#include <freebsd/dev/pci/pcireg.h>
+#include <freebsd/dev/pci/pcivar.h>
+
+#include <freebsd/local/miibus_if.h>
+
+static int brgphy_probe(device_t);
+static int brgphy_attach(device_t);
+
+struct brgphy_softc {
+	struct mii_softc mii_sc;
+	int mii_oui;
+	int mii_model;
+	int mii_rev;
+	int serdes_flags;	/* Keeps track of the serdes type used */
+#define BRGPHY_5706S		0x0001
+#define BRGPHY_5708S		0x0002
+#define BRGPHY_NOANWAIT		0x0004
+#define BRGPHY_5709S		0x0008
+	int bce_phy_flags;	/* PHY flags transferred from the MAC driver */
+};
+
+static device_method_t brgphy_methods[] = {
+	/* device interface */
+	DEVMETHOD(device_probe,		brgphy_probe),
+	DEVMETHOD(device_attach,	brgphy_attach),
+	DEVMETHOD(device_detach,	mii_phy_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	{ 0, 0 }
+};
+
+static devclass_t brgphy_devclass;
+
+static driver_t brgphy_driver = {
+	"brgphy",
+	brgphy_methods,
+	sizeof(struct brgphy_softc)
+};
+
+DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
+
+static int	brgphy_service(struct mii_softc *, struct mii_data *, int);
+static void	brgphy_setmedia(struct mii_softc *, int);
+static void	brgphy_status(struct mii_softc *);
+static void	brgphy_mii_phy_auto(struct mii_softc *, int);
+static void	brgphy_reset(struct mii_softc *);
+static void	brgphy_enable_loopback(struct mii_softc *);
+static void	bcm5401_load_dspcode(struct mii_softc *);
+static void	bcm5411_load_dspcode(struct mii_softc *);
+static void	bcm54k2_load_dspcode(struct mii_softc *);
+static void	brgphy_fixup_5704_a0_bug(struct mii_softc *);
+static void	brgphy_fixup_adc_bug(struct mii_softc *);
+static void	brgphy_fixup_adjust_trim(struct mii_softc *);
+static void	brgphy_fixup_ber_bug(struct mii_softc *);
+static void	brgphy_fixup_crc_bug(struct mii_softc *);
+static void	brgphy_fixup_jitter_bug(struct mii_softc *);
+static void	brgphy_ethernet_wirespeed(struct mii_softc *);
+static void	brgphy_jumbo_settings(struct mii_softc *, u_long);
+
+static const struct mii_phydesc brgphys[] = {
+	MII_PHY_DESC(xxBROADCOM, BCM5400),
+	MII_PHY_DESC(xxBROADCOM, BCM5401),
+	MII_PHY_DESC(xxBROADCOM, BCM5411),
+	MII_PHY_DESC(xxBROADCOM, BCM54K2),
+	MII_PHY_DESC(xxBROADCOM, BCM5701),
+	MII_PHY_DESC(xxBROADCOM, BCM5703),
+	MII_PHY_DESC(xxBROADCOM, BCM5704),
+	MII_PHY_DESC(xxBROADCOM, BCM5705),
+	MII_PHY_DESC(xxBROADCOM, BCM5706),
+	MII_PHY_DESC(xxBROADCOM, BCM5714),
+	MII_PHY_DESC(xxBROADCOM, BCM5750),
+	MII_PHY_DESC(xxBROADCOM, BCM5752),
+	MII_PHY_DESC(xxBROADCOM, BCM5754),
+	MII_PHY_DESC(xxBROADCOM, BCM5780),
+	MII_PHY_DESC(xxBROADCOM, BCM5708C),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5755),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5787),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5708S),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709CAX),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5722),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
+	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709S),
+	MII_PHY_DESC(xxBROADCOM_ALT2, BCM5717C),
+	MII_PHY_DESC(BROADCOM2, BCM5906),
+	MII_PHY_END
+};
+
+#define HS21_PRODUCT_ID	"IBM eServer BladeCenter HS21"
+#define HS21_BCM_CHIPID	0x57081021
+
+static int
+detect_hs21(struct bce_softc *bce_sc)
+{
+	char *sysenv;
+	int found;
+
+	found = 0;
+	if (bce_sc->bce_chipid == HS21_BCM_CHIPID) {
+		sysenv = getenv("smbios.system.product");
+		if (sysenv != NULL) {
+			if (strncmp(sysenv, HS21_PRODUCT_ID,
+			    strlen(HS21_PRODUCT_ID)) == 0)
+				found = 1;
+			freeenv(sysenv);
+		}
+	}
+	return (found);
+}
+
+/* Search for our PHY in the list of known PHYs */
+static int
+brgphy_probe(device_t dev)
+{
+
+	return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
+}
+
+/* Attach the PHY to the MII bus */
+static int
+brgphy_attach(device_t dev)
+{
+	struct brgphy_softc *bsc;
+	struct bge_softc *bge_sc = NULL;
+	struct bce_softc *bce_sc = NULL;
+	struct mii_softc *sc;
+	struct mii_attach_args *ma;
+	struct mii_data *mii;
+	struct ifnet *ifp;
+
+	bsc = device_get_softc(dev);
+	sc = &bsc->mii_sc;
+	ma = device_get_ivars(dev);
+	sc->mii_dev = device_get_parent(dev);
+	mii = ma->mii_data;
+	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
+
+	/* Initialize mii_softc structure */
+	sc->mii_flags = miibus_get_flags(dev);
+	sc->mii_inst = mii->mii_instance++;
+	sc->mii_phy = ma->mii_phyno;
+	sc->mii_service = brgphy_service;
+	sc->mii_pdata = mii;
+
+	/*
+	 * At least some variants wedge when isolating, at least some also
+	 * don't support loopback.
+	 */
+	sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE;
+
+	/* Initialize brgphy_softc structure */
+	bsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+	bsc->mii_model = MII_MODEL(ma->mii_id2);
+	bsc->mii_rev = MII_REV(ma->mii_id2);
+	bsc->serdes_flags = 0;
+
+	if (bootverbose)
+		device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
+		    bsc->mii_oui, bsc->mii_model, bsc->mii_rev);
+
+	/* Handle any special cases based on the PHY ID */
+	switch (bsc->mii_oui) {
+	case MII_OUI_BROADCOM:
+	case MII_OUI_BROADCOM2:
+		break;
+	case MII_OUI_xxBROADCOM:
+		switch (bsc->mii_model) {
+		case MII_MODEL_xxBROADCOM_BCM5706:
+		case MII_MODEL_xxBROADCOM_BCM5714:
+			/*
+			 * The 5464 PHY used in the 5706 supports both copper
+			 * and fiber interfaces over GMII.  Need to check the
+			 * shadow registers to see which mode is actually
+			 * in effect, and therefore whether we have 5706C or
+			 * 5706S.
+			 */
+			PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
+				BRGPHY_SHADOW_1C_MODE_CTRL);
+			if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
+				BRGPHY_SHADOW_1C_ENA_1000X) {
+				bsc->serdes_flags |= BRGPHY_5706S;
+				sc->mii_flags |= MIIF_HAVEFIBER;
+			}
+			break;
+		} break;
+	case MII_OUI_xxBROADCOM_ALT1:
+		switch (bsc->mii_model) {
+		case MII_MODEL_xxBROADCOM_ALT1_BCM5708S:
+			bsc->serdes_flags |= BRGPHY_5708S;
+			sc->mii_flags |= MIIF_HAVEFIBER;
+			break;
+		case MII_MODEL_xxBROADCOM_ALT1_BCM5709S:
+			bsc->serdes_flags |= BRGPHY_5709S;
+			sc->mii_flags |= MIIF_HAVEFIBER;
+			break;
+		}
+		break;
+	case MII_OUI_xxBROADCOM_ALT2:
+		/* No special handling yet. */
+		break;
+	default:
+		device_printf(dev, "Unrecognized OUI for PHY!\n");
+	}
+
+	ifp = sc->mii_pdata->mii_ifp;
+
+	/* Find the MAC driver associated with this PHY. */
+	if (strcmp(ifp->if_dname, "bge") == 0)	{
+		bge_sc = ifp->if_softc;
+	} else if (strcmp(ifp->if_dname, "bce") == 0) {
+		bce_sc = ifp->if_softc;
+	}
+
+	brgphy_reset(sc);
+
+	/* Read the PHY's capabilities. */
+	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+	if (sc->mii_capabilities & BMSR_EXTSTAT)
+		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
+	device_printf(dev, " ");
+
+#define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
+
+	/* Add the supported media types */
+	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+		mii_phy_add_media(sc);
+		printf("\n");
+	} else {
+		sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
+			BRGPHY_S1000 | BRGPHY_BMCR_FDX);
+		printf("1000baseSX-FDX, ");
+		/* 2.5G support is a software enabled feature on the 5708S and 5709S. */
+		if (bce_sc && (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, sc->mii_inst), 0);
+			printf("2500baseSX-FDX, ");
+		} else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
+		    (detect_hs21(bce_sc) != 0)) {
+			/*
+			 * There appears to be certain silicon revision
+			 * in IBM HS21 blades that is having issues with
+			 * this driver wating for the auto-negotiation to
+			 * complete. This happens with a specific chip id
+			 * only and when the 1000baseSX-FDX is the only
+			 * mode. Workaround this issue since it's unlikely
+			 * to be ever addressed.
+			 */
+			printf("auto-neg workaround, ");
+			bsc->serdes_flags |= BRGPHY_NOANWAIT;
+		}
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
+		printf("auto\n");
+	}
+
+#undef ADD
+	MIIBUS_MEDIAINIT(sc->mii_dev);
+	return (0);
+}
+
+static int
+brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int val;
+
+	switch (cmd) {
+	case MII_POLLSTAT:
+		break;
+	case MII_MEDIACHG:
+		/* If the interface is not up, don't do anything. */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			break;
+
+		/* Todo: Why is this here?  Is it really needed? */
+		brgphy_reset(sc);	/* XXX hardware bug work-around */
+
+		switch (IFM_SUBTYPE(ife->ifm_media)) {
+		case IFM_AUTO:
+			brgphy_mii_phy_auto(sc, ife->ifm_media);
+			break;
+		case IFM_2500_SX:
+		case IFM_1000_SX:
+		case IFM_1000_T:
+		case IFM_100_TX:
+		case IFM_10_T:
+			brgphy_setmedia(sc, ife->ifm_media);
+			break;
+		default:
+			return (EINVAL);
+		}
+		break;
+	case MII_TICK:
+		/* Bail if the interface isn't up. */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			return (0);
+
+
+		/* Bail if autoneg isn't in process. */
+		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+			sc->mii_ticks = 0;
+			break;
+		}
+
+		/*
+		 * Check to see if we have link.  If we do, we don't
+		 * need to restart the autonegotiation process.
+		 */
+		val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
+		if (val & BMSR_LINK) {
+			sc->mii_ticks = 0;	/* Reset autoneg timer. */
+			break;
+		}
+
+		/* Announce link loss right after it happens. */
+		if (sc->mii_ticks++ == 0)
+			break;
+
+		/* Only retry autonegotiation every mii_anegticks seconds. */
+		if (sc->mii_ticks <= sc->mii_anegticks)
+			break;
+
+
+		/* Retry autonegotiation */
+		sc->mii_ticks = 0;
+		brgphy_mii_phy_auto(sc, ife->ifm_media);
+		break;
+	}
+
+	/* Update the media status. */
+	brgphy_status(sc);
+
+	/*
+	 * Callback if something changed. Note that we need to poke
+	 * the DSP on the Broadcom PHYs if the media changes.
+	 */
+	if (sc->mii_media_active != mii->mii_media_active ||
+	    sc->mii_media_status != mii->mii_media_status ||
+	    cmd == MII_MEDIACHG) {
+		switch (bsc->mii_oui) {
+		case MII_OUI_BROADCOM:
+			break;
+		case MII_OUI_xxBROADCOM:
+			switch (bsc->mii_model) {
+			case MII_MODEL_xxBROADCOM_BCM5400:
+				bcm5401_load_dspcode(sc);
+				break;
+			case MII_MODEL_xxBROADCOM_BCM5401:
+				if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
+					bcm5401_load_dspcode(sc);
+				break;
+			case MII_MODEL_xxBROADCOM_BCM5411:
+				bcm5411_load_dspcode(sc);
+				break;
+			case MII_MODEL_xxBROADCOM_BCM54K2:
+				bcm54k2_load_dspcode(sc);
+				break;
+			}
+			break;
+		case MII_OUI_xxBROADCOM_ALT1:
+			break;
+		}
+	}
+	mii_phy_update(sc, cmd);
+	return (0);
+}
+
+/****************************************************************************/
+/* Sets the PHY link speed.                                                 */
+/*                                                                          */
+/* Returns:                                                                 */
+/*   None                                                                   */
+/****************************************************************************/
+static void
+brgphy_setmedia(struct mii_softc *sc, int media)
+{
+	int bmcr = 0, gig;
+
+	switch (IFM_SUBTYPE(media)) {
+	case IFM_2500_SX:
+		break;
+	case IFM_1000_SX:
+	case IFM_1000_T:
+		bmcr = BRGPHY_S1000;
+		break;
+	case IFM_100_TX:
+		bmcr = BRGPHY_S100;
+		break;
+	case IFM_10_T:
+	default:
+		bmcr = BRGPHY_S10;
+		break;
+	}
+
+	if ((media & IFM_GMASK) == IFM_FDX) {
+		bmcr |= BRGPHY_BMCR_FDX;
+		gig = BRGPHY_1000CTL_AFD;
+	} else {
+		gig = BRGPHY_1000CTL_AHD;
+	}
+
+	/* Force loopback to disconnect PHY from Ethernet medium. */
+	brgphy_enable_loopback(sc);
+
+	PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
+	PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
+
+	if (IFM_SUBTYPE(media) != IFM_1000_T &&
+	    IFM_SUBTYPE(media) != IFM_1000_SX) {
+		PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
+		return;
+	}
+
+	if (IFM_SUBTYPE(media) == IFM_1000_T) {
+		gig |= BRGPHY_1000CTL_MSE;
+		if ((media & IFM_ETH_MASTER) != 0 ||
+		    (sc->mii_pdata->mii_ifp->if_flags & IFF_LINK0) != 0)
+			gig |= BRGPHY_1000CTL_MSC;
+	}
+	PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
+	PHY_WRITE(sc, BRGPHY_MII_BMCR,
+	    bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
+}
+
+/****************************************************************************/
+/* Set the media status based on the PHY settings.                          */
+/*                                                                          */
+/* Returns:                                                                 */
+/*   None                                                                   */
+/****************************************************************************/
+static void
+brgphy_status(struct mii_softc *sc)
+{
+	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
+	struct mii_data *mii = sc->mii_pdata;
+	int aux, bmcr, bmsr, val, xstat;
+	u_int flowstat;
+
+	mii->mii_media_status = IFM_AVALID;
+	mii->mii_media_active = IFM_ETHER;
+
+	bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
+	bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
+
+	if (bmcr & BRGPHY_BMCR_LOOP) {
+		mii->mii_media_active |= IFM_LOOP;
+	}
+
+	if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
+	    (bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
+	    (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
+		/* Erg, still trying, I guess... */
+		mii->mii_media_active |= IFM_NONE;
+		return;
+	}
+
+	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+		/*
+		 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
+		 * wedges at least the PHY of BCM5704 (but not others).
+		 */
+		flowstat = mii_phy_flowstatus(sc);
+		xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
+		aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
+
+		/* If copper link is up, get the negotiated speed/duplex. */
+		if (aux & BRGPHY_AUXSTS_LINK) {
+			mii->mii_media_status |= IFM_ACTIVE;
+			switch (aux & BRGPHY_AUXSTS_AN_RES) {
+			case BRGPHY_RES_1000FD:
+				mii->mii_media_active |= IFM_1000_T | IFM_FDX; 	break;
+			case BRGPHY_RES_1000HD:
+				mii->mii_media_active |= IFM_1000_T | IFM_HDX; 	break;
+			case BRGPHY_RES_100FD:
+				mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
+			case BRGPHY_RES_100T4:
+				mii->mii_media_active |= IFM_100_T4; break;
+			case BRGPHY_RES_100HD:
+				mii->mii_media_active |= IFM_100_TX | IFM_HDX; 	break;
+			case BRGPHY_RES_10FD:
+				mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
+			case BRGPHY_RES_10HD:
+				mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
+			default:
+				mii->mii_media_active |= IFM_NONE; break;
+			}
+
+			if ((mii->mii_media_active & IFM_FDX) != 0)
+				mii->mii_media_active |= flowstat;
+
+			if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
+			    (xstat & BRGPHY_1000STS_MSR) != 0)
+				mii->mii_media_active |= IFM_ETH_MASTER;
+		}
+	} else {
+		/* Todo: Add support for flow control. */
+		/* If serdes link is up, get the negotiated speed/duplex. */
+		if (bmsr & BRGPHY_BMSR_LINK) {
+			mii->mii_media_status |= IFM_ACTIVE;
+		}
+
+		/* Check the link speed/duplex based on the PHY type. */
+		if (bsc->serdes_flags & BRGPHY_5706S) {
+			mii->mii_media_active |= IFM_1000_SX;
+
+			/* If autoneg enabled, read negotiated duplex settings */
+			if (bmcr & BRGPHY_BMCR_AUTOEN) {
+				val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
+				if (val & BRGPHY_SERDES_ANAR_FDX)
+					mii->mii_media_active |= IFM_FDX;
+				else
+					mii->mii_media_active |= IFM_HDX;
+			}
+		} else if (bsc->serdes_flags & BRGPHY_5708S) {
+			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
+			xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
+
+			/* Check for MRBE auto-negotiated speed results. */
+			switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
+			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
+				mii->mii_media_active |= IFM_10_FL; break;
+			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
+				mii->mii_media_active |= IFM_100_FX; break;
+			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
+				mii->mii_media_active |= IFM_1000_SX; break;
+			case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
+				mii->mii_media_active |= IFM_2500_SX; break;
+			}
+
+			/* Check for MRBE auto-negotiated duplex results. */
+			if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
+				mii->mii_media_active |= IFM_FDX;
+			else
+				mii->mii_media_active |= IFM_HDX;
+		} else if (bsc->serdes_flags & BRGPHY_5709S) {
+			/* Select GP Status Block of the AN MMD, get autoneg results. */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
+			xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
+
+			/* Restore IEEE0 block (assumed in all brgphy(4) code). */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
+
+			/* Check for MRBE auto-negotiated speed results. */
+			switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
+				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
+					mii->mii_media_active |= IFM_10_FL; break;
+				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
+					mii->mii_media_active |= IFM_100_FX; break;
+				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
+					mii->mii_media_active |= IFM_1000_SX; break;
+				case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
+					mii->mii_media_active |= IFM_2500_SX; break;
+			}
+
+			/* Check for MRBE auto-negotiated duplex results. */
+			if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
+				mii->mii_media_active |= IFM_FDX;
+			else
+				mii->mii_media_active |= IFM_HDX;
+		}
+	}
+}
+
+static void
+brgphy_mii_phy_auto(struct mii_softc *sc, int media)
+{
+	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
+	int anar, ktcr = 0;
+
+	brgphy_reset(sc);
+
+	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+		anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
+		if ((media & IFM_FLOW) != 0 ||
+		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
+			anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
+		PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
+	} else {
+		anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
+		if ((media & IFM_FLOW) != 0 ||
+		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
+			anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
+		PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
+	}
+
+	ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
+	if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
+		ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
+	PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
+	ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
+
+	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
+	    BRGPHY_BMCR_STARTNEG);
+	PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
+}
+
+/* Enable loopback to force the link down. */
+static void
+brgphy_enable_loopback(struct mii_softc *sc)
+{
+	int i;
+
+	PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
+	for (i = 0; i < 15000; i++) {
+		if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
+			break;
+		DELAY(10);
+	}
+}
+
+/* Turn off tap power management on 5401. */
+static void
+bcm5401_load_dspcode(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ BRGPHY_MII_AUXCTL,		0x0c20 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x0012 },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x1804 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x0013 },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x1204 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x0132 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x8006 },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x0232 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x0a20 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+	DELAY(40);
+}
+
+static void
+bcm5411_load_dspcode(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ 0x1c,				0x8c23 },
+		{ 0x1c,				0x8ca3 },
+		{ 0x1c,				0x8c23 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+void
+bcm54k2_load_dspcode(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ 4,				0x01e1 },
+		{ 9,				0x0300 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+
+}
+
+static void
+brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ 0x1c,				0x8d68 },
+		{ 0x1c,				0x8d68 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+static void
+brgphy_fixup_adc_bug(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ BRGPHY_MII_AUXCTL,		0x0c00 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x2aaa },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+static void
+brgphy_fixup_adjust_trim(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ BRGPHY_MII_AUXCTL,		0x0c00 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x110b },
+		{ BRGPHY_MII_TEST1,			0x0014 },
+		{ BRGPHY_MII_AUXCTL,		0x0400 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+static void
+brgphy_fixup_ber_bug(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ BRGPHY_MII_AUXCTL,		0x0c00 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x310b },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x201f },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x9506 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x401f },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x14e2 },
+		{ BRGPHY_MII_AUXCTL,		0x0400 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+static void
+brgphy_fixup_crc_bug(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ BRGPHY_MII_DSP_RW_PORT,	0x0a75 },
+		{ 0x1c,				0x8c68 },
+		{ 0x1c,				0x8d68 },
+		{ 0x1c,				0x8c68 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+static void
+brgphy_fixup_jitter_bug(struct mii_softc *sc)
+{
+	static const struct {
+		int		reg;
+		uint16_t	val;
+	} dspcode[] = {
+		{ BRGPHY_MII_AUXCTL,		0x0c00 },
+		{ BRGPHY_MII_DSP_ADDR_REG,	0x000a },
+		{ BRGPHY_MII_DSP_RW_PORT,	0x010b },
+		{ BRGPHY_MII_AUXCTL,		0x0400 },
+		{ 0,				0 },
+	};
+	int i;
+
+	for (i = 0; dspcode[i].reg != 0; i++)
+		PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
+}
+
+static void
+brgphy_fixup_disable_early_dac(struct mii_softc *sc)
+{
+	uint32_t val;
+
+	PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
+	val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
+	val &= ~(1 << 8);
+	PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
+
+}
+
+static void
+brgphy_ethernet_wirespeed(struct mii_softc *sc)
+{
+	uint32_t	val;
+
+	/* Enable Ethernet@WireSpeed. */
+	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
+	val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
+	PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
+}
+
+static void
+brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
+{
+	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
+	uint32_t	val;
+
+	/* Set or clear jumbo frame settings in the PHY. */
+	if (mtu > ETHER_MAX_LEN) {
+		if (bsc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
+			/* BCM5401 PHY cannot read-modify-write. */
+			PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
+		} else {
+			PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
+			val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
+			PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
+			    val | BRGPHY_AUXCTL_LONG_PKT);
+		}
+
+		val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
+		PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
+		    val | BRGPHY_PHY_EXTCTL_HIGH_LA);
+	} else {
+		PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
+		val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
+		PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
+		    val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
+
+		val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
+		PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
+			val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
+	}
+}
+
+static void
+brgphy_reset(struct mii_softc *sc)
+{
+	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
+	struct bge_softc *bge_sc = NULL;
+	struct bce_softc *bce_sc = NULL;
+	struct ifnet *ifp;
+	int val;
+
+	/* Perform a standard PHY reset. */
+	mii_phy_reset(sc);
+
+	/* Handle any PHY specific procedures following the reset. */
+	switch (bsc->mii_oui) {
+	case MII_OUI_BROADCOM:
+		break;
+	case MII_OUI_xxBROADCOM:
+		switch (bsc->mii_model) {
+		case MII_MODEL_xxBROADCOM_BCM5400:
+			bcm5401_load_dspcode(sc);
+			break;
+		case MII_MODEL_xxBROADCOM_BCM5401:
+			if (bsc->mii_rev == 1 || bsc->mii_rev == 3)
+				bcm5401_load_dspcode(sc);
+			break;
+		case MII_MODEL_xxBROADCOM_BCM5411:
+			bcm5411_load_dspcode(sc);
+			break;
+		case MII_MODEL_xxBROADCOM_BCM54K2:
+			bcm54k2_load_dspcode(sc);
+			break;
+		}
+		break;
+	case MII_OUI_xxBROADCOM_ALT1:
+	case MII_OUI_xxBROADCOM_ALT2:
+		break;
+	}
+
+	ifp = sc->mii_pdata->mii_ifp;
+
+	/* Find the driver associated with this PHY. */
+	if (strcmp(ifp->if_dname, "bge") == 0)	{
+		bge_sc = ifp->if_softc;
+	} else if (strcmp(ifp->if_dname, "bce") == 0) {
+		bce_sc = ifp->if_softc;
+	}
+
+	if (bge_sc) {
+		/* Fix up various bugs */
+		if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
+			brgphy_fixup_5704_a0_bug(sc);
+		if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
+			brgphy_fixup_adc_bug(sc);
+		if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
+			brgphy_fixup_adjust_trim(sc);
+		if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
+			brgphy_fixup_ber_bug(sc);
+		if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
+			brgphy_fixup_crc_bug(sc);
+		if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
+			brgphy_fixup_jitter_bug(sc);
+
+		brgphy_jumbo_settings(sc, ifp->if_mtu);
+
+		if (bge_sc->bge_phy_flags & BGE_PHY_WIRESPEED)
+			brgphy_ethernet_wirespeed(sc);
+
+		/* Enable Link LED on Dell boxes */
+		if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
+			PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
+			    PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
+			    ~BRGPHY_PHY_EXTCTL_3_LED);
+		}
+
+		/* Adjust output voltage (From Linux driver) */
+		if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
+			PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
+	} else if (bce_sc) {
+		if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
+			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
+
+			/* Store autoneg capabilities/results in digital block (Page 0) */
+			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
+			PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
+				BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
+			PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
+
+			/* Enable fiber mode and autodetection */
+			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
+				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
+				BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
+				BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
+
+			/* Enable parallel detection */
+			PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
+				PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
+				BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
+
+			/* Advertise 2.5G support through next page during autoneg */
+			if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
+				PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
+					PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
+					BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
+
+			/* Increase TX signal amplitude */
+			if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
+			    (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
+			    (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
+				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
+					BRGPHY_5708S_TX_MISC_PG5);
+				PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
+					PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
+				PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
+					BRGPHY_5708S_DIG_PG0);
+			}
+
+			/* Backplanes use special driver/pre-driver/pre-emphasis values. */
+			if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
+				(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
+					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
+						BRGPHY_5708S_TX_MISC_PG5);
+					PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
+						bce_sc->bce_port_hw_cfg &
+						BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
+					PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
+						BRGPHY_5708S_DIG_PG0);
+			}
+		} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
+			(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
+
+			/* Select the SerDes Digital block of the AN MMD. */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
+			val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
+			val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
+			val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
+			PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
+
+			/* Select the Over 1G block of the AN MMD. */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
+
+			/* Enable autoneg "Next Page" to advertise 2.5G support. */
+			val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
+			if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
+				val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
+			else
+				val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
+			PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
+
+			/* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
+
+			/* Enable MRBE speed autoneg. */
+			val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
+			val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
+			    BRGPHY_MRBE_MSG_PG5_NP_T2;
+			PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
+
+			/* Select the Clause 73 User B0 block of the AN MMD. */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
+
+			/* Enable MRBE speed autoneg. */
+			PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
+			    BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
+			    BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
+			    BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
+
+			/* Restore IEEE0 block (assumed in all brgphy(4) code). */
+			PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
+        } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
+			if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
+				(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
+				brgphy_fixup_disable_early_dac(sc);
+
+			brgphy_jumbo_settings(sc, ifp->if_mtu);
+			brgphy_ethernet_wirespeed(sc);
+		} else {
+			brgphy_fixup_ber_bug(sc);
+			brgphy_jumbo_settings(sc, ifp->if_mtu);
+			brgphy_ethernet_wirespeed(sc);
+		}
+	}
+}
diff --git a/freebsd/sys/dev/mii/brgphyreg.h b/freebsd/sys/dev/mii/brgphyreg.h
new file mode 100644
index 00000000..fb8b65a5
--- /dev/null
+++ b/freebsd/sys/dev/mii/brgphyreg.h
@@ -0,0 +1,420 @@
+/*-
+ * Copyright (c) 2000
+ *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_MII_BRGPHYREG_HH_
+#define	_DEV_MII_BRGPHYREG_HH_
+
+/*
+ * Broadcom BCM5400 registers
+ */
+
+#define	BRGPHY_MII_BMCR		0x00
+#define	BRGPHY_BMCR_RESET	0x8000
+#define	BRGPHY_BMCR_LOOP	0x4000
+#define	BRGPHY_BMCR_SPD0	0x2000	/* Speed select, lower bit */
+#define	BRGPHY_BMCR_AUTOEN	0x1000	/* Autoneg enabled */
+#define	BRGPHY_BMCR_PDOWN	0x0800	/* Power down */
+#define	BRGPHY_BMCR_ISO		0x0400	/* Isolate */
+#define	BRGPHY_BMCR_STARTNEG	0x0200	/* Restart autoneg */
+#define	BRGPHY_BMCR_FDX		0x0100	/* Duplex mode */
+#define	BRGPHY_BMCR_CTEST	0x0080	/* Collision test enable */
+#define	BRGPHY_BMCR_SPD1	0x0040	/* Speed select, upper bit */
+
+#define	BRGPHY_S1000		BRGPHY_BMCR_SPD1	/* 1000mbps */
+#define	BRGPHY_S100		BRGPHY_BMCR_SPD0	/* 100mpbs */
+#define	BRGPHY_S10		0			/* 10mbps */
+
+#define	BRGPHY_MII_BMSR		0x01
+#define	BRGPHY_BMSR_EXTSTS	0x0100	/* Extended status present */
+#define	BRGPHY_BMSR_PRESUB	0x0040	/* Preamble surpression */
+#define	BRGPHY_BMSR_ACOMP	0x0020	/* Autoneg complete */
+#define	BRGPHY_BMSR_RFAULT	0x0010	/* Remote fault condition occured */
+#define	BRGPHY_BMSR_ANEG	0x0008	/* Autoneg capable */
+#define	BRGPHY_BMSR_LINK	0x0004	/* Link status */
+#define	BRGPHY_BMSR_JABBER	0x0002	/* Jabber detected */
+#define	BRGPHY_BMSR_EXT		0x0001	/* Extended capability */
+
+#define	BRGPHY_MII_ANAR		0x04
+#define	BRGPHY_ANAR_NP		0x8000	/* Next page */
+#define	BRGPHY_ANAR_RF		0x2000	/* Remote fault */
+#define	BRGPHY_ANAR_ASP		0x0800	/* Asymmetric Pause */
+#define	BRGPHY_ANAR_PC		0x0400	/* Pause capable */
+#define	BRGPHY_ANAR_SEL		0x001F	/* Selector field, 00001=Ethernet */
+
+#define	BRGPHY_MII_ANLPAR	0x05
+#define	BRGPHY_ANLPAR_NP	0x8000	/* Next page */
+#define	BRGPHY_ANLPAR_RF	0x2000	/* Remote fault */
+#define	BRGPHY_ANLPAR_ASP	0x0800	/* Asymmetric Pause */
+#define	BRGPHY_ANLPAR_PC	0x0400	/* Pause capable */
+#define	BRGPHY_ANLPAR_SEL	0x001F	/* Selector field, 00001=Ethernet */
+
+#define	BRGPHY_SEL_TYPE		0x0001	/* Ethernet */
+
+#define	BRGPHY_MII_ANER		0x06
+#define	BRGPHY_ANER_PDF		0x0010	/* Parallel detection fault */
+#define	BRGPHY_ANER_LPNP	0x0008	/* Link partner can next page */
+#define	BRGPHY_ANER_NP		0x0004	/* Local PHY can next page */
+#define	BRGPHY_ANER_RX		0x0002	/* Next page received */
+#define	BRGPHY_ANER_LPAN	0x0001 	/* Link partner autoneg capable */
+
+#define	BRGPHY_MII_NEXTP	0x07	/* Next page */
+
+#define	BRGPHY_MII_NEXTP_LP	0x08	/* Next page of link partner */
+
+#define	BRGPHY_MII_1000CTL	0x09	/* 1000baseT control */
+#define	BRGPHY_1000CTL_TST	0xE000	/* Test modes */
+#define	BRGPHY_1000CTL_MSE	0x1000	/* Master/Slave enable */
+#define	BRGPHY_1000CTL_MSC	0x0800	/* Master/Slave configuration */
+#define	BRGPHY_1000CTL_RD	0x0400	/* Repeater/DTE */
+#define	BRGPHY_1000CTL_AFD	0x0200	/* Advertise full duplex */
+#define	BRGPHY_1000CTL_AHD	0x0100	/* Advertise half duplex */
+
+#define	BRGPHY_MII_1000STS	0x0A	/* 1000baseT status */
+#define	BRGPHY_1000STS_MSF	0x8000	/* Master/slave fault */
+#define	BRGPHY_1000STS_MSR	0x4000	/* Master/slave result */
+#define	BRGPHY_1000STS_LRS	0x2000	/* Local receiver status */
+#define	BRGPHY_1000STS_RRS	0x1000	/* Remote receiver status */
+#define	BRGPHY_1000STS_LPFD	0x0800	/* Link partner can FD */
+#define	BRGPHY_1000STS_LPHD	0x0400	/* Link partner can HD */
+#define	BRGPHY_1000STS_IEC	0x00FF	/* Idle error count */
+
+#define	BRGPHY_MII_EXTSTS	0x0F	/* Extended status */
+#define	BRGPHY_EXTSTS_X_FD_CAP	0x8000	/* 1000base-X FD capable */
+#define	BRGPHY_EXTSTS_X_HD_CAP	0x4000	/* 1000base-X HD capable */
+#define	BRGPHY_EXTSTS_T_FD_CAP	0x2000	/* 1000base-T FD capable */
+#define	BRGPHY_EXTSTS_T_HD_CAP	0x1000	/* 1000base-T HD capable */
+
+#define	BRGPHY_MII_PHY_EXTCTL	0x10	/* PHY extended control */
+#define	BRGPHY_PHY_EXTCTL_MAC_PHY	0x8000	/* 10BIT/GMI-interface */
+#define	BRGPHY_PHY_EXTCTL_DIS_CROSS	0x4000	/* Disable MDI crossover */
+#define	BRGPHY_PHY_EXTCTL_TX_DIS	0x2000	/* TX output disabled */
+#define	BRGPHY_PHY_EXTCTL_INT_DIS	0x1000	/* Interrupts disabled */
+#define	BRGPHY_PHY_EXTCTL_F_INT		0x0800	/* Force interrupt */
+#define	BRGPHY_PHY_EXTCTL_BY_45		0x0400	/* Bypass 4B5B-Decoder */
+#define	BRGPHY_PHY_EXTCTL_BY_SCR	0x0200	/* Bypass scrambler */
+#define	BRGPHY_PHY_EXTCTL_BY_MLT3	0x0100	/* Bypass MLT3 encoder */
+#define	BRGPHY_PHY_EXTCTL_BY_RXA	0x0080	/* Bypass RX alignment */
+#define	BRGPHY_PHY_EXTCTL_RES_SCR	0x0040	/* Reset scrambler */
+#define	BRGPHY_PHY_EXTCTL_EN_LTR	0x0020	/* Enable LED traffic mode */
+#define	BRGPHY_PHY_EXTCTL_LED_ON	0x0010	/* Force LEDs on */
+#define	BRGPHY_PHY_EXTCTL_LED_OFF	0x0008	/* Force LEDs off */
+#define	BRGPHY_PHY_EXTCTL_EX_IPG	0x0004	/* Extended TX IPG mode */
+#define	BRGPHY_PHY_EXTCTL_3_LED		0x0002	/* Three link LED mode */
+#define	BRGPHY_PHY_EXTCTL_HIGH_LA	0x0001	/* GMII Fifo Elasticy (?) */
+
+#define	BRGPHY_MII_PHY_EXTSTS	0x11	/* PHY extended status */
+#define	BRGPHY_PHY_EXTSTS_CROSS_STAT	0x2000	/* MDI crossover status */
+#define	BRGPHY_PHY_EXTSTS_INT_STAT	0x1000	/* Interrupt status */
+#define	BRGPHY_PHY_EXTSTS_RRS		0x0800	/* Remote receiver status */
+#define	BRGPHY_PHY_EXTSTS_LRS		0x0400	/* Local receiver status */
+#define	BRGPHY_PHY_EXTSTS_LOCKED	0x0200	/* Locked */
+#define	BRGPHY_PHY_EXTSTS_LS		0x0100	/* Link status */
+#define	BRGPHY_PHY_EXTSTS_RF		0x0080	/* Remove fault */
+#define	BRGPHY_PHY_EXTSTS_CE_ER		0x0040	/* Carrier ext error */
+#define	BRGPHY_PHY_EXTSTS_BAD_SSD	0x0020	/* Bad SSD */
+#define	BRGPHY_PHY_EXTSTS_BAD_ESD	0x0010	/* Bad ESS */
+#define	BRGPHY_PHY_EXTSTS_RX_ER		0x0008	/* RX error */
+#define	BRGPHY_PHY_EXTSTS_TX_ER		0x0004	/* TX error */
+#define	BRGPHY_PHY_EXTSTS_LOCK_ER	0x0002	/* Lock error */
+#define	BRGPHY_PHY_EXTSTS_MLT3_ER	0x0001	/* MLT3 code error */
+
+#define	BRGPHY_MII_RXERRCNT	0x12	/* RX error counter */
+
+#define	BRGPHY_MII_FCERRCNT	0x13	/* False carrier sense counter */
+#define	BGRPHY_FCERRCNT		0x00FF	/* False carrier counter */
+
+#define	BRGPHY_MII_RXNOCNT	0x14	/* RX not OK counter */
+#define	BRGPHY_RXNOCNT_LOCAL	0xFF00	/* Local RX not OK counter */
+#define	BRGPHY_RXNOCNT_REMOTE	0x00FF	/* Local RX not OK counter */
+
+#define	BRGPHY_MII_DSP_RW_PORT	0x15	/* DSP coefficient r/w port */
+
+#define	BRGPHY_MII_DSP_ADDR_REG	0x17	/* DSP coefficient addr register */
+#define	BRGPHY_MII_EPHY_PTEST	0x17	/* 5906 PHY register */
+
+#define	BRGPHY_DSP_TAP_NUMBER_MASK		0x00
+#define	BRGPHY_DSP_AGC_A			0x00
+#define	BRGPHY_DSP_AGC_B			0x01
+#define	BRGPHY_DSP_MSE_PAIR_STATUS		0x02
+#define	BRGPHY_DSP_SOFT_DECISION		0x03
+#define	BRGPHY_DSP_PHASE_REG			0x04
+#define	BRGPHY_DSP_SKEW				0x05
+#define	BRGPHY_DSP_POWER_SAVER_UPPER_BOUND	0x06
+#define	BRGPHY_DSP_POWER_SAVER_LOWER_BOUND	0x07
+#define	BRGPHY_DSP_LAST_ECHO			0x08
+#define	BRGPHY_DSP_FREQUENCY			0x09
+#define	BRGPHY_DSP_PLL_BANDWIDTH		0x0A
+#define	BRGPHY_DSP_PLL_PHASE_OFFSET		0x0B
+
+#define	BRGPHYDSP_FILTER_DCOFFSET		0x0C00
+#define	BRGPHY_DSP_FILTER_FEXT3			0x0B00
+#define	BRGPHY_DSP_FILTER_FEXT2			0x0A00
+#define	BRGPHY_DSP_FILTER_FEXT1			0x0900
+#define	BRGPHY_DSP_FILTER_FEXT0			0x0800
+#define	BRGPHY_DSP_FILTER_NEXT3			0x0700
+#define	BRGPHY_DSP_FILTER_NEXT2			0x0600
+#define	BRGPHY_DSP_FILTER_NEXT1			0x0500
+#define	BRGPHY_DSP_FILTER_NEXT0			0x0400
+#define	BRGPHY_DSP_FILTER_ECHO			0x0300
+#define	BRGPHY_DSP_FILTER_DFE			0x0200
+#define	BRGPHY_DSP_FILTER_FFE			0x0100
+
+#define	BRGPHY_DSP_CONTROL_ALL_FILTERS		0x1000
+
+#define	BRGPHY_DSP_SEL_CH_0			0x0000
+#define	BRGPHY_DSP_SEL_CH_1			0x2000
+#define	BRGPHY_DSP_SEL_CH_2			0x4000
+#define	BRGPHY_DSP_SEL_CH_3			0x6000
+
+#define	BRGPHY_MII_AUXCTL	0x18	/* AUX control */
+#define	BRGPHY_AUXCTL_LOW_SQ	0x8000	/* Low squelch */
+#define	BRGPHY_AUXCTL_LONG_PKT	0x4000	/* RX long packets */
+#define	BRGPHY_AUXCTL_ER_CTL	0x3000	/* Edgerate control */
+#define	BRGPHY_AUXCTL_TX_TST	0x0400	/* TX test, always 1 */
+#define	BRGPHY_AUXCTL_DIS_PRF	0x0080	/* dis part resp filter */
+#define	BRGPHY_AUXCTL_DIAG_MODE	0x0004	/* Diagnostic mode */
+
+#define	BRGPHY_MII_AUXSTS	0x19	/* AUX status */
+#define	BRGPHY_AUXSTS_ACOMP	0x8000	/* Autoneg complete */
+#define	BRGPHY_AUXSTS_AN_ACK	0x4000	/* Autoneg complete ack */
+#define	BRGPHY_AUXSTS_AN_ACK_D	0x2000	/* Autoneg complete ack detect */
+#define	BRGPHY_AUXSTS_AN_NPW	0x1000	/* Autoneg next page wait */
+#define	BRGPHY_AUXSTS_AN_RES	0x0700	/* Autoneg HCD */
+#define	BRGPHY_AUXSTS_PDF	0x0080	/* Parallel detect. fault */
+#define	BRGPHY_AUXSTS_RF	0x0040	/* Remote fault */
+#define	BRGPHY_AUXSTS_ANP_R	0x0020	/* Autoneg page received */
+#define	BRGPHY_AUXSTS_LP_ANAB	0x0010	/* Link partner autoneg ability */
+#define	BRGPHY_AUXSTS_LP_NPAB	0x0008	/* Link partner next page ability */
+#define	BRGPHY_AUXSTS_LINK	0x0004	/* Link status */
+#define	BRGPHY_AUXSTS_PRR	0x0002	/* Pause resolution-RX */
+#define	BRGPHY_AUXSTS_PRT	0x0001	/* Pause resolution-TX */
+
+#define	BRGPHY_RES_1000FD	0x0700	/* 1000baseT full duplex */
+#define	BRGPHY_RES_1000HD	0x0600	/* 1000baseT half duplex */
+#define	BRGPHY_RES_100FD	0x0500	/* 100baseT full duplex */
+#define	BRGPHY_RES_100T4	0x0400	/* 100baseT4 */
+#define	BRGPHY_RES_100HD	0x0300	/* 100baseT half duplex */
+#define	BRGPHY_RES_10FD		0x0200	/* 10baseT full duplex */
+#define	BRGPHY_RES_10HD		0x0100	/* 10baseT half duplex */
+
+#define	BRGPHY_MII_ISR		0x1A	/* Interrupt status */
+#define	BRGPHY_ISR_PSERR	0x4000	/* Pair swap error */
+#define	BRGPHY_ISR_MDXI_SC	0x2000	/* MDIX Status Change */
+#define	BRGPHY_ISR_HCT		0x1000	/* Counter above 32K */
+#define	BRGPHY_ISR_LCT		0x0800	/* All counter below 128 */
+#define	BRGPHY_ISR_AN_PR	0x0400	/* Autoneg page received */
+#define	BRGPHY_ISR_NO_HDCL	0x0200	/* No HCD Link */
+#define	BRGPHY_ISR_NO_HDC	0x0100	/* No HCD */
+#define	BRGPHY_ISR_USHDC	0x0080	/* Negotiated Unsupported HCD */
+#define	BRGPHY_ISR_SCR_S_ERR	0x0040	/* Scrambler sync error */
+#define	BRGPHY_ISR_RRS_CHG	0x0020	/* Remote RX status change */
+#define	BRGPHY_ISR_LRS_CHG	0x0010	/* Local RX status change */
+#define	BRGPHY_ISR_DUP_CHG	0x0008	/* Duplex mode change */
+#define	BRGPHY_ISR_LSP_CHG	0x0004	/* Link speed changed */
+#define	BRGPHY_ISR_LNK_CHG	0x0002	/* Link status change */
+#define	BRGPHY_ISR_CRCERR	0x0001	/* CRC error */
+
+#define	BRGPHY_MII_IMR		0x1B	/* Interrupt mask */
+#define	BRGPHY_IMR_PSERR	0x4000	/* Pair swap error */
+#define	BRGPHY_IMR_MDXI_SC	0x2000	/* MDIX Status Change */
+#define	BRGPHY_IMR_HCT		0x1000	/* Counter above 32K */
+#define	BRGPHY_IMR_LCT		0x0800	/* All counter below 128 */
+#define	BRGPHY_IMR_AN_PR	0x0400	/* Autoneg page received */
+#define	BRGPHY_IMR_NO_HDCL	0x0200	/* No HCD Link */
+#define	BRGPHY_IMR_NO_HDC	0x0100	/* No HCD */
+#define	BRGPHY_IMR_USHDC	0x0080	/* Negotiated Unsupported HCD */
+#define	BRGPHY_IMR_SCR_S_ERR	0x0040	/* Scrambler sync error */
+#define	BRGPHY_IMR_RRS_CHG	0x0020	/* Remote RX status change */
+#define	BRGPHY_IMR_LRS_CHG	0x0010	/* Local RX status change */
+#define	BRGPHY_IMR_DUP_CHG	0x0008	/* Duplex mode change */
+#define	BRGPHY_IMR_LSP_CHG	0x0004	/* Link speed changed */
+#define	BRGPHY_IMR_LNK_CHG	0x0002	/* Link status change */
+#define	BRGPHY_IMR_CRCERR	0x0001	/* CRC error */
+
+/*******************************************************/
+/* Begin: Shared SerDes PHY register definitions       */
+/*******************************************************/
+
+/* SerDes autoneg is different from copper */
+#define	BRGPHY_SERDES_ANAR		0x04
+#define	BRGPHY_SERDES_ANAR_FDX		0x0020
+#define	BRGPHY_SERDES_ANAR_HDX		0x0040
+#define	BRGPHY_SERDES_ANAR_NO_PAUSE	(0x0 << 7)
+#define	BRGPHY_SERDES_ANAR_SYM_PAUSE	(0x1 << 7)
+#define	BRGPHY_SERDES_ANAR_ASYM_PAUSE	(0x2 << 7)
+#define	BRGPHY_SERDES_ANAR_BOTH_PAUSE	(0x3 << 7)
+
+#define	BRGPHY_SERDES_ANLPAR		0x05
+#define	BRGPHY_SERDES_ANLPAR_FDX	0x0020
+#define	BRGPHY_SERDES_ANLPAR_HDX	0x0040
+#define	BRGPHY_SERDES_ANLPAR_NO_PAUSE	(0x0 << 7)
+#define	BRGPHY_SERDES_ANLPAR_SYM_PAUSE	(0x1 << 7)
+#define	BRGPHY_SERDES_ANLPAR_ASYM_PAUSE	(0x2 << 7)
+#define	BRGPHY_SERDES_ANLPAR_BOTH_PAUSE	(0x3 << 7)
+
+/*******************************************************/
+/* End: Shared SerDes PHY register definitions         */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5706 PHY         */
+/*******************************************************/
+
+/* 
+ * Shadow register 0x1C, bit 15 is write enable,
+ * bits 14-10 select function (0x00 to 0x1F).
+ */
+#define	BRGPHY_MII_SHADOW_1C		0x1C
+#define	BRGPHY_SHADOW_1C_WRITE_EN	0x8000
+#define	BRGPHY_SHADOW_1C_SELECT_MASK	0x7C00
+
+/* Shadow 0x1C Mode Control Register (select value 0x1F) */
+#define	BRGPHY_SHADOW_1C_MODE_CTRL	(0x1F << 10)
+/* When set, Regs 0-0x0F are 1000X, else 1000T */
+#define	BRGPHY_SHADOW_1C_ENA_1000X	0x0001	
+
+#define	BRGPHY_MII_TEST1		0x1E
+#define	BRGPHY_TEST1_TRIM_EN		0x0010
+#define	BRGPHY_TEST1_CRC_EN		0x8000
+
+#define	BRGPHY_MII_TEST2		0x1F
+
+/*******************************************************/
+/* End: PHY register values for the 5706 PHY           */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
+
+/* Autoneg Next Page Transmit 1 Regiser */
+#define	BRGPHY_5708S_ANEG_NXT_PG_XMIT1		0x0B
+#define	BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G	0x0001
+
+/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
+#define	BRGPHY_5708S_BLOCK_ADDR			0x1f
+#define	BRGPHY_5708S_DIG_PG0			0x0000
+#define	BRGPHY_5708S_DIG3_PG2			0x0002
+#define	BRGPHY_5708S_TX_MISC_PG5		0x0005
+
+/* 5708S SerDes "Digital" Registers (page 0) */
+#define	BRGPHY_5708S_PG0_1000X_CTL1		0x10
+#define	BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN	0x0010
+#define	BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE	0x0001
+
+#define	BRGPHY_5708S_PG0_1000X_STAT1		0x14
+#define	BRGPHY_5708S_PG0_1000X_STAT1_LINK	0x0002
+#define	BRGPHY_5708S_PG0_1000X_STAT1_FDX	0x0004
+#define	BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK	0x0018
+#define	BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10	(0x0 << 3)
+#define	BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100	(0x1 << 3)
+#define	BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G	(0x2 << 3)
+#define	BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G	(0x3 << 3)
+
+
+#define	BRGPHY_5708S_PG0_1000X_CTL2		0x11
+#define	BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN	0x0001
+
+/* 5708S SerDes "Digital 3" Registers (page 2) */
+#define	BRGPHY_5708S_PG2_DIGCTL_3_0		0x10
+#define	BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE	0x0001
+
+/* 5708S SerDes "TX Misc" Registers (page 5) */
+#define	BRGPHY_5708S_PG5_2500STATUS1		0x10
+#define	BRGPHY_5708S_PG5_TXACTL1		0x15
+#define	BRGPHY_5708S_PG5_TXACTL3		0x17
+
+/*******************************************************/
+/* End: PHY register values for the 5708S SerDes PHY   */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5709S SerDes PHY */
+/*******************************************************/
+
+/* 5709S SerDes "General Purpose Status" Registers */
+#define	BRGPHY_BLOCK_ADDR_GP_STATUS		0x8120
+#define	BRGPHY_GP_STATUS_TOP_ANEG_STATUS	0x1B
+#define	BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK	0x3F00
+#define	BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10	0x0000
+#define	BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100	0x0100
+#define	BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G	0x0200
+#define	BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G	0x0300
+#define	BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1GKX	0x0D00
+#define	BRGPHY_GP_STATUS_TOP_ANEG_FDX		0x0008
+#define	BRGPHY_GP_STATUS_TOP_ANEG_LINK_UP	0x0004
+#define	BRGPHY_GP_STATUS_TOP_ANEG_CL73_COMP	0x0001
+
+/* 5709S SerDes "SerDes Digital" Registers */
+#define	BRGPHY_BLOCK_ADDR_SERDES_DIG		0x8300
+#define	BRGPHY_SERDES_DIG_1000X_CTL1		0x0010
+#define	BRGPHY_SD_DIG_1000X_CTL1_AUTODET	0x0010
+#define	BRGPHY_SD_DIG_1000X_CTL1_FIBER		0x0001
+
+/* 5709S SerDes "Over 1G" Registers */
+#define	BRGPHY_BLOCK_ADDR_OVER_1G		0x8320
+#define	BRGPHY_OVER_1G_UNFORMAT_PG1		0x19
+
+/* 5709S SerDes "Multi-Rate Backplane Ethernet" Registers */
+#define	BRGPHY_BLOCK_ADDR_MRBE			0x8350
+#define	BRGPHY_MRBE_MSG_PG5_NP			0x10
+#define	BRGPHY_MRBE_MSG_PG5_NP_MBRE		0x0001
+#define	BRGPHY_MRBE_MSG_PG5_NP_T2		0x0002
+
+/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
+#define	BRGPHY_BLOCK_ADDR_CL73_USER_B0		0x8370
+#define	BRGPHY_CL73_USER_B0_MBRE_CTL1		0x12
+#define	BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP	0x2000
+#define	BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR	0x4000
+#define	BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG	0x8000
+
+/* 5709S SerDes "IEEE Clause 73 User B0" Registers */
+#define	BRGPHY_BLOCK_ADDR_ADDR_EXT		0xFFD0
+
+/* 5709S SerDes "Combo IEEE 0" Registers */
+#define	BRGPHY_BLOCK_ADDR_COMBO_IEEE0		0xFFE0
+
+#define	BRGPHY_ADDR_EXT				0x1E
+#define	BRGPHY_BLOCK_ADDR			0x1F
+
+#define	BRGPHY_ADDR_EXT_AN_MMD			0x3800
+
+/*******************************************************/
+/* End: PHY register values for the 5709S SerDes PHY   */
+/*******************************************************/
+
+#define	BRGPHY_INTRS	\
+	~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG)
+
+#endif /* _DEV_BRGPHY_MIIREG_HH_ */
diff --git a/freebsd/sys/dev/mii/icsphy.c b/freebsd/sys/dev/mii/icsphy.c
new file mode 100644
index 00000000..a034eb36
--- /dev/null
+++ b/freebsd/sys/dev/mii/icsphy.c
@@ -0,0 +1,277 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*	$NetBSD: icsphy.c,v 1.41 2006/11/16 21:24:07 christos Exp $	*/
+
+/*-
+ * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * driver for Integrated Circuit Systems' ICS1889-1893 ethernet 10/100 PHY
+ * datasheet from www.icst.com
+ */
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/kernel.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/socket.h>
+#include <freebsd/sys/bus.h>
+
+#include <freebsd/net/if.h>
+#include <freebsd/net/if_media.h>
+
+#include <freebsd/dev/mii/mii.h>
+#include <freebsd/dev/mii/miivar.h>
+#include <freebsd/local/miidevs.h>
+
+#include <freebsd/dev/mii/icsphyreg.h>
+
+#include <freebsd/local/miibus_if.h>
+
+static int	icsphy_probe(device_t dev);
+static int	icsphy_attach(device_t dev);
+
+struct icsphy_softc {
+	struct mii_softc mii_sc;
+	int mii_model;
+};
+
+static device_method_t icsphy_methods[] = {
+	/* device interface */
+	DEVMETHOD(device_probe,		icsphy_probe),
+	DEVMETHOD(device_attach,	icsphy_attach),
+	DEVMETHOD(device_detach,	mii_phy_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+	{ 0, 0 }
+};
+
+static devclass_t icsphy_devclass;
+
+static driver_t icsphy_driver = {
+	"icsphy",
+	icsphy_methods,
+	sizeof(struct icsphy_softc)
+};
+
+DRIVER_MODULE(icsphy, miibus, icsphy_driver, icsphy_devclass, 0, 0);
+
+static int	icsphy_service(struct mii_softc *, struct mii_data *, int);
+static void	icsphy_status(struct mii_softc *);
+static void	icsphy_reset(struct mii_softc *);
+
+static const struct mii_phydesc icsphys[] = {
+	MII_PHY_DESC(xxICS, 1889),
+	MII_PHY_DESC(xxICS, 1890),
+	MII_PHY_DESC(xxICS, 1892),
+	MII_PHY_DESC(xxICS, 1893),
+	MII_PHY_END
+};
+
+static int
+icsphy_probe(device_t dev)
+{
+
+	return (mii_phy_dev_probe(dev, icsphys, BUS_PROBE_DEFAULT));
+}
+
+static int
+icsphy_attach(device_t dev)
+{
+	struct icsphy_softc *isc;
+	struct mii_softc *sc;
+	struct mii_attach_args *ma;
+	struct mii_data *mii;
+
+	isc = device_get_softc(dev);
+	sc = &isc->mii_sc;
+	ma = device_get_ivars(dev);
+	sc->mii_dev = device_get_parent(dev);
+	mii = ma->mii_data;
+	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
+
+	sc->mii_flags = miibus_get_flags(dev);
+	sc->mii_inst = mii->mii_instance++;
+	sc->mii_phy = ma->mii_phyno;
+	sc->mii_service = icsphy_service;
+	sc->mii_pdata = mii;
+
+	sc->mii_flags |= MIIF_NOISOLATE;
+
+	ifmedia_add(&mii->mii_media,
+	    IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
+	    MII_MEDIA_100_TX, NULL);
+
+	isc->mii_model = MII_MODEL(ma->mii_id2);
+	icsphy_reset(sc);
+
+	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+	device_printf(dev, " ");
+	mii_phy_add_media(sc);
+	printf("\n");
+
+	MIIBUS_MEDIAINIT(sc->mii_dev);
+
+	return (0);
+}
+
+static int
+icsphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
+
+	switch (cmd) {
+	case MII_POLLSTAT:
+		break;
+
+	case MII_MEDIACHG:
+		/*
+		 * If the interface is not up, don't do anything.
+		 */
+		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+			break;
+
+		mii_phy_setmedia(sc);
+		break;
+
+	case MII_TICK:
+		if (mii_phy_tick(sc) == EJUSTRETURN)
+			return (0);
+		break;
+	}
+
+	/* Update the media status. */
+	icsphy_status(sc);
+
+	/* Callback if something changed. */
+	mii_phy_update(sc, cmd);
+	return (0);
+}
+
+static void
+icsphy_status(struct mii_softc *sc)
+{
+	struct mii_data *mii = sc->mii_pdata;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int bmcr, qpr;
+
+	mii->mii_media_status = IFM_AVALID;
+	mii->mii_media_active = IFM_ETHER;
+
+	/*
+	 * Don't get link from the BMSR.  It's available in the QPR,
+	 * and we have to read it twice to unlatch it anyhow.  This
+	 * gives us fewer register reads.
+	 */
+	qpr = PHY_READ(sc, MII_ICSPHY_QPR);		/* unlatch */
+	qpr = PHY_READ(sc, MII_ICSPHY_QPR);		/* real value */
+
+	if (qpr & QPR_LINK)
+		mii->mii_media_status |= IFM_ACTIVE;
+
+	bmcr = PHY_READ(sc, MII_BMCR);
+	if (bmcr & BMCR_ISO) {
+		mii->mii_media_active |= IFM_NONE;
+		mii->mii_media_status = 0;
+		return;
+	}
+
+	if (bmcr & BMCR_LOOP)
+		mii->mii_media_active |= IFM_LOOP;
+
+	if (bmcr & BMCR_AUTOEN) {
+		if ((qpr & QPR_ACOMP) == 0) {
+			/* Erg, still trying, I guess... */
+			mii->mii_media_active |= IFM_NONE;
+			return;
+		}
+		if (qpr & QPR_SPEED)
+			mii->mii_media_active |= IFM_100_TX;
+		else
+			mii->mii_media_active |= IFM_10_T;
+		if (qpr & QPR_FDX)
+			mii->mii_media_active |= IFM_FDX;
+		else
+			mii->mii_media_active |= IFM_HDX;
+	} else
+		mii->mii_media_active = ife->ifm_media;
+}
+
+static void
+icsphy_reset(struct mii_softc *sc)
+{
+	struct icsphy_softc *isc = (struct icsphy_softc *)sc;
+
+	mii_phy_reset(sc);
+	/* set powerdown feature */
+	switch (isc->mii_model) {
+		case MII_MODEL_xxICS_1890:
+		case MII_MODEL_xxICS_1893:
+			PHY_WRITE(sc, MII_ICSPHY_ECR2, ECR2_100AUTOPWRDN);
+			break;
+		case MII_MODEL_xxICS_1892:
+			PHY_WRITE(sc, MII_ICSPHY_ECR2,
+			    ECR2_10AUTOPWRDN|ECR2_100AUTOPWRDN);
+			break;
+		default:
+			/* 1889 have no ECR2 */
+			break;
+	}
+	/*
+	 * There is no description that the reset do auto-negotiation in the
+	 * data sheet.
+	 */
+	PHY_WRITE(sc, MII_BMCR, BMCR_S100|BMCR_STARTNEG|BMCR_FDX);
+}
diff --git a/freebsd/sys/dev/mii/icsphyreg.h b/freebsd/sys/dev/mii/icsphyreg.h
new file mode 100644
index 00000000..a5754b7d
--- /dev/null
+++ b/freebsd/sys/dev/mii/icsphyreg.h
@@ -0,0 +1,129 @@
+/*	$NetBSD: icsphyreg.h,v 1.2 2003/07/01 22:46:08 msaitoh Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_MII_ICSPHYREG_HH_
+#define	_DEV_MII_ICSPHYREG_HH_
+
+/*
+ * ICS1890 registers.
+ *	http://www.icst.com/pdf/18??.pdf
+ */
+
+/* HEX				1889	1890	1892	1893
+ *--------------------------------------------------------------
+ *  0 Control			*	*	*	*
+ *  1 Status			*	*	*	*
+ *  2 PHY Identifier		*	*	*	*
+ *  3 PHY Identifier		*	*	*	*
+ *  4 Auto-Neg. Advertisement		*	*	*
+ *  5 Auto-Neg. Link Parent Adv		*	*	*
+ *  6 Auto-Neg. Expansion		*	*	*
+ *  7 Auto-Neg. Next Page Tx			*	*
+ *  8 ANg Nxt Page Lnk Parnt Abl		*	*
+ * 10 Extended Control		*	*	*	*
+ * 11 Quick Poll Status		*	*	*	*
+ * 12 10Base-T Operation		*	*	*
+ * 13 Extended Control2			*	*	*
+ */
+
+#define	MII_ICSPHY_ECR		0x10	/* Extended Control Register */
+#define	ECR_OVR			0x8000	/* disable command reg overwrites */
+#define	ECR_PHYADDR_MASK	0x07c0	/* PHY address mask */
+#define	ECR_CTEST		0x0020	/* Stream Cipher Test Mode */
+#define	ECR_IECT		0x0004	/* Invalid Error Code Test */
+#define	ECR_SSD			0x0001	/* Stream Cipher Disable */
+
+#define	MII_ICSPHY_QPR		0x11	/* Quick Poll Register */
+#define	QPR_SPEED		0x8000	/* 100Mbps */
+#define	QPR_FDX			0x4000	/* Full dupled */
+#define	QPR_ANB2		0x2000	/* Autoneg monitor bit 2 */
+#define	QPR_ANB1		0x1000	/* Autoneg monitor bit 1 */
+#define	QPR_ANB0		0x0800	/* Autoneg monitor bit 0 */
+#define	QPR_RXERR		0x0400	/* Receive signal lost */
+#define	QPR_PLLERR		0x0200	/* PLL error */
+#define	QPR_FCARR		0x0100	/* False carrier detected */
+#define	QPR_INVALSYM		0x0080	/* Invalid Symbol Detected */
+#define	QPR_HALT		0x0040	/* Halt Symbol Detected */
+#define	QPR_PREEM		0x0020	/* Two Idle Symbols together */
+#define	QPR_ACOMP		0x0010	/* Autonegotiation complete */
+#define	QPR_SDETECT		0x0008	/* signal detect */
+#define	QPR_JABBER		0x0004	/* Jabber detected */
+#define	QPR_RFAULT		0x0002	/* Remote Fault */
+#define	QPR_LINK		0x0001	/* Link */
+
+#define	MII_ICSPHY_TTR		0x12	/* 10baseT Operations Register */
+#define	TTR_RJABBER		0x8000	/* Remote Jabber */
+#define	TTR_POLARITY		0x4000	/* Polarity Reversed */
+#define	TTR_NOJABBER		0x0020	/* Disable Jabber Check */
+#define	TTR_LOOP		0x0010	/* Loopback mode */
+#define	TTR_NOAPOLARITY		0x0008	/* Disable auto polarity correction */
+#define	TTR_NOSQE		0x0004	/* Disable SQE check */
+#define	TTR_NOLINK		0x0002	/* Disable Link check */
+#define	TTR_NOSQUELCH		0x0001	/* Disable squelch */
+
+
+/*
+ * Extended Control Register 2
+ *
+ * HEX					1889	1890	1892	1893
+ *-------------------------------------------------------------------
+ * 8000	Node/Repeater Mode			*	*	*
+ * 4000 Hardware/Software Mode			*	*	*
+ * 2000 Link Partner Support Remote Flt		*
+ * 2000 Remote Fault					*	*
+ * 1000
+ * 0800
+ * 0400 Xmitted Remote Fault status		*
+ * 0200
+ * 0100
+ * 0080 Tri-state Enable					*
+ * 0040
+ * 0020
+ * 0010 A-N Powerup Remote Flt			*
+ * 0008
+ * 0004
+ * 0002 Automatic 10Base-T Power Down			*
+ * 0001 Automatic 100Base-TX Power Down		*	*	*
+ */
+
+#define	MII_ICSPHY_ECR2		0x13	/* Extended Control Register 2 */
+#define	ECR2_REPEATER		0x8000	/* Repeater Mode */
+#define	ECR2_HWSW		0x4000	/* hw/sw config priority */
+#define	ECR2_LPRF		0x2000	/* link partner supports rem fault */
+#define	ECR2_FORCERF		0x0400	/* Force transmit of rem fault */
+#define	ECR2_RFPUP		0x0010	/* A-N Powerup Remote fault */
+#define	ECR2_10AUTOPWRDN	0x0002	/* Automatic 10baseT power down */
+#define	ECR2_100AUTOPWRDN	0x0001	/* Automatic 100baseTX power down */
+
+#endif /* _DEV_MII_ICSPHYREG_HH_ */
diff --git a/freebsd/sys/dev/mii/mii.c b/freebsd/sys/dev/mii/mii.c
new file mode 100644
index 00000000..c5aebad6
--- /dev/null
+++ b/freebsd/sys/dev/mii/mii.c
@@ -0,0 +1,576 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*	$NetBSD: mii.c,v 1.12 1999/08/03 19:41:49 drochner Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * MII bus layer, glues MII-capable network interface drivers to sharable
+ * PHY drivers.  This exports an interface compatible with BSD/OS 3.0's,
+ * plus some NetBSD extensions.
+ */
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/socket.h>
+#include <freebsd/sys/malloc.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/bus.h> 
+
+#include <freebsd/net/if.h>
+#include <freebsd/net/if_media.h>
+#include <freebsd/net/route.h>
+
+#include <freebsd/dev/mii/mii.h>
+#include <freebsd/dev/mii/miivar.h>
+
+MODULE_VERSION(miibus, 1);
+
+#include <freebsd/local/miibus_if.h>
+
+static int miibus_print_child(device_t dev, device_t child);
+static int miibus_read_ivar(device_t dev, device_t child, int which,
+    uintptr_t *result);
+static int miibus_child_location_str(device_t bus, device_t child, char *buf,
+    size_t buflen);
+static int miibus_child_pnpinfo_str(device_t bus, device_t child, char *buf,
+    size_t buflen);
+static int miibus_readreg(device_t, int, int);
+static int miibus_writereg(device_t, int, int, int);
+static void miibus_statchg(device_t);
+static void miibus_linkchg(device_t);
+static void miibus_mediainit(device_t);
+
+static device_method_t miibus_methods[] = {
+	/* device interface */
+	DEVMETHOD(device_probe,		miibus_probe),
+	DEVMETHOD(device_attach,	miibus_attach),
+	DEVMETHOD(device_detach,	miibus_detach),
+	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
+
+	/* bus interface */
+	DEVMETHOD(bus_print_child,	miibus_print_child),
+	DEVMETHOD(bus_read_ivar,	miibus_read_ivar),
+	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
+	DEVMETHOD(bus_child_pnpinfo_str, miibus_child_pnpinfo_str),
+	DEVMETHOD(bus_child_location_str, miibus_child_location_str),
+
+	/* MII interface */
+	DEVMETHOD(miibus_readreg,	miibus_readreg),
+	DEVMETHOD(miibus_writereg,	miibus_writereg),
+	DEVMETHOD(miibus_statchg,	miibus_statchg),    
+	DEVMETHOD(miibus_linkchg,	miibus_linkchg),    
+	DEVMETHOD(miibus_mediainit,	miibus_mediainit),    
+
+	{ 0, 0 }
+};
+
+devclass_t miibus_devclass;
+
+driver_t miibus_driver = {
+	"miibus",
+	miibus_methods,
+	sizeof(struct mii_data)
+};
+
+struct miibus_ivars {
+	struct ifnet	*ifp;
+	ifm_change_cb_t	ifmedia_upd;
+	ifm_stat_cb_t	ifmedia_sts;
+	int		mii_flags;
+};
+
+int
+miibus_probe(device_t dev)
+{
+
+	device_set_desc(dev, "MII bus");
+
+	return (BUS_PROBE_SPECIFIC);
+}
+
+int
+miibus_attach(device_t dev)
+{
+	struct miibus_ivars	*ivars;
+	struct mii_attach_args	*ma;
+	struct mii_data		*mii;
+	device_t		*children;
+	int			i, nchildren;
+
+	mii = device_get_softc(dev);
+	nchildren = 0;
+	if (device_get_children(dev, &children, &nchildren) == 0) {
+		for (i = 0; i < nchildren; i++) {
+			ma = device_get_ivars(children[i]);
+			ma->mii_data = mii;
+		}
+		free(children, M_TEMP);
+	}
+	if (nchildren == 0) {
+		device_printf(dev, "cannot get children\n");
+		return (ENXIO);
+	}
+	ivars = device_get_ivars(dev);
+	ifmedia_init(&mii->mii_media, IFM_IMASK, ivars->ifmedia_upd,
+	    ivars->ifmedia_sts);
+	mii->mii_ifp = ivars->ifp;
+	mii->mii_ifp->if_capabilities |= IFCAP_LINKSTATE;
+	mii->mii_ifp->if_capenable |= IFCAP_LINKSTATE;
+	LIST_INIT(&mii->mii_phys);
+
+	return (bus_generic_attach(dev));
+}
+
+int
+miibus_detach(device_t dev)
+{
+	struct mii_data		*mii;
+
+	bus_generic_detach(dev);
+	mii = device_get_softc(dev);
+	ifmedia_removeall(&mii->mii_media);
+	mii->mii_ifp = NULL;
+
+	return (0);
+}
+
+static int
+miibus_print_child(device_t dev, device_t child)
+{
+	struct mii_attach_args *ma;
+	int retval;
+
+	ma = device_get_ivars(child);
+	retval = bus_print_child_header(dev, child);
+	retval += printf(" PHY %d", ma->mii_phyno);
+	retval += bus_print_child_footer(dev, child);
+
+	return (retval);
+}
+
+static int
+miibus_read_ivar(device_t dev, device_t child __unused, int which,
+    uintptr_t *result)
+{
+	struct miibus_ivars *ivars;
+
+	/*
+	 * NB: this uses the instance variables of the miibus rather than
+	 * its PHY children.
+	 */
+	ivars = device_get_ivars(dev);
+	switch (which) {
+	case MIIBUS_IVAR_FLAGS:
+		*result = ivars->mii_flags;
+		break;
+	default:
+		return (ENOENT);
+	}
+	return (0);
+}
+
+static int
+miibus_child_pnpinfo_str(device_t bus __unused, device_t child, char *buf,
+    size_t buflen)
+{
+	struct mii_attach_args *ma;
+
+	ma = device_get_ivars(child);
+	snprintf(buf, buflen, "oui=0x%x model=0x%x rev=0x%x",
+	    MII_OUI(ma->mii_id1, ma->mii_id2),
+	    MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
+	return (0);
+}
+
+static int
+miibus_child_location_str(device_t bus __unused, device_t child, char *buf,
+    size_t buflen)
+{
+	struct mii_attach_args *ma;
+
+	ma = device_get_ivars(child);
+	snprintf(buf, buflen, "phyno=%d", ma->mii_phyno);
+	return (0);
+}
+
+static int
+miibus_readreg(device_t dev, int phy, int reg)
+{
+	device_t		parent;
+
+	parent = device_get_parent(dev);
+	return (MIIBUS_READREG(parent, phy, reg));
+}
+
+static int
+miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+	device_t		parent;
+
+	parent = device_get_parent(dev);
+	return (MIIBUS_WRITEREG(parent, phy, reg, data));
+}
+
+static void
+miibus_statchg(device_t dev)
+{
+	device_t		parent;
+	struct mii_data		*mii;
+	struct ifnet		*ifp;
+
+	parent = device_get_parent(dev);
+	MIIBUS_STATCHG(parent);
+
+	mii = device_get_softc(dev);
+
+	/*
+	 * Note that each NIC's softc must start with an ifnet pointer.
+	 * XXX: EVIL HACK!
+	 */
+	ifp = *(struct ifnet **)device_get_softc(parent);
+	ifp->if_baudrate = ifmedia_baudrate(mii->mii_media_active);
+}
+
+static void
+miibus_linkchg(device_t dev)
+{
+	struct mii_data		*mii;
+	device_t		parent;
+	int			link_state;
+
+	parent = device_get_parent(dev);
+	MIIBUS_LINKCHG(parent);
+
+	mii = device_get_softc(dev);
+	
+	if (mii->mii_media_status & IFM_AVALID) {
+		if (mii->mii_media_status & IFM_ACTIVE)
+			link_state = LINK_STATE_UP;
+		else
+			link_state = LINK_STATE_DOWN;
+	} else
+		link_state = LINK_STATE_UNKNOWN;
+	/*
+	 * Note that each NIC's softc must start with an ifnet pointer.
+	 * XXX: EVIL HACK!
+	 */
+	if_link_state_change(*(struct ifnet**)device_get_softc(parent), link_state);
+}
+
+static void
+miibus_mediainit(device_t dev)
+{
+	struct mii_data		*mii;
+	struct ifmedia_entry	*m;
+	int			media = 0;
+
+	/* Poke the parent in case it has any media of its own to add. */
+	MIIBUS_MEDIAINIT(device_get_parent(dev));
+
+	mii = device_get_softc(dev);
+	LIST_FOREACH(m, &mii->mii_media.ifm_list, ifm_list) {
+		media = m->ifm_media;
+		if (media == (IFM_ETHER | IFM_AUTO))
+			break;
+	}
+
+	ifmedia_set(&mii->mii_media, media);
+}
+
+/*
+ * Helper function used by network interface drivers, attaches the miibus and
+ * the PHYs to the network interface driver parent.
+ */
+int
+mii_attach(device_t dev, device_t *miibus, struct ifnet *ifp,
+    ifm_change_cb_t ifmedia_upd, ifm_stat_cb_t ifmedia_sts, int capmask,
+    int phyloc, int offloc, int flags)
+{
+	struct miibus_ivars *ivars;
+	struct mii_attach_args ma, *args;
+	device_t *children, phy;
+	int bmsr, first, i, nchildren, offset, phymax, phymin, rv;
+
+	if (phyloc != MII_PHY_ANY && offloc != MII_OFFSET_ANY) {
+		printf("%s: phyloc and offloc specified\n", __func__);
+		return (EINVAL);
+	}
+
+	if (offloc != MII_OFFSET_ANY && (offloc < 0 || offloc >= MII_NPHY)) {
+		printf("%s: ivalid offloc %d\n", __func__, offloc);
+		return (EINVAL);
+	}
+
+	if (phyloc == MII_PHY_ANY) {
+		phymin = 0;
+		phymax = MII_NPHY - 1;
+	} else {
+		if (phyloc < 0 || phyloc >= MII_NPHY) {
+			printf("%s: ivalid phyloc %d\n", __func__, phyloc);
+			return (EINVAL);
+		}
+		phymin = phymax = phyloc;
+	}
+
+	first = 0;
+	if (*miibus == NULL) {
+		first = 1;
+		ivars = malloc(sizeof(*ivars), M_DEVBUF, M_NOWAIT);
+		if (ivars == NULL)
+			return (ENOMEM);
+		ivars->ifp = ifp;
+		ivars->ifmedia_upd = ifmedia_upd;
+		ivars->ifmedia_sts = ifmedia_sts;
+		ivars->mii_flags = flags;
+		*miibus = device_add_child(dev, "miibus", -1);
+		if (*miibus == NULL) {
+			rv = ENXIO;
+			goto fail;
+		}
+		device_set_ivars(*miibus, ivars);
+	} else {
+		ivars = device_get_ivars(*miibus);
+		if (ivars->ifp != ifp || ivars->ifmedia_upd != ifmedia_upd ||
+		    ivars->ifmedia_sts != ifmedia_sts ||
+		    ivars->mii_flags != flags) {
+			printf("%s: non-matching invariant\n", __func__);
+			return (EINVAL);
+		}
+		/*
+		 * Assignment of the attach arguments mii_data for the first
+		 * pass is done in miibus_attach(), i.e. once the miibus softc
+		 * has been allocated.
+		 */
+		ma.mii_data = device_get_softc(*miibus);
+	} 
+
+	ma.mii_capmask = capmask;
+
+	phy = NULL;
+	offset = 0;
+	for (ma.mii_phyno = phymin; ma.mii_phyno <= phymax; ma.mii_phyno++) {
+		/*
+		 * Make sure we haven't already configured a PHY at this
+		 * address.  This allows mii_attach() to be called
+		 * multiple times.
+		 */
+		if (device_get_children(*miibus, &children, &nchildren) == 0) {
+			for (i = 0; i < nchildren; i++) {
+				args = device_get_ivars(children[i]);
+				if (args->mii_phyno == ma.mii_phyno) {
+					/*
+					 * Yes, there is already something
+					 * configured at this address.
+					 */
+					free(children, M_TEMP);
+					goto skip;
+				}
+			}
+			free(children, M_TEMP);
+		}
+
+		/*
+		 * Check to see if there is a PHY at this address.  Note,
+		 * many braindead PHYs report 0/0 in their ID registers,
+		 * so we test for media in the BMSR.
+	 	 */
+		bmsr = MIIBUS_READREG(dev, ma.mii_phyno, MII_BMSR);
+		if (bmsr == 0 || bmsr == 0xffff ||
+		    (bmsr & (BMSR_EXTSTAT | BMSR_MEDIAMASK)) == 0) {
+			/* Assume no PHY at this address. */
+			continue;
+		}
+
+		/*
+		 * There is a PHY at this address.  If we were given an
+		 * `offset' locator, skip this PHY if it doesn't match.
+		 */
+		if (offloc != MII_OFFSET_ANY && offloc != offset)
+			goto skip;
+
+		/*
+		 * Extract the IDs. Braindead PHYs will be handled by
+		 * the `ukphy' driver, as we have no ID information to
+		 * match on.
+	 	 */
+		ma.mii_id1 = MIIBUS_READREG(dev, ma.mii_phyno, MII_PHYIDR1);
+		ma.mii_id2 = MIIBUS_READREG(dev, ma.mii_phyno, MII_PHYIDR2);
+
+		args = malloc(sizeof(struct mii_attach_args), M_DEVBUF,
+		    M_NOWAIT);
+		if (args == NULL)
+			goto skip;
+		bcopy((char *)&ma, (char *)args, sizeof(ma));
+		phy = device_add_child(*miibus, NULL, -1);
+		if (phy == NULL) {
+			free(args, M_DEVBUF);
+			goto skip;
+		}
+		device_set_ivars(phy, args);
+ skip:
+		offset++;
+	}
+
+	if (first != 0) {
+		if (phy == NULL) {
+			rv = ENXIO;
+			goto fail;
+		}
+		rv = bus_generic_attach(dev);
+		if (rv != 0)
+			goto fail;
+
+		/* Attaching of the PHY drivers is done in miibus_attach(). */
+		return (0);
+	}
+	rv = bus_generic_attach(*miibus);
+	if (rv != 0)
+		goto fail;
+
+	return (0);
+
+ fail:
+	if (*miibus != NULL)
+		device_delete_child(dev, *miibus);
+	free(ivars, M_DEVBUF);
+	if (first != 0)
+		*miibus = NULL;
+	return (rv);
+}
+
+int
+mii_phy_probe(device_t dev, device_t *child, ifm_change_cb_t ifmedia_upd,
+    ifm_stat_cb_t ifmedia_sts)
+{
+	struct ifnet *ifp;
+
+	/*
+	 * Note that each NIC's softc must start with an ifnet pointer.
+	 * XXX: EVIL HACK!
+	 */
+	ifp = *(struct ifnet **)device_get_softc(dev);
+	return (mii_attach(dev, child, ifp, ifmedia_upd, ifmedia_sts,
+	    BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0));
+}
+
+/*
+ * Media changed; notify all PHYs.
+ */
+int
+mii_mediachg(struct mii_data *mii)
+{
+	struct mii_softc *child;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int rv;
+
+	mii->mii_media_status = 0;
+	mii->mii_media_active = IFM_NONE;
+
+	LIST_FOREACH(child, &mii->mii_phys, mii_list) {
+		/*
+		 * If the media indicates a different PHY instance,
+		 * isolate this one.
+		 */
+		if (IFM_INST(ife->ifm_media) != child->mii_inst) {
+			if ((child->mii_flags & MIIF_NOISOLATE) != 0) {
+				device_printf(child->mii_dev, "%s: "
+				    "can't handle non-zero PHY instance %d\n",
+				    __func__, child->mii_inst);
+				continue;
+			}
+			PHY_WRITE(child, MII_BMCR, PHY_READ(child, MII_BMCR) |
+			    BMCR_ISO);
+			continue;
+		}
+		rv = (*child->mii_service)(child, mii, MII_MEDIACHG);
+		if (rv)
+			return (rv);
+	}
+	return (0);
+}
+
+/*
+ * Call the PHY tick routines, used during autonegotiation.
+ */
+void
+mii_tick(struct mii_data *mii)
+{
+	struct mii_softc *child;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+
+	LIST_FOREACH(child, &mii->mii_phys, mii_list) {
+		/*
+		 * If this PHY instance isn't currently selected, just skip
+		 * it.
+		 */
+		if (IFM_INST(ife->ifm_media) != child->mii_inst)
+			continue;
+		(void)(*child->mii_service)(child, mii, MII_TICK);
+	}
+}
+
+/*
+ * Get media status from PHYs.
+ */
+void
+mii_pollstat(struct mii_data *mii)
+{
+	struct mii_softc *child;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+
+	mii->mii_media_status = 0;
+	mii->mii_media_active = IFM_NONE;
+
+	LIST_FOREACH(child, &mii->mii_phys, mii_list) {
+		/*
+		 * If we're not polling this PHY instance, just skip it.
+		 */
+		if (IFM_INST(ife->ifm_media) != child->mii_inst)
+			continue;
+		(void)(*child->mii_service)(child, mii, MII_POLLSTAT);
+	}
+}
+
+/*
+ * Inform the PHYs that the interface is down.
+ */
+void
+mii_down(struct mii_data *mii)
+{
+	struct mii_softc *child;
+
+	LIST_FOREACH(child, &mii->mii_phys, mii_list)
+		mii_phy_down(child);
+}
diff --git a/freebsd/sys/dev/mii/mii.h b/freebsd/sys/dev/mii/mii.h
new file mode 100644
index 00000000..21c6b768
--- /dev/null
+++ b/freebsd/sys/dev/mii/mii.h
@@ -0,0 +1,212 @@
+/*	$NetBSD: mii.h,v 1.9 2001/05/31 03:07:14 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 1997 Manuel Bouyer.  All rights reserved.
+ *
+ * Modification to match BSD/OS 3.0 MII interface by Jason R. Thorpe,
+ * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_MII_MII_HH_
+#define	_DEV_MII_MII_HH_
+
+/*
+ * Registers common to all PHYs.
+ */
+
+#define	MII_NPHY	32	/* max # of PHYs per MII */
+
+/*
+ * MII commands, used if a device must drive the MII lines
+ * manually.
+ */
+#define	MII_COMMAND_START	0x01
+#define	MII_COMMAND_READ	0x02
+#define	MII_COMMAND_WRITE	0x01
+#define	MII_COMMAND_ACK		0x02
+
+#define	MII_BMCR	0x00	/* Basic mode control register (rw) */
+#define	BMCR_RESET	0x8000	/* reset */
+#define	BMCR_LOOP	0x4000	/* loopback */
+#define	BMCR_SPEED0	0x2000	/* speed selection (LSB) */
+#define	BMCR_AUTOEN	0x1000	/* autonegotiation enable */
+#define	BMCR_PDOWN	0x0800	/* power down */
+#define	BMCR_ISO	0x0400	/* isolate */
+#define	BMCR_STARTNEG	0x0200	/* restart autonegotiation */
+#define	BMCR_FDX	0x0100	/* Set duplex mode */
+#define	BMCR_CTEST	0x0080	/* collision test */
+#define	BMCR_SPEED1	0x0040	/* speed selection (MSB) */
+
+#define	BMCR_S10	0x0000		/* 10 Mb/s */
+#define	BMCR_S100	BMCR_SPEED0	/* 100 Mb/s */
+#define	BMCR_S1000	BMCR_SPEED1	/* 1000 Mb/s */
+
+#define	BMCR_SPEED(x)	((x) & (BMCR_SPEED0|BMCR_SPEED1))
+
+#define	MII_BMSR	0x01	/* Basic mode status register (ro) */
+#define	BMSR_100T4	0x8000	/* 100 base T4 capable */
+#define	BMSR_100TXFDX	0x4000	/* 100 base Tx full duplex capable */
+#define	BMSR_100TXHDX	0x2000	/* 100 base Tx half duplex capable */
+#define	BMSR_10TFDX	0x1000	/* 10 base T full duplex capable */
+#define	BMSR_10THDX	0x0800	/* 10 base T half duplex capable */
+#define	BMSR_100T2FDX	0x0400	/* 100 base T2 full duplex capable */
+#define	BMSR_100T2HDX	0x0200	/* 100 base T2 half duplex capable */
+#define	BMSR_EXTSTAT	0x0100	/* Extended status in register 15 */
+#define	BMSR_MFPS	0x0040	/* MII Frame Preamble Suppression */
+#define	BMSR_ACOMP	0x0020	/* Autonegotiation complete */
+#define	BMSR_RFAULT	0x0010	/* Link partner fault */
+#define	BMSR_ANEG	0x0008	/* Autonegotiation capable */
+#define	BMSR_LINK	0x0004	/* Link status */
+#define	BMSR_JABBER	0x0002	/* Jabber detected */
+#define	BMSR_EXTCAP	0x0001	/* Extended capability */
+
+#define	BMSR_DEFCAPMASK	0xffffffff
+
+/*
+ * Note that the EXTSTAT bit indicates that there is extended status
+ * info available in register 15, but 802.3 section 22.2.4.3 also
+ * states that that all 1000 Mb/s capable PHYs will set this bit to 1.
+ */
+#if 0
+#define	BMSR_MEDIAMASK	(BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX|BMSR_10TFDX| \
+			 BMSR_10THDX|BMSR_ANEG)
+
+#else
+/* NetBSD uses: */
+#define	BMSR_MEDIAMASK	(BMSR_100T4|BMSR_100TXFDX|BMSR_100TXHDX| \
+			 BMSR_10TFDX|BMSR_10THDX|BMSR_100T2FDX|BMSR_100T2HDX)
+#endif
+
+/*
+ * Convert BMSR media capabilities to ANAR bits for autonegotiation.
+ * Note the shift chopps off the BMSR_ANEG bit.
+ */
+#define	BMSR_MEDIA_TO_ANAR(x)	(((x) & BMSR_MEDIAMASK) >> 6)
+
+#define	MII_PHYIDR1	0x02	/* ID register 1 (ro) */
+
+#define	MII_PHYIDR2	0x03	/* ID register 2 (ro) */
+#define	IDR2_OUILSB	0xfc00	/* OUI LSB */
+#define	IDR2_MODEL	0x03f0	/* vendor model */
+#define	IDR2_REV	0x000f	/* vendor revision */
+
+#define	MII_OUI(id1, id2)	(((id1) << 6) | ((id2) >> 10))
+#define	MII_MODEL(id2)		(((id2) & IDR2_MODEL) >> 4)
+#define	MII_REV(id2)		((id2) & IDR2_REV)
+
+#define	MII_ANAR	0x04	/* Autonegotiation advertisement (rw) */
+		/* section 28.2.4.1 and 37.2.6.1 */
+#define ANAR_NP		0x8000	/* Next page (ro) */
+#define	ANAR_ACK	0x4000	/* link partner abilities acknowledged (ro) */
+#define ANAR_RF		0x2000	/* remote fault (ro) */
+#define	ANAR_FC		0x0400	/* local device supports PAUSE */
+#define ANAR_T4		0x0200	/* local device supports 100bT4 */
+#define ANAR_TX_FD	0x0100	/* local device supports 100bTx FD */
+#define ANAR_TX		0x0080	/* local device supports 100bTx */
+#define ANAR_10_FD	0x0040	/* local device supports 10bT FD */
+#define ANAR_10		0x0020	/* local device supports 10bT */
+#define	ANAR_CSMA	0x0001	/* protocol selector CSMA/CD */
+#define	ANAR_PAUSE_NONE		(0 << 10)
+#define	ANAR_PAUSE_SYM		(1 << 10)
+#define	ANAR_PAUSE_ASYM		(2 << 10)
+#define	ANAR_PAUSE_TOWARDS	(3 << 10)
+
+#define	ANAR_X_FD	0x0020	/* local device supports 1000BASE-X FD */
+#define	ANAR_X_HD	0x0040	/* local device supports 1000BASE-X HD */
+#define	ANAR_X_PAUSE_NONE	(0 << 7)
+#define	ANAR_X_PAUSE_SYM	(1 << 7)
+#define	ANAR_X_PAUSE_ASYM	(2 << 7)
+#define	ANAR_X_PAUSE_TOWARDS	(3 << 7)
+
+#define	MII_ANLPAR	0x05	/* Autonegotiation lnk partner abilities (rw) */
+		/* section 28.2.4.1 and 37.2.6.1 */
+#define ANLPAR_NP	0x8000	/* Next page (ro) */
+#define	ANLPAR_ACK	0x4000	/* link partner accepted ACK (ro) */
+#define ANLPAR_RF	0x2000	/* remote fault (ro) */
+#define	ANLPAR_FC	0x0400	/* link partner supports PAUSE */
+#define ANLPAR_T4	0x0200	/* link partner supports 100bT4 */
+#define ANLPAR_TX_FD	0x0100	/* link partner supports 100bTx FD */
+#define ANLPAR_TX	0x0080	/* link partner supports 100bTx */
+#define ANLPAR_10_FD	0x0040	/* link partner supports 10bT FD */
+#define ANLPAR_10	0x0020	/* link partner supports 10bT */
+#define	ANLPAR_CSMA	0x0001	/* protocol selector CSMA/CD */
+#define	ANLPAR_PAUSE_MASK	(3 << 10)
+#define	ANLPAR_PAUSE_NONE	(0 << 10)
+#define	ANLPAR_PAUSE_SYM	(1 << 10)
+#define	ANLPAR_PAUSE_ASYM	(2 << 10)
+#define	ANLPAR_PAUSE_TOWARDS	(3 << 10)
+
+#define	ANLPAR_X_FD	0x0020	/* local device supports 1000BASE-X FD */
+#define	ANLPAR_X_HD	0x0040	/* local device supports 1000BASE-X HD */
+#define	ANLPAR_X_PAUSE_MASK	(3 << 7)
+#define	ANLPAR_X_PAUSE_NONE	(0 << 7)
+#define	ANLPAR_X_PAUSE_SYM	(1 << 7)
+#define	ANLPAR_X_PAUSE_ASYM	(2 << 7)
+#define	ANLPAR_X_PAUSE_TOWARDS	(3 << 7)
+
+#define	MII_ANER	0x06	/* Autonegotiation expansion (ro) */
+		/* section 28.2.4.1 and 37.2.6.1 */
+#define ANER_MLF	0x0010	/* multiple link detection fault */
+#define ANER_LPNP	0x0008	/* link parter next page-able */
+#define ANER_NP		0x0004	/* next page-able */
+#define ANER_PAGE_RX	0x0002	/* Page received */
+#define ANER_LPAN	0x0001	/* link parter autoneg-able */
+
+#define	MII_ANNP	0x07	/* Autonegotiation next page */
+		/* section 28.2.4.1 and 37.2.6.1 */
+
+#define	MII_ANLPRNP	0x08	/* Autonegotiation link partner rx next page */
+		/* section 32.5.1 and 37.2.6.1 */
+
+			/* This is also the 1000baseT control register */
+#define	MII_100T2CR	0x09	/* 100base-T2 control register */
+#define	GTCR_TEST_MASK	0xe000	/* see 802.3ab ss. 40.6.1.1.2 */
+#define	GTCR_MAN_MS	0x1000	/* enable manual master/slave control */
+#define	GTCR_ADV_MS	0x0800	/* 1 = adv. master, 0 = adv. slave */
+#define	GTCR_PORT_TYPE	0x0400	/* 1 = DCE, 0 = DTE (NIC) */
+#define	GTCR_ADV_1000TFDX 0x0200 /* adv. 1000baseT FDX */
+#define	GTCR_ADV_1000THDX 0x0100 /* adv. 1000baseT HDX */
+
+			/* This is also the 1000baseT status register */
+#define	MII_100T2SR	0x0a	/* 100base-T2 status register */
+#define	GTSR_MAN_MS_FLT	0x8000	/* master/slave config fault */
+#define	GTSR_MS_RES	0x4000	/* result: 1 = master, 0 = slave */
+#define	GTSR_LRS	0x2000	/* local rx status, 1 = ok */
+#define	GTSR_RRS	0x1000	/* remove rx status, 1 = ok */
+#define	GTSR_LP_1000TFDX 0x0800	/* link partner 1000baseT FDX capable */
+#define	GTSR_LP_1000THDX 0x0400	/* link partner 1000baseT HDX capable */
+#define	GTSR_LP_ASM_DIR	0x0200	/* link partner asym. pause dir. capable */
+#define	GTSR_IDLE_ERR	0x00ff	/* IDLE error count */
+
+#define	MII_EXTSR	0x0f	/* Extended status register */
+#define	EXTSR_1000XFDX	0x8000	/* 1000X full-duplex capable */
+#define	EXTSR_1000XHDX	0x4000	/* 1000X half-duplex capable */
+#define	EXTSR_1000TFDX	0x2000	/* 1000T full-duplex capable */
+#define	EXTSR_1000THDX	0x1000	/* 1000T half-duplex capable */
+
+#define	EXTSR_MEDIAMASK	(EXTSR_1000XFDX|EXTSR_1000XHDX| \
+			 EXTSR_1000TFDX|EXTSR_1000THDX)
+
+#endif /* _DEV_MII_MII_HH_ */
diff --git a/freebsd/sys/dev/mii/mii_physubr.c b/freebsd/sys/dev/mii/mii_physubr.c
new file mode 100644
index 00000000..f5a278d6
--- /dev/null
+++ b/freebsd/sys/dev/mii/mii_physubr.c
@@ -0,0 +1,667 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*	$NetBSD: mii_physubr.c,v 1.5 1999/08/03 19:41:49 drochner Exp $	*/
+
+/*-
+ * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Subroutines common to all PHYs.
+ */
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/kernel.h>
+#include <freebsd/sys/socket.h>
+#include <freebsd/sys/errno.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/bus.h>
+
+#include <freebsd/net/if.h>
+#include <freebsd/net/if_media.h>
+
+#include <freebsd/dev/mii/mii.h>
+#include <freebsd/dev/mii/miivar.h>
+
+#include <freebsd/local/miibus_if.h>
+
+/*
+ * Media to register setting conversion table.  Order matters.
+ */
+const struct mii_media mii_media_table[MII_NMEDIA] = {
+	/* None */
+	{ BMCR_ISO,		ANAR_CSMA,
+	  0, },
+
+	/* 10baseT */
+	{ BMCR_S10,		ANAR_CSMA|ANAR_10,
+	  0, },
+
+	/* 10baseT-FDX */
+	{ BMCR_S10|BMCR_FDX,	ANAR_CSMA|ANAR_10_FD,
+	  0, },
+
+	/* 100baseT4 */
+	{ BMCR_S100,		ANAR_CSMA|ANAR_T4,
+	  0, },
+
+	/* 100baseTX */
+	{ BMCR_S100,		ANAR_CSMA|ANAR_TX,
+	  0, },
+
+	/* 100baseTX-FDX */
+	{ BMCR_S100|BMCR_FDX,	ANAR_CSMA|ANAR_TX_FD,
+	  0, },
+
+	/* 1000baseX */
+	{ BMCR_S1000,		ANAR_CSMA,
+	  0, },
+
+	/* 1000baseX-FDX */
+	{ BMCR_S1000|BMCR_FDX,	ANAR_CSMA,
+	  0, },
+
+	/* 1000baseT */
+	{ BMCR_S1000,		ANAR_CSMA,
+	  GTCR_ADV_1000THDX },
+
+	/* 1000baseT-FDX */
+	{ BMCR_S1000,		ANAR_CSMA,
+	  GTCR_ADV_1000TFDX },
+};
+
+void
+mii_phy_setmedia(struct mii_softc *sc)
+{
+	struct mii_data *mii = sc->mii_pdata;
+	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+	int bmcr, anar, gtcr;
+
+	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
+		/*
+		 * Force renegotiation if MIIF_DOPAUSE or MIIF_FORCEANEG.
+		 * The former is necessary as we might switch from flow-
+		 * control advertisment being off to on or vice versa.
+		 */
+		if ((PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN) == 0 ||
+		    (sc->mii_flags & (MIIF_DOPAUSE | MIIF_FORCEANEG)) != 0)
+			(void)mii_phy_auto(sc);
+		return;
+	}
+
+	/*
+	 * Table index is stored in the media entry.
+	 */
+
+	KASSERT(ife->ifm_data >=0 && ife->ifm_data < MII_NMEDIA,
+	    ("invalid ife->ifm_data (0x%x) in mii_phy_setmedia",
+	    ife->ifm_data));
+
+	anar = mii_media_table[ife->ifm_data].mm_anar;
+	bmcr = mii_media_table[ife->ifm_data].mm_bmcr;
+	gtcr = mii_media_table[ife->ifm_data].mm_gtcr;
+
+	if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
+		gtcr |= GTCR_MAN_MS;
+		if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
+			gtcr |= GTCR_ADV_MS;
+	}
+
+	if ((ife->ifm_media & IFM_GMASK) == (IFM_FDX | IFM_FLOW) ||
+	    (sc->mii_flags & MIIF_FORCEPAUSE) != 0) {
+		if ((sc->mii_flags & MIIF_IS_1000X) != 0)
+			anar |= ANAR_X_PAUSE_TOWARDS;
+		else {
+			anar |= ANAR_FC;
+			/* XXX Only 1000BASE-T has PAUSE_ASYM? */
+			if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0 &&
+			    (sc->mii_extcapabilities &
+			    (EXTSR_1000THDX | EXTSR_1000TFDX)) != 0)
+				anar |= ANAR_X_PAUSE_ASYM;
+		}
+	}
+
+	if ((ife->ifm_media & IFM_LOOP) != 0)
+		bmcr |= BMCR_LOOP;
+
+	PHY_WRITE(sc, MII_ANAR, anar);
+	PHY_WRITE(sc, MII_BMCR, bmcr);
+	if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0)
+		PHY_WRITE(sc, MII_100T2CR, gtcr);
+}
+
+int
+mii_phy_auto(struct mii_softc *sc)
+{
+	struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
+	int anar, gtcr;
+
+	/*
+	 * Check for 1000BASE-X.  Autonegotiation is a bit
+	 * different on such devices.
+	 */
+	if ((sc->mii_flags & MIIF_IS_1000X) != 0) {
+		anar = 0;
+		if ((sc->mii_extcapabilities & EXTSR_1000XFDX) != 0)
+			anar |= ANAR_X_FD;
+		if ((sc->mii_extcapabilities & EXTSR_1000XHDX) != 0)
+			anar |= ANAR_X_HD;
+
+		if ((ife->ifm_media & IFM_FLOW) != 0 ||
+		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
+			anar |= ANAR_X_PAUSE_TOWARDS;
+		PHY_WRITE(sc, MII_ANAR, anar);
+	} else {
+		anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) |
+		    ANAR_CSMA;
+		if ((ife->ifm_media & IFM_FLOW) != 0 ||
+		    (sc->mii_flags & MIIF_FORCEPAUSE) != 0) {
+			if ((sc->mii_capabilities & BMSR_100TXFDX) != 0)
+				anar |= ANAR_FC;
+			/* XXX Only 1000BASE-T has PAUSE_ASYM? */
+			if (((sc->mii_flags & MIIF_HAVE_GTCR) != 0) &&
+			    (sc->mii_extcapabilities &
+			    (EXTSR_1000THDX | EXTSR_1000TFDX)) != 0)
+				anar |= ANAR_X_PAUSE_ASYM;
+		}
+		PHY_WRITE(sc, MII_ANAR, anar);
+		if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
+			gtcr = 0;
+			if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0)
+				gtcr |= GTCR_ADV_1000TFDX;
+			if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0)
+				gtcr |= GTCR_ADV_1000THDX;
+			PHY_WRITE(sc, MII_100T2CR, gtcr);
+		}
+	}
+	PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
+	return (EJUSTRETURN);
+}
+
+int
+mii_phy_tick(struct mii_softc *sc)
+{
+	struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
+	struct ifnet *ifp = sc->mii_pdata->mii_ifp;
+	int reg;
+
+	/* Just bail now if the interface is down. */
+	if ((ifp->if_flags & IFF_UP) == 0)
+		return (EJUSTRETURN);
+
+	/*
+	 * If we're not doing autonegotiation, we don't need to do
+	 * any extra work here.  However, we need to check the link
+	 * status so we can generate an announcement if the status
+	 * changes.
+	 */
+	if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+		sc->mii_ticks = 0;	/* reset autonegotiation timer. */
+		return (0);
+	}
+
+	/* Read the status register twice; BMSR_LINK is latch-low. */
+	reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
+	if ((reg & BMSR_LINK) != 0) {
+		sc->mii_ticks = 0;	/* reset autonegotiation timer. */
+		/* See above. */
+		return (0);
+	}
+
+	/* Announce link loss right after it happens */
+	if (sc->mii_ticks++ == 0)
+		return (0);
+
+	/* XXX: use default value if phy driver did not set mii_anegticks */
+	if (sc->mii_anegticks == 0)
+		sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+
+	/* Only retry autonegotiation every mii_anegticks ticks. */
+	if (sc->mii_ticks <= sc->mii_anegticks)
+		return (EJUSTRETURN);
+
+	sc->mii_ticks = 0;
+	mii_phy_reset(sc);
+	mii_phy_auto(sc);
+	return (0);
+}
+
+void
+mii_phy_reset(struct mii_softc *sc)
+{
+	struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
+	int reg, i;
+
+	if ((sc->mii_flags & MIIF_NOISOLATE) != 0)
+		reg = BMCR_RESET;
+	else
+		reg = BMCR_RESET | BMCR_ISO;
+	PHY_WRITE(sc, MII_BMCR, reg);
+
+	/* Wait 100ms for it to complete. */
+	for (i = 0; i < 100; i++) {
+		reg = PHY_READ(sc, MII_BMCR);
+		if ((reg & BMCR_RESET) == 0)
+			break;
+		DELAY(1000);
+	}
+
+	if ((sc->mii_flags & MIIF_NOISOLATE) == 0) {
+		if ((ife == NULL && sc->mii_inst != 0) ||
+		    (ife != NULL && IFM_INST(ife->ifm_media) != sc->mii_inst))
+			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+	}
+}
+
+void
+mii_phy_down(struct mii_softc *sc)
+{
+
+}
+
+void
+mii_phy_update(struct mii_softc *sc, int cmd)
+{
+	struct mii_data *mii = sc->mii_pdata;
+
+	if (sc->mii_media_active != mii->mii_media_active ||
+	    cmd == MII_MEDIACHG) {
+		MIIBUS_STATCHG(sc->mii_dev);
+		sc->mii_media_active = mii->mii_media_active;
+	}
+	if (sc->mii_media_status != mii->mii_media_status) {
+		MIIBUS_LINKCHG(sc->mii_dev);
+		sc->mii_media_status = mii->mii_media_status;
+	}
+}
+
+/*
+ * Given an ifmedia word, return the corresponding ANAR value.
+ */
+int
+mii_anar(int media)
+{
+	int rv;
+
+	switch (media & (IFM_TMASK|IFM_NMASK|IFM_FDX)) {
+	case IFM_ETHER|IFM_10_T:
+		rv = ANAR_10|ANAR_CSMA;
+		break;
+	case IFM_ETHER|IFM_10_T|IFM_FDX:
+		rv = ANAR_10_FD|ANAR_CSMA;
+		break;
+	case IFM_ETHER|IFM_100_TX:
+		rv = ANAR_TX|ANAR_CSMA;
+		break;
+	case IFM_ETHER|IFM_100_TX|IFM_FDX:
+		rv = ANAR_TX_FD|ANAR_CSMA;
+		break;
+	case IFM_ETHER|IFM_100_T4:
+		rv = ANAR_T4|ANAR_CSMA;
+		break;
+	default:
+		rv = 0;
+		break;
+	}
+
+	return (rv);
+}
+
+/*
+ * Initialize generic PHY media based on BMSR, called when a PHY is
+ * attached.  We expect to be set up to print a comma-separated list
+ * of media names.  Does not print a newline.
+ */
+void
+mii_add_media(struct mii_softc *sc)
+{
+	struct mii_data *mii = sc->mii_pdata;
+	const char *sep = "";
+
+	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0) {
+		printf("no media present");
+		return;
+	}
+
+#define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
+#define	PRINT(s)	printf("%s%s", sep, s); sep = ", "
+
+	if (sc->mii_capabilities & BMSR_10THDX) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), 0);
+		PRINT("10baseT");
+	}
+	if (sc->mii_capabilities & BMSR_10TFDX) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
+		    BMCR_FDX);
+		PRINT("10baseT-FDX");
+	}
+	if (sc->mii_capabilities & BMSR_100TXHDX) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
+		    BMCR_S100);
+		PRINT("100baseTX");
+	}
+	if (sc->mii_capabilities & BMSR_100TXFDX) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
+		    BMCR_S100|BMCR_FDX);
+		PRINT("100baseTX-FDX");
+	}
+	if (sc->mii_capabilities & BMSR_100T4) {
+		/*
+		 * XXX How do you enable 100baseT4?  I assume we set
+		 * XXX BMCR_S100 and then assume the PHYs will take
+		 * XXX watever action is necessary to switch themselves
+		 * XXX into T4 mode.
+		 */
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_T4, 0, sc->mii_inst),
+		    BMCR_S100);
+		PRINT("100baseT4");
+	}
+	if (sc->mii_capabilities & BMSR_ANEG) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst),
+		    BMCR_AUTOEN);
+		PRINT("auto");
+	}
+
+
+
+#undef ADD
+#undef PRINT
+}
+
+/*
+ * Initialize generic PHY media based on BMSR, called when a PHY is
+ * attached.  We expect to be set up to print a comma-separated list
+ * of media names.  Does not print a newline.
+ */
+void
+mii_phy_add_media(struct mii_softc *sc)
+{
+	struct mii_data *mii = sc->mii_pdata;
+	const char *sep = "";
+	int fdx = 0;
+
+	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
+	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) {
+		printf("no media present");
+		return;
+	}
+
+	/*
+	 * Set the autonegotiation timer for 10/100 media.  Gigabit media is
+	 * handled below.
+	 */
+	sc->mii_anegticks = MII_ANEGTICKS;
+
+#define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
+#define	PRINT(s)	printf("%s%s", sep, s); sep = ", "
+
+	if ((sc->mii_flags & MIIF_NOISOLATE) == 0)
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
+		    MII_MEDIA_NONE);
+
+	/*
+	 * There are different interpretations for the bits in
+	 * HomePNA PHYs.  And there is really only one media type
+	 * that is supported.
+	 */
+	if ((sc->mii_flags & MIIF_IS_HPNA) != 0) {
+		if ((sc->mii_capabilities & BMSR_10THDX) != 0) {
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_HPNA_1, 0,
+			    sc->mii_inst), MII_MEDIA_10_T);
+			PRINT("HomePNA1");
+		}
+		return;
+	}
+
+	if ((sc->mii_capabilities & BMSR_10THDX) != 0) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
+		    MII_MEDIA_10_T);
+		PRINT("10baseT");
+	}
+	if ((sc->mii_capabilities & BMSR_10TFDX) != 0) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
+		    MII_MEDIA_10_T_FDX);
+		PRINT("10baseT-FDX");
+		if ((sc->mii_flags & MIIF_DOPAUSE) != 0 &&
+		    (sc->mii_flags & MIIF_NOMANPAUSE) == 0) {
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T,
+			    IFM_FDX | IFM_FLOW, sc->mii_inst),
+			    MII_MEDIA_10_T_FDX);
+			PRINT("10baseT-FDX-flow");
+		}
+		fdx = 1;
+	}
+	if ((sc->mii_capabilities & BMSR_100TXHDX) != 0) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
+		    MII_MEDIA_100_TX);
+		PRINT("100baseTX");
+	}
+	if ((sc->mii_capabilities & BMSR_100TXFDX) != 0) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
+		    MII_MEDIA_100_TX_FDX);
+		PRINT("100baseTX-FDX");
+		if ((sc->mii_flags & MIIF_DOPAUSE) != 0 &&
+		    (sc->mii_flags & MIIF_NOMANPAUSE) == 0) {
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX,
+			    IFM_FDX | IFM_FLOW, sc->mii_inst),
+			    MII_MEDIA_100_TX_FDX);
+			PRINT("100baseTX-FDX-flow");
+		}
+		fdx = 1;
+	}
+	if ((sc->mii_capabilities & BMSR_100T4) != 0) {
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_T4, 0, sc->mii_inst),
+		    MII_MEDIA_100_T4);
+		PRINT("100baseT4");
+	}
+
+	if ((sc->mii_extcapabilities & EXTSR_MEDIAMASK) != 0) {
+		/*
+		 * XXX Right now only handle 1000SX and 1000TX.  Need
+		 * XXX to handle 1000LX and 1000CX somehow.
+		 */
+		if ((sc->mii_extcapabilities & EXTSR_1000XHDX) != 0) {
+			sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+			sc->mii_flags |= MIIF_IS_1000X;
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0,
+			    sc->mii_inst), MII_MEDIA_1000_X);
+			PRINT("1000baseSX");
+		}
+		if ((sc->mii_extcapabilities & EXTSR_1000XFDX) != 0) {
+			sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+			sc->mii_flags |= MIIF_IS_1000X;
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX,
+			    sc->mii_inst), MII_MEDIA_1000_X_FDX);
+			PRINT("1000baseSX-FDX");
+			if ((sc->mii_flags & MIIF_DOPAUSE) != 0 &&
+			    (sc->mii_flags & MIIF_NOMANPAUSE) == 0) {
+				ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX,
+				    IFM_FDX | IFM_FLOW, sc->mii_inst),
+				    MII_MEDIA_1000_X_FDX);
+				PRINT("1000baseSX-FDX-flow");
+			}
+			fdx = 1;
+		}
+
+		/*
+		 * 1000baseT media needs to be able to manipulate
+		 * master/slave mode.
+		 *
+		 * All 1000baseT PHYs have a 1000baseT control register.
+		 */
+		if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0) {
+			sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+			sc->mii_flags |= MIIF_HAVE_GTCR;
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
+			    sc->mii_inst), MII_MEDIA_1000_T);
+			PRINT("1000baseT");
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
+			    IFM_ETH_MASTER, sc->mii_inst), MII_MEDIA_1000_T);
+			PRINT("1000baseT-master");
+		}
+		if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0) {
+			sc->mii_anegticks = MII_ANEGTICKS_GIGE;
+			sc->mii_flags |= MIIF_HAVE_GTCR;
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX,
+			    sc->mii_inst), MII_MEDIA_1000_T_FDX);
+			PRINT("1000baseT-FDX");
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
+			    IFM_FDX | IFM_ETH_MASTER, sc->mii_inst),
+			    MII_MEDIA_1000_T_FDX);
+			PRINT("1000baseT-FDX-master");
+			if ((sc->mii_flags & MIIF_DOPAUSE) != 0 &&
+			    (sc->mii_flags & MIIF_NOMANPAUSE) == 0) {
+				ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
+				    IFM_FDX | IFM_FLOW, sc->mii_inst),
+				    MII_MEDIA_1000_T_FDX);
+				PRINT("1000baseT-FDX-flow");
+				ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
+				    IFM_FDX | IFM_FLOW | IFM_ETH_MASTER,
+				    sc->mii_inst), MII_MEDIA_1000_T_FDX);
+				PRINT("1000baseT-FDX-flow-master");
+			}
+			fdx = 1;
+		}
+	}
+
+	if ((sc->mii_capabilities & BMSR_ANEG) != 0) {
+		/* intentionally invalid index */
+		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst),
+		    MII_NMEDIA);
+		PRINT("auto");
+		if (fdx != 0 && (sc->mii_flags & MIIF_DOPAUSE) != 0) {
+			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, IFM_FLOW,
+			    sc->mii_inst), MII_NMEDIA);
+			PRINT("auto-flow");
+		}
+	}
+#undef ADD
+#undef PRINT
+}
+
+int
+mii_phy_detach(device_t dev)
+{
+	struct mii_softc *sc;
+
+	sc = device_get_softc(dev);
+	mii_phy_down(sc);
+	sc->mii_dev = NULL;
+	LIST_REMOVE(sc, mii_list);
+	return (0);
+}
+
+const struct mii_phydesc *
+mii_phy_match_gen(const struct mii_attach_args *ma,
+  const struct mii_phydesc *mpd, size_t len)
+{
+
+	for (; mpd->mpd_name != NULL;
+	    mpd = (const struct mii_phydesc *)((const char *)mpd + len)) {
+		if (MII_OUI(ma->mii_id1, ma->mii_id2) == mpd->mpd_oui &&
+		    MII_MODEL(ma->mii_id2) == mpd->mpd_model)
+			return (mpd);
+	}
+	return (NULL);
+}
+
+const struct mii_phydesc *
+mii_phy_match(const struct mii_attach_args *ma, const struct mii_phydesc *mpd)
+{
+
+	return (mii_phy_match_gen(ma, mpd, sizeof(struct mii_phydesc)));
+}
+
+int
+mii_phy_dev_probe(device_t dev, const struct mii_phydesc *mpd, int mrv)
+{
+
+	mpd = mii_phy_match(device_get_ivars(dev), mpd);
+	if (mpd != NULL) {
+		device_set_desc(dev, mpd->mpd_name);
+		return (mrv);
+	}
+	return (ENXIO);
+}
+
+/*
+ * Return the flow control status flag from MII_ANAR & MII_ANLPAR.
+ */
+u_int
+mii_phy_flowstatus(struct mii_softc *sc)
+{
+	int anar, anlpar;
+
+	if ((sc->mii_flags & MIIF_DOPAUSE) == 0)
+		return (0);
+
+	anar = PHY_READ(sc, MII_ANAR);
+	anlpar = PHY_READ(sc, MII_ANLPAR);
+
+	/*
+	 * Check for 1000BASE-X.  Autonegotiation is a bit
+	 * different on such devices.
+	 */
+	if ((sc->mii_flags & MIIF_IS_1000X) != 0) {
+		anar <<= 3;
+		anlpar <<= 3;
+	}
+
+	if ((anar & ANAR_PAUSE_SYM) != 0 && (anlpar & ANLPAR_PAUSE_SYM) != 0)
+		return (IFM_FLOW | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
+
+	if ((anar & ANAR_PAUSE_SYM) == 0) {
+		if ((anar & ANAR_PAUSE_ASYM) != 0 &&
+		    (anlpar & ANLPAR_PAUSE_TOWARDS) != 0)
+			return (IFM_FLOW | IFM_ETH_TXPAUSE);
+		else
+			return (0);
+	}
+
+	if ((anar & ANAR_PAUSE_ASYM) == 0) {
+		if ((anlpar & ANLPAR_PAUSE_SYM) != 0)
+			return (IFM_FLOW | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
+		else
+			return (0);
+	}
+
+	switch ((anlpar & ANLPAR_PAUSE_TOWARDS)) {
+	case ANLPAR_PAUSE_NONE:
+		return (0);
+	case ANLPAR_PAUSE_ASYM:
+		return (IFM_FLOW | IFM_ETH_RXPAUSE);
+	default:
+		return (IFM_FLOW | IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
+	}
+	/* NOTREACHED */
+}
diff --git a/freebsd/sys/dev/mii/miivar.h b/freebsd/sys/dev/mii/miivar.h
new file mode 100644
index 00000000..e8d467f7
--- /dev/null
+++ b/freebsd/sys/dev/mii/miivar.h
@@ -0,0 +1,260 @@
+/*	$NetBSD: miivar.h,v 1.8 1999/04/23 04:24:32 thorpej Exp $	*/
+
+/*-
+ * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_MII_MIIVAR_HH_
+#define	_DEV_MII_MIIVAR_HH_
+
+#include <freebsd/sys/queue.h>
+
+/*
+ * Media Independent Interface configuration defintions.
+ */
+
+struct mii_softc;
+
+/*
+ * Callbacks from MII layer into network interface device driver.
+ */
+typedef	int (*mii_readreg_t)(struct device *, int, int);
+typedef	void (*mii_writereg_t)(struct device *, int, int, int);
+typedef	void (*mii_statchg_t)(struct device *);
+
+/*
+ * A network interface driver has one of these structures in its softc.
+ * It is the interface from the network interface driver to the MII
+ * layer.
+ */
+struct mii_data {
+	struct ifmedia mii_media;	/* media information */
+	struct ifnet *mii_ifp;		/* pointer back to network interface */
+
+	/*
+	 * For network interfaces with multiple PHYs, a list of all
+	 * PHYs is required so they can all be notified when a media
+	 * request is made.
+	 */
+	LIST_HEAD(mii_listhead, mii_softc) mii_phys;
+	int mii_instance;
+
+	/*
+	 * PHY driver fills this in with active media status.
+	 */
+	int mii_media_status;
+	int mii_media_active;
+
+	/*
+	 * Calls from MII layer into network interface driver.
+	 */
+	mii_readreg_t mii_readreg;
+	mii_writereg_t mii_writereg;
+	mii_statchg_t mii_statchg;
+};
+typedef struct mii_data mii_data_t;
+
+/*
+ * This call is used by the MII layer to call into the PHY driver
+ * to perform a `service request'.
+ */
+typedef	int (*mii_downcall_t)(struct mii_softc *, struct mii_data *, int);
+
+/*
+ * Requests that can be made to the downcall.
+ */
+#define	MII_TICK	1	/* once-per-second tick */
+#define	MII_MEDIACHG	2	/* user changed media; perform the switch */
+#define	MII_POLLSTAT	3	/* user requested media status; fill it in */
+
+/*
+ * Each PHY driver's softc has one of these as the first member.
+ * XXX This would be better named "phy_softc", but this is the name
+ * XXX BSDI used, and we would like to have the same interface.
+ */
+struct mii_softc {
+	device_t mii_dev;		/* generic device glue */
+
+	LIST_ENTRY(mii_softc) mii_list;	/* entry on parent's PHY list */
+
+	int mii_phy;			/* our MII address */
+	int mii_inst;			/* instance for ifmedia */
+
+	mii_downcall_t mii_service;	/* our downcall */
+	struct mii_data *mii_pdata;	/* pointer to parent's mii_data */
+
+	int mii_flags;			/* misc. flags; see below */
+	int mii_capabilities;		/* capabilities from BMSR */
+	int mii_extcapabilities;	/* extended capabilities */
+	int mii_ticks;			/* MII_TICK counter */
+	int mii_anegticks;		/* ticks before retrying aneg */
+	int mii_media_active;		/* last active media */
+	int mii_media_status;		/* last active status */
+};
+typedef struct mii_softc mii_softc_t;
+
+/* mii_flags */
+#define	MIIF_INITDONE	0x00000001	/* has been initialized (mii_data) */
+#define	MIIF_NOISOLATE	0x00000002	/* do not isolate the PHY */
+#define	MIIF_NOLOOP	0x00000004	/* no loopback capability */
+#define	MIIF_DOINGAUTO	0x00000008	/* doing autonegotiation (mii_softc) */
+#define	MIIF_AUTOTSLEEP	0x00000010	/* use tsleep(), not callout() */
+#define	MIIF_HAVEFIBER	0x00000020	/* from parent: has fiber interface */
+#define	MIIF_HAVE_GTCR	0x00000040	/* has 100base-T2/1000base-T CR */
+#define	MIIF_IS_1000X	0x00000080	/* is a 1000BASE-X device */
+#define	MIIF_DOPAUSE	0x00000100	/* advertise PAUSE capability */
+#define	MIIF_IS_HPNA	0x00000200	/* is a HomePNA device */
+#define	MIIF_FORCEANEG	0x00000400	/* force auto-negotiation */
+#define	MIIF_NOMANPAUSE	0x00100000	/* no manual PAUSE selection */
+#define	MIIF_FORCEPAUSE	0x00200000	/* force PAUSE advertisment */
+#define	MIIF_MACPRIV0	0x01000000	/* private to the MAC driver */
+#define	MIIF_MACPRIV1	0x02000000	/* private to the MAC driver */
+#define	MIIF_MACPRIV2	0x04000000	/* private to the MAC driver */
+#define	MIIF_PHYPRIV0	0x10000000	/* private to the PHY driver */
+#define	MIIF_PHYPRIV1	0x20000000	/* private to the PHY driver */
+#define	MIIF_PHYPRIV2	0x40000000	/* private to the PHY driver */
+
+/* Default mii_anegticks values */
+#define	MII_ANEGTICKS		5
+#define	MII_ANEGTICKS_GIGE	17
+
+#define	MIIF_INHERIT_MASK	(MIIF_NOISOLATE|MIIF_NOLOOP|MIIF_AUTOTSLEEP)
+
+/*
+ * Special `locators' passed to mii_attach().  If one of these is not
+ * an `any' value, we look for *that* PHY and configure it.  If both
+ * are not `any', that is an error, and mii_attach() will fail.
+ */
+#define	MII_OFFSET_ANY		-1
+#define	MII_PHY_ANY		-1
+
+/*
+ * Used to attach a PHY to a parent.
+ */
+struct mii_attach_args {
+	struct mii_data *mii_data;	/* pointer to parent data */
+	int mii_phyno;			/* MII address */
+	int mii_id1;			/* PHY ID register 1 */
+	int mii_id2;			/* PHY ID register 2 */
+	int mii_capmask;		/* capability mask from BMSR */
+};
+typedef struct mii_attach_args mii_attach_args_t;
+
+/*
+ * Used to match a PHY.
+ */
+struct mii_phydesc {
+	u_int32_t mpd_oui;		/* the PHY's OUI */
+	u_int32_t mpd_model;		/* the PHY's model */
+	const char *mpd_name;		/* the PHY's name */
+};
+#define MII_PHY_DESC(a, b) { MII_OUI_ ## a, MII_MODEL_ ## a ## _ ## b, \
+	MII_STR_ ## a ## _ ## b }
+#define MII_PHY_END	{ 0, 0, NULL }
+
+/*
+ * An array of these structures map MII media types to BMCR/ANAR settings.
+ */
+struct mii_media {
+	int	mm_bmcr;		/* BMCR settings for this media */
+	int	mm_anar;		/* ANAR settings for this media */
+	int	mm_gtcr;		/* 100base-T2 or 1000base-T CR */
+};
+
+#define	MII_MEDIA_NONE		0
+#define	MII_MEDIA_10_T		1
+#define	MII_MEDIA_10_T_FDX	2
+#define	MII_MEDIA_100_T4	3
+#define	MII_MEDIA_100_TX	4
+#define	MII_MEDIA_100_TX_FDX	5
+#define	MII_MEDIA_1000_X	6
+#define	MII_MEDIA_1000_X_FDX	7
+#define	MII_MEDIA_1000_T	8
+#define	MII_MEDIA_1000_T_FDX	9
+#define	MII_NMEDIA		10
+
+#ifdef _KERNEL
+
+#define PHY_READ(p, r) \
+	MIIBUS_READREG((p)->mii_dev, (p)->mii_phy, (r))
+
+#define PHY_WRITE(p, r, v) \
+	MIIBUS_WRITEREG((p)->mii_dev, (p)->mii_phy, (r), (v))
+
+enum miibus_device_ivars {
+	MIIBUS_IVAR_FLAGS
+};
+
+/*
+ * Simplified accessors for miibus
+ */
+#define	MIIBUS_ACCESSOR(var, ivar, type)				\
+	__BUS_ACCESSOR(miibus, var, MIIBUS, ivar, type)
+
+MIIBUS_ACCESSOR(flags,		FLAGS,		int)
+
+extern devclass_t	miibus_devclass;
+extern driver_t		miibus_driver;
+
+int	miibus_probe(device_t);
+int	miibus_attach(device_t);
+int	miibus_detach(device_t);
+
+int	mii_attach(device_t, device_t *, struct ifnet *, ifm_change_cb_t,
+	    ifm_stat_cb_t, int, int, int, int);
+int	mii_anar(int);
+void	mii_down(struct mii_data *);
+int	mii_mediachg(struct mii_data *);
+void	mii_tick(struct mii_data *);
+void	mii_pollstat(struct mii_data *);
+int	mii_phy_probe(device_t, device_t *, ifm_change_cb_t, ifm_stat_cb_t);
+void	mii_add_media(struct mii_softc *);
+void	mii_phy_add_media(struct mii_softc *);
+
+int	mii_phy_auto(struct mii_softc *);
+int	mii_phy_detach(device_t dev);
+void	mii_phy_down(struct mii_softc *);
+u_int	mii_phy_flowstatus(struct mii_softc *);
+void	mii_phy_reset(struct mii_softc *);
+void	mii_phy_setmedia(struct mii_softc *sc);
+void	mii_phy_update(struct mii_softc *, int);
+int	mii_phy_tick(struct mii_softc *);
+
+const struct mii_phydesc * mii_phy_match(const struct mii_attach_args *ma,
+    const struct mii_phydesc *mpd);
+const struct mii_phydesc * mii_phy_match_gen(const struct mii_attach_args *ma,
+    const struct mii_phydesc *mpd, size_t endlen);
+int mii_phy_dev_probe(device_t dev, const struct mii_phydesc *mpd, int mrv);
+
+void	ukphy_status(struct mii_softc *);
+#endif /* _KERNEL */
+
+#endif /* _DEV_MII_MIIVAR_HH_ */