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authorSebastian Huber <sebastian.huber@embedded-brains.de>2013-11-04 11:33:00 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2013-11-04 15:28:21 +0100
commitaf5333e0a02b2295304d4e029b15ee15a4fe2b3a (patch)
treec5c43680d374f58b487eeeaf18fb7ec6b84ba074 /freebsd/sys/dev/dc
parentBUS_SPACE(9): Use simple memory model for ARM (diff)
downloadrtems-libbsd-af5333e0a02b2295304d4e029b15ee15a4fe2b3a.tar.bz2
Update to FreeBSD 8.4
Diffstat (limited to 'freebsd/sys/dev/dc')
-rw-r--r--freebsd/sys/dev/dc/dcphy.c26
-rw-r--r--freebsd/sys/dev/dc/if_dc.c1695
-rw-r--r--freebsd/sys/dev/dc/if_dcreg.h1325
-rw-r--r--freebsd/sys/dev/dc/pnphy.c33
4 files changed, 1713 insertions, 1366 deletions
diff --git a/freebsd/sys/dev/dc/dcphy.c b/freebsd/sys/dev/dc/dcphy.c
index fcfa7d6c..b1fe5545 100644
--- a/freebsd/sys/dev/dc/dcphy.c
+++ b/freebsd/sys/dev/dc/dcphy.c
@@ -98,7 +98,7 @@ static device_method_t dcphy_methods[] = {
DEVMETHOD(device_attach, dcphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
- { 0, 0 }
+ DEVMETHOD_END
};
static devclass_t dcphy_devclass;
@@ -160,7 +160,7 @@ dcphy_attach(device_t dev)
/*
* Apparently, we can neither isolate nor do loopback.
*/
- sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
+ sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE;
/*dcphy_reset(sc);*/
dc_sc = mii->mii_ifp->if_softc;
@@ -224,17 +224,12 @@ dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
/*dcphy_reset(sc);*/
(void) dcphy_auto(sc);
break;
- case IFM_100_T4:
- /*
- * XXX Not supported as a manual setting right now.
- */
- return (EINVAL);
case IFM_100_TX:
dcphy_reset(sc);
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode |= DC_NETCFG_PORTSEL | DC_NETCFG_PCS |
DC_NETCFG_SCRAMBLER;
- if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
+ if ((ife->ifm_media & IFM_FDX) != 0)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
@@ -243,7 +238,7 @@ dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
case IFM_10_T:
DC_CLRBIT(dc_sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(dc_sc, DC_10BTCTRL, 0xFFFF);
- if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
+ if ((ife->ifm_media & IFM_FDX) != 0)
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3D);
else
DC_SETBIT(dc_sc, DC_10BTCTRL, 0x7F3F);
@@ -251,7 +246,7 @@ dcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
DC_CLRBIT(dc_sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL);
mode &= ~DC_NETCFG_PORTSEL;
mode |= DC_NETCFG_SPEEDSEL;
- if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
+ if ((ife->ifm_media & IFM_FDX) != 0)
mode |= DC_NETCFG_FULLDUPLEX;
else
mode &= ~DC_NETCFG_FULLDUPLEX;
@@ -310,7 +305,7 @@ static void
dcphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
- int reg, anlpar, tstat = 0;
+ int anlpar, tstat;
struct dc_softc *dc_sc;
dc_sc = mii->mii_ifp->if_softc;
@@ -321,13 +316,12 @@ dcphy_status(struct mii_softc *sc)
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
return;
- reg = CSR_READ_4(dc_sc, DC_10BTSTAT);
- if (!(reg & DC_TSTAT_LS10) || !(reg & DC_TSTAT_LS100))
+ tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
+ if (!(tstat & DC_TSTAT_LS10) || !(tstat & DC_TSTAT_LS100))
mii->mii_media_status |= IFM_ACTIVE;
if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {
/* Erg, still trying, I guess... */
- tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);
if ((tstat & DC_TSTAT_ANEGSTAT) != DC_ASTAT_AUTONEGCMP) {
if ((DC_IS_MACRONIX(dc_sc) || DC_IS_PNICII(dc_sc)) &&
(tstat & DC_TSTAT_ANEGSTAT) == DC_ASTAT_DISABLE)
@@ -367,9 +361,9 @@ dcphy_status(struct mii_softc *sc)
* and hope that the user is clever enough to manually
* change the media settings if we're wrong.
*/
- if (!(reg & DC_TSTAT_LS100))
+ if (!(tstat & DC_TSTAT_LS100))
mii->mii_media_active |= IFM_100_TX | IFM_HDX;
- else if (!(reg & DC_TSTAT_LS10))
+ else if (!(tstat & DC_TSTAT_LS10))
mii->mii_media_active |= IFM_10_T | IFM_HDX;
else
mii->mii_media_active |= IFM_NONE;
diff --git a/freebsd/sys/dev/dc/if_dc.c b/freebsd/sys/dev/dc/if_dc.c
index 9b60bc06..37bc2d42 100644
--- a/freebsd/sys/dev/dc/if_dc.c
+++ b/freebsd/sys/dev/dc/if_dc.c
@@ -46,8 +46,8 @@ __FBSDID("$FreeBSD$");
* ASIX Electronics AX88141 (www.asix.com.tw)
* ADMtek AL981 (www.admtek.com.tw)
* ADMtek AN983 (www.admtek.com.tw)
- * ADMtek cardbus AN985 (www.admtek.com.tw)
- * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek cardbus AN985
+ * ADMtek CardBus AN985 (www.admtek.com.tw)
+ * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
* Accton EN1217 (www.accton.com)
* Xircom X3201 (www.xircom.com)
@@ -124,12 +124,13 @@ __FBSDID("$FreeBSD$");
#include <sys/rman.h>
#include <dev/mii/mii.h>
+#include <dev/mii/mii_bitbang.h>
#include <dev/mii/miivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
-#define DC_USEIOSPACE
+#define DC_USEIOSPACE
#include <dev/dc/if_dcreg.h>
@@ -167,7 +168,7 @@ static const struct dc_type dc_devs[] = {
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
"ADMtek AN983 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
- "ADMtek AN985 cardBus 10/100BaseTX or clone" },
+ "ADMtek AN985 CardBus 10/100BaseTX or clone" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
"ADMtek ADM9511 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
@@ -226,6 +227,10 @@ static const struct dc_type dc_devs[] = {
"Linksys PCMPC200 CardBus 10/100" },
{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
"Linksys PCMPC200 CardBus 10/100" },
+ { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0,
+ "ULi M5261 FastEthernet" },
+ { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0,
+ "ULi M5263 FastEthernet" },
{ 0, 0, NULL }
};
@@ -235,7 +240,8 @@ static int dc_detach(device_t);
static int dc_suspend(device_t);
static int dc_resume(device_t);
static const struct dc_type *dc_devtype(device_t);
-static int dc_newbuf(struct dc_softc *, int, int);
+static void dc_discard_rxbuf(struct dc_softc *, int);
+static int dc_newbuf(struct dc_softc *, int);
static int dc_encap(struct dc_softc *, struct mbuf **);
static void dc_pnic_rx_bug_war(struct dc_softc *, int);
static int dc_rx_resync(struct dc_softc *);
@@ -253,34 +259,35 @@ static void dc_stop(struct dc_softc *);
static void dc_watchdog(void *);
static int dc_shutdown(device_t);
static int dc_ifmedia_upd(struct ifnet *);
+static int dc_ifmedia_upd_locked(struct dc_softc *);
static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int dc_dma_alloc(struct dc_softc *);
+static void dc_dma_free(struct dc_softc *);
+static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
+
static void dc_delay(struct dc_softc *);
static void dc_eeprom_idle(struct dc_softc *);
static void dc_eeprom_putbyte(struct dc_softc *, int);
-static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
-static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
-static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
+static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
+static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
+static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
static void dc_eeprom_width(struct dc_softc *);
static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
-static void dc_mii_writebit(struct dc_softc *, int);
-static int dc_mii_readbit(struct dc_softc *);
-static void dc_mii_sync(struct dc_softc *);
-static void dc_mii_send(struct dc_softc *, u_int32_t, int);
-static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
-static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
static int dc_miibus_readreg(device_t, int, int);
static int dc_miibus_writereg(device_t, int, int, int);
static void dc_miibus_statchg(device_t);
static void dc_miibus_mediainit(device_t);
static void dc_setcfg(struct dc_softc *, int);
+static void dc_netcfg_wait(struct dc_softc *);
static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
static uint32_t dc_mchash_be(const uint8_t *);
static void dc_setfilt_21143(struct dc_softc *);
static void dc_setfilt_asix(struct dc_softc *);
static void dc_setfilt_admtek(struct dc_softc *);
+static void dc_setfilt_uli(struct dc_softc *);
static void dc_setfilt_xircom(struct dc_softc *);
static void dc_setfilt(struct dc_softc *);
@@ -289,19 +296,38 @@ static void dc_reset(struct dc_softc *);
static int dc_list_rx_init(struct dc_softc *);
static int dc_list_tx_init(struct dc_softc *);
-static void dc_read_srom(struct dc_softc *, int);
-static void dc_parse_21143_srom(struct dc_softc *);
-static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
-static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
-static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
+static int dc_read_srom(struct dc_softc *, int);
+static int dc_parse_21143_srom(struct dc_softc *);
+static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
+static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
+static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
static void dc_apply_fixup(struct dc_softc *, int);
+static int dc_check_multiport(struct dc_softc *);
+
+/*
+ * MII bit-bang glue
+ */
+static uint32_t dc_mii_bitbang_read(device_t);
+static void dc_mii_bitbang_write(device_t, uint32_t);
+
+static const struct mii_bitbang_ops dc_mii_bitbang_ops = {
+ dc_mii_bitbang_read,
+ dc_mii_bitbang_write,
+ {
+ DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */
+ DC_SIO_MII_DATAIN, /* MII_BIT_MDI */
+ DC_SIO_MII_CLK, /* MII_BIT_MDC */
+ 0, /* MII_BIT_DIR_HOST_PHY */
+ DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */
+ }
+};
#ifdef DC_USEIOSPACE
-#define DC_RES SYS_RES_IOPORT
-#define DC_RID DC_PCI_CFBIO
+#define DC_RES SYS_RES_IOPORT
+#define DC_RID DC_PCI_CFBIO
#else
-#define DC_RES SYS_RES_MEMORY
-#define DC_RID DC_PCI_CFBMA
+#define DC_RES SYS_RES_MEMORY
+#define DC_RID DC_PCI_CFBMA
#endif
static device_method_t dc_methods[] = {
@@ -313,17 +339,13 @@ static device_method_t dc_methods[] = {
DEVMETHOD(device_resume, dc_resume),
DEVMETHOD(device_shutdown, dc_shutdown),
- /* bus interface */
- DEVMETHOD(bus_print_child, bus_generic_print_child),
- DEVMETHOD(bus_driver_added, bus_generic_driver_added),
-
/* MII interface */
DEVMETHOD(miibus_readreg, dc_miibus_readreg),
DEVMETHOD(miibus_writereg, dc_miibus_writereg),
DEVMETHOD(miibus_statchg, dc_miibus_statchg),
DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
- { 0, 0 }
+ DEVMETHOD_END
};
static driver_t dc_driver = {
@@ -334,17 +356,18 @@ static driver_t dc_driver = {
static devclass_t dc_devclass;
-DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
-DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
+DRIVER_MODULE_ORDERED(dc, pci, dc_driver, dc_devclass, NULL, NULL,
+ SI_ORDER_ANY);
+DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
-#define DC_SETBIT(sc, reg, x) \
+#define DC_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
-#define DC_CLRBIT(sc, reg, x) \
+#define DC_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
-#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
-#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
+#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
+#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
static void
dc_delay(struct dc_softc *sc)
@@ -491,10 +514,10 @@ dc_eeprom_putbyte(struct dc_softc *sc, int addr)
* the EEPROM.
*/
static void
-dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
+dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
{
int i;
- u_int32_t r;
+ uint32_t r;
CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
@@ -502,7 +525,7 @@ dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
DELAY(1);
r = CSR_READ_4(sc, DC_SIO);
if (!(r & DC_PN_SIOCTL_BUSY)) {
- *dest = (u_int16_t)(r & 0xFFFF);
+ *dest = (uint16_t)(r & 0xFFFF);
return;
}
}
@@ -514,17 +537,17 @@ dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
* the EEPROM, too.
*/
static void
-dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
+dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
{
SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
addr *= 2;
CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
- *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
+ *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
addr += 1;
CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
- *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
+ *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
}
@@ -533,10 +556,10 @@ dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
* Read a word of data stored in the EEPROM at address 'addr.'
*/
static void
-dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
+dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
{
int i;
- u_int16_t word = 0;
+ uint16_t word = 0;
/* Force EEPROM to idle state. */
dc_eeprom_idle(sc);
@@ -582,7 +605,7 @@ static void
dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
{
int i;
- u_int16_t word = 0, *ptr;
+ uint16_t word = 0, *ptr;
for (i = 0; i < cnt; i++) {
if (DC_IS_PNIC(sc))
@@ -591,7 +614,7 @@ dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
dc_eeprom_getword_xircom(sc, off + i, &word);
else
dc_eeprom_getword(sc, off + i, &word);
- ptr = (u_int16_t *)(dest + (i * 2));
+ ptr = (uint16_t *)(dest + (i * 2));
if (be)
*ptr = be16toh(word);
else
@@ -600,185 +623,45 @@ dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
}
/*
- * The following two routines are taken from the Macronix 98713
- * Application Notes pp.19-21.
- */
-/*
- * Write a bit to the MII bus.
+ * Write the MII serial port for the MII bit-bang module.
*/
static void
-dc_mii_writebit(struct dc_softc *sc, int bit)
+dc_mii_bitbang_write(device_t dev, uint32_t val)
{
- uint32_t reg;
+ struct dc_softc *sc;
- reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0);
- CSR_WRITE_4(sc, DC_SIO, reg);
- CSR_BARRIER_4(sc, DC_SIO,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
+ sc = device_get_softc(dev);
- CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
- CSR_BARRIER_4(sc, DC_SIO,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
- CSR_WRITE_4(sc, DC_SIO, reg);
+ CSR_WRITE_4(sc, DC_SIO, val);
CSR_BARRIER_4(sc, DC_SIO,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
}
/*
- * Read a bit from the MII bus.
+ * Read the MII serial port for the MII bit-bang module.
*/
-static int
-dc_mii_readbit(struct dc_softc *sc)
+static uint32_t
+dc_mii_bitbang_read(device_t dev)
{
- uint32_t reg;
-
- reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR;
- CSR_WRITE_4(sc, DC_SIO, reg);
- CSR_BARRIER_4(sc, DC_SIO,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
- (void)CSR_READ_4(sc, DC_SIO);
- CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
- CSR_BARRIER_4(sc, DC_SIO,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
- CSR_WRITE_4(sc, DC_SIO, reg);
- CSR_BARRIER_4(sc, DC_SIO,
- BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
- if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
- return (1);
-
- return (0);
-}
+ struct dc_softc *sc;
+ uint32_t val;
-/*
- * Sync the PHYs by setting data bit and strobing the clock 32 times.
- */
-static void
-dc_mii_sync(struct dc_softc *sc)
-{
- int i;
+ sc = device_get_softc(dev);
- CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
+ val = CSR_READ_4(sc, DC_SIO);
CSR_BARRIER_4(sc, DC_SIO,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
- DELAY(1);
-
- for (i = 0; i < 32; i++)
- dc_mii_writebit(sc, 1);
-}
-
-/*
- * Clock a series of bits through the MII.
- */
-static void
-dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
-{
- int i;
-
- for (i = (0x1 << (cnt - 1)); i; i >>= 1)
- dc_mii_writebit(sc, bits & i);
-}
-
-/*
- * Read an PHY register through the MII.
- */
-static int
-dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
-{
- int i;
-
- /*
- * Set up frame for RX.
- */
- frame->mii_stdelim = DC_MII_STARTDELIM;
- frame->mii_opcode = DC_MII_READOP;
-
- /*
- * Sync the PHYs.
- */
- dc_mii_sync(sc);
-
- /*
- * Send command/address info.
- */
- dc_mii_send(sc, frame->mii_stdelim, 2);
- dc_mii_send(sc, frame->mii_opcode, 2);
- dc_mii_send(sc, frame->mii_phyaddr, 5);
- dc_mii_send(sc, frame->mii_regaddr, 5);
-
- /*
- * Now try reading data bits. If the turnaround failed, we still
- * need to clock through 16 cycles to keep the PHY(s) in sync.
- */
- frame->mii_turnaround = dc_mii_readbit(sc);
- if (frame->mii_turnaround != 0) {
- for (i = 0; i < 16; i++)
- dc_mii_readbit(sc);
- goto fail;
- }
- for (i = 0x8000; i; i >>= 1) {
- if (dc_mii_readbit(sc))
- frame->mii_data |= i;
- }
-
-fail:
-
- /* Clock the idle bits. */
- dc_mii_writebit(sc, 0);
- dc_mii_writebit(sc, 0);
-
- if (frame->mii_turnaround != 0)
- return (1);
- return (0);
-}
-
-/*
- * Write to a PHY register through the MII.
- */
-static int
-dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
-{
- /*
- * Set up frame for TX.
- */
- frame->mii_stdelim = DC_MII_STARTDELIM;
- frame->mii_opcode = DC_MII_WRITEOP;
- frame->mii_turnaround = DC_MII_TURNAROUND;
-
- /*
- * Sync the PHYs.
- */
- dc_mii_sync(sc);
-
- dc_mii_send(sc, frame->mii_stdelim, 2);
- dc_mii_send(sc, frame->mii_opcode, 2);
- dc_mii_send(sc, frame->mii_phyaddr, 5);
- dc_mii_send(sc, frame->mii_regaddr, 5);
- dc_mii_send(sc, frame->mii_turnaround, 2);
- dc_mii_send(sc, frame->mii_data, 16);
-
- /* Clock the idle bits. */
- dc_mii_writebit(sc, 0);
- dc_mii_writebit(sc, 0);
-
- return (0);
+ return (val);
}
static int
dc_miibus_readreg(device_t dev, int phy, int reg)
{
- struct dc_mii_frame frame;
- struct dc_softc *sc;
+ struct dc_softc *sc;
int i, rval, phy_reg = 0;
sc = device_get_softc(dev);
- bzero(&frame, sizeof(frame));
if (sc->dc_pmode != DC_PMODE_MII) {
if (phy == (MII_NPHY - 1)) {
@@ -822,6 +705,23 @@ dc_miibus_readreg(device_t dev, int phy, int reg)
return (0);
}
+ if (sc->dc_type == DC_TYPE_ULI_M5263) {
+ CSR_WRITE_4(sc, DC_ROM,
+ ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
+ ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
+ DC_ULI_PHY_OP_READ);
+ for (i = 0; i < DC_TIMEOUT; i++) {
+ DELAY(1);
+ rval = CSR_READ_4(sc, DC_ROM);
+ if ((rval & DC_ULI_PHY_OP_DONE) != 0) {
+ return (rval & DC_ULI_PHY_DATA_MASK);
+ }
+ }
+ if (i == DC_TIMEOUT)
+ device_printf(dev, "phy read timed out\n");
+ return (0);
+ }
+
if (DC_IS_COMET(sc)) {
switch (reg) {
case MII_BMCR:
@@ -853,34 +753,29 @@ dc_miibus_readreg(device_t dev, int phy, int reg)
}
rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
-
if (rval == 0xFFFF)
return (0);
return (rval);
}
- frame.mii_phyaddr = phy;
- frame.mii_regaddr = reg;
if (sc->dc_type == DC_TYPE_98713) {
phy_reg = CSR_READ_4(sc, DC_NETCFG);
CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
}
- dc_mii_readreg(sc, &frame);
+ rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
if (sc->dc_type == DC_TYPE_98713)
CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
- return (frame.mii_data);
+ return (rval);
}
static int
dc_miibus_writereg(device_t dev, int phy, int reg, int data)
{
struct dc_softc *sc;
- struct dc_mii_frame frame;
int i, phy_reg = 0;
sc = device_get_softc(dev);
- bzero(&frame, sizeof(frame));
if (DC_IS_PNIC(sc)) {
CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
@@ -892,6 +787,16 @@ dc_miibus_writereg(device_t dev, int phy, int reg, int data)
return (0);
}
+ if (sc->dc_type == DC_TYPE_ULI_M5263) {
+ CSR_WRITE_4(sc, DC_ROM,
+ ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
+ ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
+ ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) |
+ DC_ULI_PHY_OP_WRITE);
+ DELAY(1);
+ return (0);
+ }
+
if (DC_IS_COMET(sc)) {
switch (reg) {
case MII_BMCR:
@@ -926,15 +831,11 @@ dc_miibus_writereg(device_t dev, int phy, int reg, int data)
return (0);
}
- frame.mii_phyaddr = phy;
- frame.mii_regaddr = reg;
- frame.mii_data = data;
-
if (sc->dc_type == DC_TYPE_98713) {
phy_reg = CSR_READ_4(sc, DC_NETCFG);
CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
}
- dc_mii_writereg(sc, &frame);
+ mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data);
if (sc->dc_type == DC_TYPE_98713)
CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
@@ -945,22 +846,34 @@ static void
dc_miibus_statchg(device_t dev)
{
struct dc_softc *sc;
+ struct ifnet *ifp;
struct mii_data *mii;
struct ifmedia *ifm;
sc = device_get_softc(dev);
- if (DC_IS_ADMTEK(sc))
- return;
mii = device_get_softc(sc->dc_miibus);
+ ifp = sc->dc_ifp;
+ if (mii == NULL || ifp == NULL ||
+ (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ return;
+
ifm = &mii->mii_media;
- if (DC_IS_DAVICOM(sc) &&
- IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
+ if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
dc_setcfg(sc, ifm->ifm_media);
- sc->dc_if_media = ifm->ifm_media;
- } else {
+ return;
+ } else if (!DC_IS_ADMTEK(sc))
dc_setcfg(sc, mii->mii_media_active);
- sc->dc_if_media = mii->mii_media_active;
+
+ sc->dc_link = 0;
+ if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+ (IFM_ACTIVE | IFM_AVALID)) {
+ switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ case IFM_10_T:
+ case IFM_100_TX:
+ sc->dc_link = 1;
+ break;
+ }
}
}
@@ -990,9 +903,9 @@ dc_miibus_mediainit(device_t dev)
ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
}
-#define DC_BITS_512 9
-#define DC_BITS_128 7
-#define DC_BITS_64 6
+#define DC_BITS_512 9
+#define DC_BITS_128 7
+#define DC_BITS_64 6
static uint32_t
dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
@@ -1056,7 +969,7 @@ dc_setfilt_21143(struct dc_softc *sc)
{
uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
struct dc_desc *sframe;
- u_int32_t h, *sp;
+ uint32_t h, *sp;
struct ifmultiaddr *ifma;
struct ifnet *ifp;
int i;
@@ -1066,11 +979,11 @@ dc_setfilt_21143(struct dc_softc *sc)
i = sc->dc_cdata.dc_tx_prod;
DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
sc->dc_cdata.dc_tx_cnt++;
- sframe = &sc->dc_ldata->dc_tx_list[i];
+ sframe = &sc->dc_ldata.dc_tx_list[i];
sp = sc->dc_cdata.dc_sbuf;
bzero(sp, DC_SFRAME_LEN);
- sframe->dc_data = htole32(sc->dc_saddr);
+ sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
@@ -1109,6 +1022,9 @@ dc_setfilt_21143(struct dc_softc *sc)
sp[41] = DC_SP_MAC(eaddr[2]);
sframe->dc_status = htole32(DC_TXSTAT_OWN);
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
+ BUS_DMASYNC_PREWRITE);
+ bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
/*
@@ -1129,7 +1045,7 @@ dc_setfilt_admtek(struct dc_softc *sc)
struct ifnet *ifp;
struct ifmultiaddr *ifma;
int h = 0;
- u_int32_t hashes[2] = { 0, 0 };
+ uint32_t hashes[2] = { 0, 0 };
ifp = sc->dc_ifp;
@@ -1190,7 +1106,7 @@ dc_setfilt_asix(struct dc_softc *sc)
struct ifnet *ifp;
struct ifmultiaddr *ifma;
int h = 0;
- u_int32_t hashes[2] = { 0, 0 };
+ uint32_t hashes[2] = { 0, 0 };
ifp = sc->dc_ifp;
@@ -1254,13 +1170,104 @@ dc_setfilt_asix(struct dc_softc *sc)
}
static void
+dc_setfilt_uli(struct dc_softc *sc)
+{
+ uint8_t eaddr[ETHER_ADDR_LEN];
+ struct ifnet *ifp;
+ struct ifmultiaddr *ifma;
+ struct dc_desc *sframe;
+ uint32_t filter, *sp;
+ uint8_t *ma;
+ int i, mcnt;
+
+ ifp = sc->dc_ifp;
+
+ i = sc->dc_cdata.dc_tx_prod;
+ DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
+ sc->dc_cdata.dc_tx_cnt++;
+ sframe = &sc->dc_ldata.dc_tx_list[i];
+ sp = sc->dc_cdata.dc_sbuf;
+ bzero(sp, DC_SFRAME_LEN);
+
+ sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
+ sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
+ DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT);
+
+ sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
+
+ /* Set station address. */
+ bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
+ *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]);
+ *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]);
+ *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]);
+
+ /* Set broadcast address. */
+ *sp++ = DC_SP_MAC(0xFFFF);
+ *sp++ = DC_SP_MAC(0xFFFF);
+ *sp++ = DC_SP_MAC(0xFFFF);
+
+ /* Extract current filter configuration. */
+ filter = CSR_READ_4(sc, DC_NETCFG);
+ filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI);
+
+ /* Now build perfect filters. */
+ mcnt = 0;
+ if_maddr_rlock(ifp);
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ if (mcnt >= DC_ULI_FILTER_NPERF) {
+ filter |= DC_NETCFG_RX_ALLMULTI;
+ break;
+ }
+ ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
+ *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]);
+ *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]);
+ *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]);
+ mcnt++;
+ }
+ if_maddr_runlock(ifp);
+
+ for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) {
+ *sp++ = DC_SP_MAC(0xFFFF);
+ *sp++ = DC_SP_MAC(0xFFFF);
+ *sp++ = DC_SP_MAC(0xFFFF);
+ }
+
+ if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
+ CSR_WRITE_4(sc, DC_NETCFG,
+ filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
+ if (ifp->if_flags & IFF_PROMISC)
+ filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI;
+ if (ifp->if_flags & IFF_ALLMULTI)
+ filter |= DC_NETCFG_RX_ALLMULTI;
+ CSR_WRITE_4(sc, DC_NETCFG,
+ filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
+ if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
+ CSR_WRITE_4(sc, DC_NETCFG, filter);
+
+ sframe->dc_status = htole32(DC_TXSTAT_OWN);
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
+ BUS_DMASYNC_PREWRITE);
+ bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
+ CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
+
+ /*
+ * Wait some time...
+ */
+ DELAY(1000);
+
+ sc->dc_wdog_timer = 5;
+}
+
+static void
dc_setfilt_xircom(struct dc_softc *sc)
{
uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
struct ifnet *ifp;
struct ifmultiaddr *ifma;
struct dc_desc *sframe;
- u_int32_t h, *sp;
+ uint32_t h, *sp;
int i;
ifp = sc->dc_ifp;
@@ -1269,11 +1276,11 @@ dc_setfilt_xircom(struct dc_softc *sc)
i = sc->dc_cdata.dc_tx_prod;
DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
sc->dc_cdata.dc_tx_cnt++;
- sframe = &sc->dc_ldata->dc_tx_list[i];
+ sframe = &sc->dc_ldata.dc_tx_list[i];
sp = sc->dc_cdata.dc_sbuf;
bzero(sp, DC_SFRAME_LEN);
- sframe->dc_data = htole32(sc->dc_saddr);
+ sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
@@ -1313,8 +1320,10 @@ dc_setfilt_xircom(struct dc_softc *sc)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
- ifp->if_drv_flags |= IFF_DRV_RUNNING;
sframe->dc_status = htole32(DC_TXSTAT_OWN);
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
+ BUS_DMASYNC_PREWRITE);
+ bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
/*
@@ -1339,10 +1348,39 @@ dc_setfilt(struct dc_softc *sc)
if (DC_IS_ADMTEK(sc))
dc_setfilt_admtek(sc);
+ if (DC_IS_ULI(sc))
+ dc_setfilt_uli(sc);
+
if (DC_IS_XIRCOM(sc))
dc_setfilt_xircom(sc);
}
+static void
+dc_netcfg_wait(struct dc_softc *sc)
+{
+ uint32_t isr;
+ int i;
+
+ for (i = 0; i < DC_TIMEOUT; i++) {
+ isr = CSR_READ_4(sc, DC_ISR);
+ if (isr & DC_ISR_TX_IDLE &&
+ ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
+ (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
+ break;
+ DELAY(10);
+ }
+ if (i == DC_TIMEOUT) {
+ if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
+ device_printf(sc->dc_dev,
+ "%s: failed to force tx to idle state\n", __func__);
+ if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
+ (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
+ !DC_HAS_BROKEN_RXSTATE(sc))
+ device_printf(sc->dc_dev,
+ "%s: failed to force rx to idle state\n", __func__);
+ }
+}
+
/*
* In order to fiddle with the 'full-duplex' and '100Mbps' bits in
* the netconfig register, we first have to put the transmit and/or
@@ -1351,8 +1389,7 @@ dc_setfilt(struct dc_softc *sc)
static void
dc_setcfg(struct dc_softc *sc, int media)
{
- int i, restart = 0, watchdogreg;
- u_int32_t isr;
+ int restart = 0, watchdogreg;
if (IFM_SUBTYPE(media) == IFM_NONE)
return;
@@ -1360,28 +1397,7 @@ dc_setcfg(struct dc_softc *sc, int media)
if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
restart = 1;
DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
-
- for (i = 0; i < DC_TIMEOUT; i++) {
- isr = CSR_READ_4(sc, DC_ISR);
- if (isr & DC_ISR_TX_IDLE &&
- ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
- (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
- break;
- DELAY(10);
- }
-
- if (i == DC_TIMEOUT) {
- if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
- device_printf(sc->dc_dev,
- "%s: failed to force tx to idle state\n",
- __func__);
- if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
- (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
- !DC_HAS_BROKEN_RXSTATE(sc))
- device_printf(sc->dc_dev,
- "%s: failed to force rx to idle state\n",
- __func__);
- }
+ dc_netcfg_wait(sc);
}
if (IFM_SUBTYPE(media) == IFM_100_TX) {
@@ -1405,8 +1421,6 @@ dc_setcfg(struct dc_softc *sc, int media)
if (!DC_IS_DAVICOM(sc))
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
- if (DC_IS_INTEL(sc))
- dc_apply_fixup(sc, IFM_AUTO);
} else {
if (DC_IS_PNIC(sc)) {
DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
@@ -1416,10 +1430,6 @@ dc_setcfg(struct dc_softc *sc, int media)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
- if (DC_IS_INTEL(sc))
- dc_apply_fixup(sc,
- (media & IFM_GMASK) == IFM_FDX ?
- IFM_100_TX | IFM_FDX : IFM_100_TX);
}
}
@@ -1443,8 +1453,6 @@ dc_setcfg(struct dc_softc *sc, int media)
if (!DC_IS_DAVICOM(sc))
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
- if (DC_IS_INTEL(sc))
- dc_apply_fixup(sc, IFM_AUTO);
} else {
if (DC_IS_PNIC(sc)) {
DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
@@ -1464,9 +1472,6 @@ dc_setcfg(struct dc_softc *sc, int media)
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
DC_CLRBIT(sc, DC_10BTCTRL,
DC_TCTL_AUTONEGENBL);
- dc_apply_fixup(sc,
- (media & IFM_GMASK) == IFM_FDX ?
- IFM_10_T | IFM_FDX : IFM_10_T);
DELAY(20000);
}
}
@@ -1514,7 +1519,7 @@ dc_reset(struct dc_softc *sc)
}
if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
- DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) {
+ DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) {
DELAY(10000);
DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
i = 0;
@@ -1538,7 +1543,7 @@ dc_reset(struct dc_softc *sc)
*/
if (DC_IS_INTEL(sc)) {
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
- CSR_WRITE_4(sc, DC_10BTCTRL, 0);
+ CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF);
CSR_WRITE_4(sc, DC_WATCHDOG, 0);
}
}
@@ -1547,8 +1552,8 @@ static const struct dc_type *
dc_devtype(device_t dev)
{
const struct dc_type *t;
- u_int32_t devid;
- u_int8_t rev;
+ uint32_t devid;
+ uint8_t rev;
t = dc_devs;
devid = pci_get_devid(dev);
@@ -1591,9 +1596,9 @@ static void
dc_apply_fixup(struct dc_softc *sc, int media)
{
struct dc_mediainfo *m;
- u_int8_t *p;
+ uint8_t *p;
int i;
- u_int32_t reg;
+ uint32_t reg;
m = sc->dc_mi;
@@ -1617,12 +1622,16 @@ dc_apply_fixup(struct dc_softc *sc, int media)
}
}
-static void
+static int
dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
{
struct dc_mediainfo *m;
m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (m == NULL) {
+ device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
+ return (ENOMEM);
+ }
switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
case DC_SIA_CODE_10BT:
m->dc_media = IFM_10_T;
@@ -1648,25 +1657,30 @@ dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
if (l->dc_sia_code & DC_SIA_CODE_EXT) {
m->dc_gp_len = 2;
m->dc_gp_ptr =
- (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
+ (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
} else {
m->dc_gp_len = 2;
m->dc_gp_ptr =
- (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
+ (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
}
m->dc_next = sc->dc_mi;
sc->dc_mi = m;
sc->dc_pmode = DC_PMODE_SIA;
+ return (0);
}
-static void
+static int
dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
{
struct dc_mediainfo *m;
m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (m == NULL) {
+ device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
+ return (ENOMEM);
+ }
if (l->dc_sym_code == DC_SYM_CODE_100BT)
m->dc_media = IFM_100_TX;
@@ -1674,26 +1688,31 @@ dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
m->dc_media = IFM_100_TX | IFM_FDX;
m->dc_gp_len = 2;
- m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
+ m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
m->dc_next = sc->dc_mi;
sc->dc_mi = m;
sc->dc_pmode = DC_PMODE_SYM;
+ return (0);
}
-static void
+static int
dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
{
struct dc_mediainfo *m;
- u_int8_t *p;
+ uint8_t *p;
m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (m == NULL) {
+ device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
+ return (ENOMEM);
+ }
/* We abuse IFM_AUTO to represent MII. */
m->dc_media = IFM_AUTO;
m->dc_gp_len = l->dc_gpr_len;
- p = (u_int8_t *)l;
+ p = (uint8_t *)l;
p += sizeof(struct dc_eblock_mii);
m->dc_gp_ptr = p;
p += 2 * l->dc_gpr_len;
@@ -1703,24 +1722,30 @@ dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
m->dc_next = sc->dc_mi;
sc->dc_mi = m;
+ return (0);
}
-static void
+static int
dc_read_srom(struct dc_softc *sc, int bits)
{
int size;
- size = 2 << bits;
- sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
+ size = DC_ROM_SIZE(bits);
+ sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (sc->dc_srom == NULL) {
+ device_printf(sc->dc_dev, "Could not allocate SROM buffer\n");
+ return (ENOMEM);
+ }
dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
+ return (0);
}
-static void
+static int
dc_parse_21143_srom(struct dc_softc *sc)
{
struct dc_leaf_hdr *lhdr;
struct dc_eblock_hdr *hdr;
- int have_mii, i, loff;
+ int error, have_mii, i, loff;
char *ptr;
have_mii = 0;
@@ -1747,20 +1772,21 @@ dc_parse_21143_srom(struct dc_softc *sc)
*/
ptr = (char *)lhdr;
ptr += sizeof(struct dc_leaf_hdr) - 1;
+ error = 0;
for (i = 0; i < lhdr->dc_mcnt; i++) {
hdr = (struct dc_eblock_hdr *)ptr;
switch (hdr->dc_type) {
case DC_EBLOCK_MII:
- dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
+ error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
break;
case DC_EBLOCK_SIA:
if (! have_mii)
- dc_decode_leaf_sia(sc,
+ error = dc_decode_leaf_sia(sc,
(struct dc_eblock_sia *)hdr);
break;
case DC_EBLOCK_SYM:
if (! have_mii)
- dc_decode_leaf_sym(sc,
+ error = dc_decode_leaf_sym(sc,
(struct dc_eblock_sym *)hdr);
break;
default:
@@ -1770,12 +1796,13 @@ dc_parse_21143_srom(struct dc_softc *sc)
ptr += (hdr->dc_len & 0x7F);
ptr++;
}
+ return (error);
}
static void
dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
- u_int32_t *paddr;
+ bus_addr_t *paddr;
KASSERT(nseg == 1,
("%s: wrong number of segments (%d)", __func__, nseg));
@@ -1783,6 +1810,208 @@ dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
*paddr = segs->ds_addr;
}
+static int
+dc_dma_alloc(struct dc_softc *sc)
+{
+ int error, i;
+
+ error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0,
+ BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
+ BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
+ NULL, NULL, &sc->dc_ptag);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to allocate parent DMA tag\n");
+ goto fail;
+ }
+
+ /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
+ error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1,
+ DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag);
+ if (error) {
+ device_printf(sc->dc_dev, "failed to create RX list DMA tag\n");
+ goto fail;
+ }
+
+ error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1,
+ DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag);
+ if (error) {
+ device_printf(sc->dc_dev, "failed to create TX list DMA tag\n");
+ goto fail;
+ }
+
+ /* RX descriptor list. */
+ error = bus_dmamem_alloc(sc->dc_rx_ltag,
+ (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT |
+ BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to allocate DMA'able memory for RX list\n");
+ goto fail;
+ }
+ error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap,
+ sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr,
+ &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to load DMA'able memory for RX list\n");
+ goto fail;
+ }
+ /* TX descriptor list. */
+ error = bus_dmamem_alloc(sc->dc_tx_ltag,
+ (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT |
+ BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to allocate DMA'able memory for TX list\n");
+ goto fail;
+ }
+ error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap,
+ sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr,
+ &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "cannot load DMA'able memory for TX list\n");
+ goto fail;
+ }
+
+ /*
+ * Allocate a busdma tag and DMA safe memory for the multicast
+ * setup frame.
+ */
+ error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+ DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
+ 0, NULL, NULL, &sc->dc_stag);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to create DMA tag for setup frame\n");
+ goto fail;
+ }
+ error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
+ BUS_DMA_NOWAIT, &sc->dc_smap);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to allocate DMA'able memory for setup frame\n");
+ goto fail;
+ }
+ error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
+ DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "cannot load DMA'able memory for setup frame\n");
+ goto fail;
+ }
+
+ /* Allocate a busdma tag for RX mbufs. */
+ error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+ MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag);
+ if (error) {
+ device_printf(sc->dc_dev, "failed to create RX mbuf tag\n");
+ goto fail;
+ }
+
+ /* Allocate a busdma tag for TX mbufs. */
+ error = bus_dma_tag_create(sc->dc_ptag, 1, 0,
+ BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
+ MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
+ 0, NULL, NULL, &sc->dc_tx_mtag);
+ if (error) {
+ device_printf(sc->dc_dev, "failed to create TX mbuf tag\n");
+ goto fail;
+ }
+
+ /* Create the TX/RX busdma maps. */
+ for (i = 0; i < DC_TX_LIST_CNT; i++) {
+ error = bus_dmamap_create(sc->dc_tx_mtag, 0,
+ &sc->dc_cdata.dc_tx_map[i]);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to create TX mbuf dmamap\n");
+ goto fail;
+ }
+ }
+ for (i = 0; i < DC_RX_LIST_CNT; i++) {
+ error = bus_dmamap_create(sc->dc_rx_mtag, 0,
+ &sc->dc_cdata.dc_rx_map[i]);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to create RX mbuf dmamap\n");
+ goto fail;
+ }
+ }
+ error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap);
+ if (error) {
+ device_printf(sc->dc_dev,
+ "failed to create spare RX mbuf dmamap\n");
+ goto fail;
+ }
+
+fail:
+ return (error);
+}
+
+static void
+dc_dma_free(struct dc_softc *sc)
+{
+ int i;
+
+ /* RX buffers. */
+ if (sc->dc_rx_mtag != NULL) {
+ for (i = 0; i < DC_RX_LIST_CNT; i++) {
+ if (sc->dc_cdata.dc_rx_map[i] != NULL)
+ bus_dmamap_destroy(sc->dc_rx_mtag,
+ sc->dc_cdata.dc_rx_map[i]);
+ }
+ if (sc->dc_sparemap != NULL)
+ bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap);
+ bus_dma_tag_destroy(sc->dc_rx_mtag);
+ }
+
+ /* TX buffers. */
+ if (sc->dc_rx_mtag != NULL) {
+ for (i = 0; i < DC_TX_LIST_CNT; i++) {
+ if (sc->dc_cdata.dc_tx_map[i] != NULL)
+ bus_dmamap_destroy(sc->dc_tx_mtag,
+ sc->dc_cdata.dc_tx_map[i]);
+ }
+ bus_dma_tag_destroy(sc->dc_tx_mtag);
+ }
+
+ /* RX descriptor list. */
+ if (sc->dc_rx_ltag) {
+ if (sc->dc_rx_lmap != NULL)
+ bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap);
+ if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL)
+ bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list,
+ sc->dc_rx_lmap);
+ bus_dma_tag_destroy(sc->dc_rx_ltag);
+ }
+
+ /* TX descriptor list. */
+ if (sc->dc_tx_ltag) {
+ if (sc->dc_tx_lmap != NULL)
+ bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap);
+ if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL)
+ bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list,
+ sc->dc_tx_lmap);
+ bus_dma_tag_destroy(sc->dc_tx_ltag);
+ }
+
+ /* multicast setup frame. */
+ if (sc->dc_stag) {
+ if (sc->dc_smap != NULL)
+ bus_dmamap_unload(sc->dc_stag, sc->dc_smap);
+ if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL)
+ bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf,
+ sc->dc_smap);
+ bus_dma_tag_destroy(sc->dc_stag);
+ }
+}
+
/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
@@ -1791,12 +2020,14 @@ static int
dc_attach(device_t dev)
{
uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
- u_int32_t command;
+ uint32_t command;
struct dc_softc *sc;
struct ifnet *ifp;
- u_int32_t reg, revision;
- int error, i, mac_offset, phy, rid, tmp;
- u_int8_t *mac;
+ struct dc_mediainfo *m;
+ uint32_t reg, revision;
+ uint16_t *srom;
+ int error, mac_offset, n, phy, rid, tmp;
+ uint8_t *mac;
sc = device_get_softc(dev);
sc->dc_dev = dev;
@@ -1836,6 +2067,7 @@ dc_attach(device_t dev)
sc->dc_info = dc_devtype(dev);
revision = pci_get_revid(dev);
+ error = 0;
/* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
if (sc->dc_info->dc_devid !=
DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
@@ -1849,7 +2081,9 @@ dc_attach(device_t dev)
sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
sc->dc_flags |= DC_REDUCED_MII_POLL;
/* Save EEPROM contents so we can parse them later. */
- dc_read_srom(sc, sc->dc_romwidth);
+ error = dc_read_srom(sc, sc->dc_romwidth);
+ if (error != 0)
+ goto fail;
break;
case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
@@ -1868,7 +2102,9 @@ dc_attach(device_t dev)
sc->dc_flags |= DC_TX_USE_TX_INTR;
sc->dc_flags |= DC_TX_ADMTEK_WAR;
sc->dc_pmode = DC_PMODE_MII;
- dc_read_srom(sc, sc->dc_romwidth);
+ error = dc_read_srom(sc, sc->dc_romwidth);
+ if (error != 0)
+ goto fail;
break;
case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983):
case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
@@ -1935,6 +2171,12 @@ dc_attach(device_t dev)
sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
+ if (sc->dc_pnic_rx_buf == NULL) {
+ device_printf(sc->dc_dev,
+ "Could not allocate PNIC RX buffer\n");
+ error = ENOMEM;
+ goto fail;
+ }
if (revision < DC_REVISION_82C169)
sc->dc_pmode = DC_PMODE_SYM;
break;
@@ -1960,7 +2202,24 @@ dc_attach(device_t dev)
sc->dc_flags |= DC_TX_INTR_ALWAYS;
sc->dc_flags |= DC_REDUCED_MII_POLL;
sc->dc_pmode = DC_PMODE_MII;
- dc_read_srom(sc, sc->dc_romwidth);
+ error = dc_read_srom(sc, sc->dc_romwidth);
+ if (error != 0)
+ goto fail;
+ break;
+ case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261):
+ case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263):
+ if (sc->dc_info->dc_devid ==
+ DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261))
+ sc->dc_type = DC_TYPE_ULI_M5261;
+ else
+ sc->dc_type = DC_TYPE_ULI_M5263;
+ /* TX buffers should be aligned on 4 byte boundary. */
+ sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
+ DC_TX_ALIGN;
+ sc->dc_pmode = DC_PMODE_MII;
+ error = dc_read_srom(sc, sc->dc_romwidth);
+ if (error != 0)
+ goto fail;
break;
default:
device_printf(dev, "unknown device: %x\n",
@@ -1991,9 +2250,11 @@ dc_attach(device_t dev)
* The tricky ones are the Macronix/PNIC II and the
* Intel 21143.
*/
- if (DC_IS_INTEL(sc))
- dc_parse_21143_srom(sc);
- else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
+ if (DC_IS_INTEL(sc)) {
+ error = dc_parse_21143_srom(sc);
+ if (error != 0)
+ goto fail;
+ } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
if (sc->dc_type == DC_TYPE_98713)
sc->dc_pmode = DC_PMODE_MII;
else
@@ -2057,101 +2318,70 @@ dc_attach(device_t dev)
}
bcopy(mac, eaddr, ETHER_ADDR_LEN);
break;
+ case DC_TYPE_ULI_M5261:
+ case DC_TYPE_ULI_M5263:
+ srom = (uint16_t *)sc->dc_srom;
+ if (srom == NULL || *srom == 0xFFFF || *srom == 0) {
+ /*
+ * No valid SROM present, read station address
+ * from ID Table.
+ */
+ device_printf(dev,
+ "Reading station address from ID Table.\n");
+ CSR_WRITE_4(sc, DC_BUSCTL, 0x10000);
+ CSR_WRITE_4(sc, DC_SIARESET, 0x01C0);
+ CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
+ CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010);
+ CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
+ CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
+ CSR_WRITE_4(sc, DC_SIARESET, 0x01B0);
+ mac = (uint8_t *)eaddr;
+ for (n = 0; n < ETHER_ADDR_LEN; n++)
+ mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);
+ CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
+ CSR_WRITE_4(sc, DC_BUSCTL, 0x0000);
+ DELAY(10);
+ } else
+ dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3,
+ 0);
+ break;
default:
dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
break;
}
- /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
- error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
- BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
- sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data),
- 0, NULL, NULL, &sc->dc_ltag);
- if (error) {
- device_printf(dev, "failed to allocate busdma tag\n");
- error = ENXIO;
- goto fail;
- }
- error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata,
- BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap);
- if (error) {
- device_printf(dev, "failed to allocate DMA safe memory\n");
- error = ENXIO;
- goto fail;
- }
- error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata,
- sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr,
- BUS_DMA_NOWAIT);
- if (error) {
- device_printf(dev, "cannot get address of the descriptors\n");
- error = ENXIO;
- goto fail;
- }
-
+ bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr));
/*
- * Allocate a busdma tag and DMA safe memory for the multicast
- * setup frame.
+ * If we still have invalid station address, see whether we can
+ * find station address for chip 0. Some multi-port controllers
+ * just store station address for chip 0 if they have a shared
+ * SROM.
*/
- error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
- BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
- DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
- 0, NULL, NULL, &sc->dc_stag);
- if (error) {
- device_printf(dev, "failed to allocate busdma tag\n");
- error = ENXIO;
- goto fail;
- }
- error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
- BUS_DMA_NOWAIT, &sc->dc_smap);
- if (error) {
- device_printf(dev, "failed to allocate DMA safe memory\n");
- error = ENXIO;
- goto fail;
- }
- error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
- DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
- if (error) {
- device_printf(dev, "cannot get address of the descriptors\n");
- error = ENXIO;
- goto fail;
- }
-
- /* Allocate a busdma tag for mbufs. */
- error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
- BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
- MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
- 0, NULL, NULL, &sc->dc_mtag);
- if (error) {
- device_printf(dev, "failed to allocate busdma tag\n");
- error = ENXIO;
- goto fail;
- }
-
- /* Create the TX/RX busdma maps. */
- for (i = 0; i < DC_TX_LIST_CNT; i++) {
- error = bus_dmamap_create(sc->dc_mtag, 0,
- &sc->dc_cdata.dc_tx_map[i]);
- if (error) {
- device_printf(dev, "failed to init TX ring\n");
- error = ENXIO;
- goto fail;
- }
- }
- for (i = 0; i < DC_RX_LIST_CNT; i++) {
- error = bus_dmamap_create(sc->dc_mtag, 0,
- &sc->dc_cdata.dc_rx_map[i]);
- if (error) {
- device_printf(dev, "failed to init RX ring\n");
- error = ENXIO;
+ if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) ||
+ (sc->dc_eaddr[0] == 0xffffffff &&
+ (sc->dc_eaddr[1] & 0xffff) == 0xffff)) {
+ error = dc_check_multiport(sc);
+ if (error == 0) {
+ bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr));
+ /* Extract media information. */
+ if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) {
+ while (sc->dc_mi != NULL) {
+ m = sc->dc_mi->dc_next;
+ free(sc->dc_mi, M_DEVBUF);
+ sc->dc_mi = m;
+ }
+ error = dc_parse_21143_srom(sc);
+ if (error != 0)
+ goto fail;
+ }
+ } else if (error == ENOMEM)
goto fail;
- }
+ else
+ error = 0;
}
- error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap);
- if (error) {
- device_printf(dev, "failed to init RX ring\n");
- error = ENXIO;
+
+ if ((error = dc_dma_alloc(sc)) != 0)
goto fail;
- }
ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
@@ -2225,9 +2455,6 @@ dc_attach(device_t dev)
if (sc->dc_pmode != DC_PMODE_SIA)
sc->dc_pmode = DC_PMODE_SYM;
sc->dc_flags |= DC_21143_NWAY;
- mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
- dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
- MII_OFFSET_ANY, 0);
/*
* For non-MII cards, we need to have the 21143
* drive the LEDs. Except there are some systems
@@ -2238,7 +2465,9 @@ dc_attach(device_t dev)
if (!(pci_get_subvendor(dev) == 0x1033 &&
pci_get_subdevice(dev) == 0x8028))
sc->dc_flags |= DC_TULIP_LEDS;
- error = 0;
+ error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
+ dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
+ MII_OFFSET_ANY, 0);
}
if (error) {
@@ -2300,7 +2529,6 @@ dc_detach(device_t dev)
struct dc_softc *sc;
struct ifnet *ifp;
struct dc_mediainfo *m;
- int i;
sc = device_get_softc(dev);
KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
@@ -2308,7 +2536,7 @@ dc_detach(device_t dev)
ifp = sc->dc_ifp;
#ifdef DEVICE_POLLING
- if (ifp->if_capenable & IFCAP_POLLING)
+ if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
ether_poll_deregister(ifp);
#endif
@@ -2332,30 +2560,10 @@ dc_detach(device_t dev)
if (sc->dc_res)
bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
- if (ifp)
+ if (ifp != NULL)
if_free(ifp);
- if (sc->dc_cdata.dc_sbuf != NULL)
- bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap);
- if (sc->dc_ldata != NULL)
- bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap);
- if (sc->dc_mtag) {
- for (i = 0; i < DC_TX_LIST_CNT; i++)
- if (sc->dc_cdata.dc_tx_map[i] != NULL)
- bus_dmamap_destroy(sc->dc_mtag,
- sc->dc_cdata.dc_tx_map[i]);
- for (i = 0; i < DC_RX_LIST_CNT; i++)
- if (sc->dc_cdata.dc_rx_map[i] != NULL)
- bus_dmamap_destroy(sc->dc_mtag,
- sc->dc_cdata.dc_rx_map[i]);
- bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap);
- }
- if (sc->dc_stag)
- bus_dma_tag_destroy(sc->dc_stag);
- if (sc->dc_mtag)
- bus_dma_tag_destroy(sc->dc_mtag);
- if (sc->dc_ltag)
- bus_dma_tag_destroy(sc->dc_ltag);
+ dc_dma_free(sc);
free(sc->dc_pnic_rx_buf, M_DEVBUF);
@@ -2382,25 +2590,26 @@ dc_list_tx_init(struct dc_softc *sc)
int i, nexti;
cd = &sc->dc_cdata;
- ld = sc->dc_ldata;
+ ld = &sc->dc_ldata;
for (i = 0; i < DC_TX_LIST_CNT; i++) {
if (i == DC_TX_LIST_CNT - 1)
nexti = 0;
else
nexti = i + 1;
+ ld->dc_tx_list[i].dc_status = 0;
+ ld->dc_tx_list[i].dc_ctl = 0;
+ ld->dc_tx_list[i].dc_data = 0;
ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
cd->dc_tx_chain[i] = NULL;
- ld->dc_tx_list[i].dc_data = 0;
- ld->dc_tx_list[i].dc_ctl = 0;
}
cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
- bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
+ cd->dc_tx_pkts = 0;
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
return (0);
}
-
/*
* Initialize the RX descriptors and allocate mbufs for them. Note that
* we arrange the descriptors in a closed ring, so that the last descriptor
@@ -2414,10 +2623,10 @@ dc_list_rx_init(struct dc_softc *sc)
int i, nexti;
cd = &sc->dc_cdata;
- ld = sc->dc_ldata;
+ ld = &sc->dc_ldata;
for (i = 0; i < DC_RX_LIST_CNT; i++) {
- if (dc_newbuf(sc, i, 1) != 0)
+ if (dc_newbuf(sc, i) != 0)
return (ENOBUFS);
if (i == DC_RX_LIST_CNT - 1)
nexti = 0;
@@ -2427,7 +2636,7 @@ dc_list_rx_init(struct dc_softc *sc)
}
cd->dc_rx_prod = 0;
- bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
+ bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
return (0);
}
@@ -2436,23 +2645,18 @@ dc_list_rx_init(struct dc_softc *sc)
* Initialize an RX descriptor and attach an MBUF cluster.
*/
static int
-dc_newbuf(struct dc_softc *sc, int i, int alloc)
+dc_newbuf(struct dc_softc *sc, int i)
{
- struct mbuf *m_new;
- bus_dmamap_t tmp;
+ struct mbuf *m;
+ bus_dmamap_t map;
bus_dma_segment_t segs[1];
int error, nseg;
- if (alloc) {
- m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
- if (m_new == NULL)
- return (ENOBUFS);
- } else {
- m_new = sc->dc_cdata.dc_rx_chain[i];
- m_new->m_data = m_new->m_ext.ext_buf;
- }
- m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
- m_adj(m_new, sizeof(u_int64_t));
+ m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+ if (m == NULL)
+ return (ENOBUFS);
+ m->m_len = m->m_pkthdr.len = MCLBYTES;
+ m_adj(m, sizeof(u_int64_t));
/*
* If this is a PNIC chip, zero the buffer. This is part
@@ -2460,31 +2664,31 @@ dc_newbuf(struct dc_softc *sc, int i, int alloc)
* 82c169 chips.
*/
if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
- bzero(mtod(m_new, char *), m_new->m_len);
+ bzero(mtod(m, char *), m->m_len);
- /* No need to remap the mbuf if we're reusing it. */
- if (alloc) {
- error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap,
- m_new, segs, &nseg, 0);
- if (error) {
- m_freem(m_new);
- return (error);
- }
- KASSERT(nseg == 1,
- ("%s: wrong number of segments (%d)", __func__, nseg));
- sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr);
- bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]);
- tmp = sc->dc_cdata.dc_rx_map[i];
- sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
- sc->dc_sparemap = tmp;
- sc->dc_cdata.dc_rx_chain[i] = m_new;
- }
-
- sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
- sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
- bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
+ error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap,
+ m, segs, &nseg, 0);
+ if (error) {
+ m_freem(m);
+ return (error);
+ }
+ KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__,
+ nseg));
+ if (sc->dc_cdata.dc_rx_chain[i] != NULL)
+ bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]);
+
+ map = sc->dc_cdata.dc_rx_map[i];
+ sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
+ sc->dc_sparemap = map;
+ sc->dc_cdata.dc_rx_chain[i] = m;
+ bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
BUS_DMASYNC_PREREAD);
- bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
+
+ sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
+ sc->dc_ldata.dc_rx_list[i].dc_data =
+ htole32(DC_ADDR_LO(segs[0].ds_addr));
+ sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
+ bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
return (0);
}
@@ -2541,7 +2745,7 @@ dc_newbuf(struct dc_softc *sc, int i, int alloc)
* the time.
*/
-#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
+#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
static void
dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
{
@@ -2550,16 +2754,16 @@ dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
struct mbuf *m = NULL;
unsigned char *ptr;
int i, total_len;
- u_int32_t rxstat = 0;
+ uint32_t rxstat = 0;
i = sc->dc_pnic_rx_bug_save;
- cur_rx = &sc->dc_ldata->dc_rx_list[idx];
+ cur_rx = &sc->dc_ldata.dc_rx_list[idx];
ptr = sc->dc_pnic_rx_buf;
bzero(ptr, DC_RXLEN * 5);
/* Copy all the bytes from the bogus buffers. */
while (1) {
- c = &sc->dc_ldata->dc_rx_list[i];
+ c = &sc->dc_ldata.dc_rx_list[i];
rxstat = le32toh(c->dc_status);
m = sc->dc_cdata.dc_rx_chain[i];
bcopy(mtod(m, char *), ptr, DC_RXLEN);
@@ -2567,7 +2771,7 @@ dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
/* If this is the last buffer, break out. */
if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
break;
- dc_newbuf(sc, i, 0);
+ dc_discard_rxbuf(sc, i);
DC_INC(i, DC_RX_LIST_CNT);
}
@@ -2592,7 +2796,6 @@ dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
* the status word to make it look like a successful
* frame reception.
*/
- dc_newbuf(sc, i, 0);
bcopy(ptr, mtod(m, char *), total_len);
cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
}
@@ -2617,7 +2820,7 @@ dc_rx_resync(struct dc_softc *sc)
pos = sc->dc_cdata.dc_rx_prod;
for (i = 0; i < DC_RX_LIST_CNT; i++) {
- cur_rx = &sc->dc_ldata->dc_rx_list[pos];
+ cur_rx = &sc->dc_ldata.dc_rx_list[pos];
if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
break;
DC_INC(pos, DC_RX_LIST_CNT);
@@ -2633,6 +2836,22 @@ dc_rx_resync(struct dc_softc *sc)
return (EAGAIN);
}
+static void
+dc_discard_rxbuf(struct dc_softc *sc, int i)
+{
+ struct mbuf *m;
+
+ if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
+ m = sc->dc_cdata.dc_rx_chain[i];
+ bzero(mtod(m, char *), m->m_len);
+ }
+
+ sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
+ sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
+ bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD |
+ BUS_DMASYNC_PREWRITE);
+}
+
/*
* A frame has been uploaded: pass the resulting mbuf chain up to
* the higher level protocols.
@@ -2640,22 +2859,22 @@ dc_rx_resync(struct dc_softc *sc)
static int
dc_rxeof(struct dc_softc *sc)
{
- struct mbuf *m, *m0;
+ struct mbuf *m;
struct ifnet *ifp;
struct dc_desc *cur_rx;
int i, total_len, rx_npkts;
- u_int32_t rxstat;
+ uint32_t rxstat;
DC_LOCK_ASSERT(sc);
ifp = sc->dc_ifp;
- i = sc->dc_cdata.dc_rx_prod;
- total_len = 0;
rx_npkts = 0;
- bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
- while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) &
- DC_RXSTAT_OWN)) {
+ bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD |
+ BUS_DMASYNC_POSTWRITE);
+ for (i = sc->dc_cdata.dc_rx_prod;
+ (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
+ DC_INC(i, DC_RX_LIST_CNT)) {
#ifdef DEVICE_POLLING
if (ifp->if_capenable & IFCAP_POLLING) {
if (sc->rxcycles <= 0)
@@ -2663,21 +2882,22 @@ dc_rxeof(struct dc_softc *sc)
sc->rxcycles--;
}
#endif
- cur_rx = &sc->dc_ldata->dc_rx_list[i];
+ cur_rx = &sc->dc_ldata.dc_rx_list[i];
rxstat = le32toh(cur_rx->dc_status);
+ if ((rxstat & DC_RXSTAT_OWN) != 0)
+ break;
m = sc->dc_cdata.dc_rx_chain[i];
- bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i],
+ bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
BUS_DMASYNC_POSTREAD);
total_len = DC_RXBYTES(rxstat);
+ rx_npkts++;
if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
if (rxstat & DC_RXSTAT_FIRSTFRAG)
sc->dc_pnic_rx_bug_save = i;
- if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
- DC_INC(i, DC_RX_LIST_CNT);
+ if ((rxstat & DC_RXSTAT_LASTFRAG) == 0)
continue;
- }
dc_pnic_rx_bug_war(sc, i);
rxstat = le32toh(cur_rx->dc_status);
total_len = DC_RXBYTES(rxstat);
@@ -2699,11 +2919,11 @@ dc_rxeof(struct dc_softc *sc)
ifp->if_ierrors++;
if (rxstat & DC_RXSTAT_COLLSEEN)
ifp->if_collisions++;
- dc_newbuf(sc, i, 0);
- if (rxstat & DC_RXSTAT_CRCERR) {
- DC_INC(i, DC_RX_LIST_CNT);
+ dc_discard_rxbuf(sc, i);
+ if (rxstat & DC_RXSTAT_CRCERR)
continue;
- } else {
+ else {
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
dc_init_locked(sc);
return (rx_npkts);
}
@@ -2722,29 +2942,32 @@ dc_rxeof(struct dc_softc *sc)
* if the allocation fails, then use m_devget and leave the
* existing buffer in the receive ring.
*/
- if (dc_newbuf(sc, i, 1) == 0) {
- m->m_pkthdr.rcvif = ifp;
- m->m_pkthdr.len = m->m_len = total_len;
- DC_INC(i, DC_RX_LIST_CNT);
- } else
-#endif
+ if (dc_newbuf(sc, i) != 0) {
+ dc_discard_rxbuf(sc, i);
+ ifp->if_iqdrops++;
+ continue;
+ }
+ m->m_pkthdr.rcvif = ifp;
+ m->m_pkthdr.len = m->m_len = total_len;
+#else
{
+ struct mbuf *m0;
+
m0 = m_devget(mtod(m, char *), total_len,
ETHER_ALIGN, ifp, NULL);
- dc_newbuf(sc, i, 0);
- DC_INC(i, DC_RX_LIST_CNT);
+ dc_discard_rxbuf(sc, i);
if (m0 == NULL) {
- ifp->if_ierrors++;
+ ifp->if_iqdrops++;
continue;
}
m = m0;
}
+#endif
ifp->if_ipackets++;
DC_UNLOCK(sc);
(*ifp->if_input)(ifp, m);
DC_LOCK(sc);
- rx_npkts++;
}
sc->dc_cdata.dc_rx_prod = i;
@@ -2758,10 +2981,13 @@ dc_rxeof(struct dc_softc *sc)
static void
dc_txeof(struct dc_softc *sc)
{
- struct dc_desc *cur_tx = NULL;
+ struct dc_desc *cur_tx;
struct ifnet *ifp;
- int idx;
- u_int32_t ctl, txstat;
+ int idx, setup;
+ uint32_t ctl, txstat;
+
+ if (sc->dc_cdata.dc_tx_cnt == 0)
+ return;
ifp = sc->dc_ifp;
@@ -2769,36 +2995,40 @@ dc_txeof(struct dc_softc *sc)
* Go through our tx list and free mbufs for those
* frames that have been transmitted.
*/
- bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD);
- idx = sc->dc_cdata.dc_tx_cons;
- while (idx != sc->dc_cdata.dc_tx_prod) {
-
- cur_tx = &sc->dc_ldata->dc_tx_list[idx];
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD |
+ BUS_DMASYNC_POSTWRITE);
+ setup = 0;
+ for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod;
+ DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) {
+ cur_tx = &sc->dc_ldata.dc_tx_list[idx];
txstat = le32toh(cur_tx->dc_status);
ctl = le32toh(cur_tx->dc_ctl);
if (txstat & DC_TXSTAT_OWN)
break;
- if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) {
- if (ctl & DC_TXCTL_SETUP) {
- /*
- * Yes, the PNIC is so brain damaged
- * that it will sometimes generate a TX
- * underrun error while DMAing the RX
- * filter setup frame. If we detect this,
- * we have to send the setup frame again,
- * or else the filter won't be programmed
- * correctly.
- */
- if (DC_IS_PNIC(sc)) {
- if (txstat & DC_TXSTAT_ERRSUM)
- dc_setfilt(sc);
- }
- sc->dc_cdata.dc_tx_chain[idx] = NULL;
+ if (sc->dc_cdata.dc_tx_chain[idx] == NULL)
+ continue;
+
+ if (ctl & DC_TXCTL_SETUP) {
+ cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP);
+ setup++;
+ bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
+ BUS_DMASYNC_POSTWRITE);
+ /*
+ * Yes, the PNIC is so brain damaged
+ * that it will sometimes generate a TX
+ * underrun error while DMAing the RX
+ * filter setup frame. If we detect this,
+ * we have to send the setup frame again,
+ * or else the filter won't be programmed
+ * correctly.
+ */
+ if (DC_IS_PNIC(sc)) {
+ if (txstat & DC_TXSTAT_ERRSUM)
+ dc_setfilt(sc);
}
- sc->dc_cdata.dc_tx_cnt--;
- DC_INC(idx, DC_TX_LIST_CNT);
+ sc->dc_cdata.dc_tx_chain[idx] = NULL;
continue;
}
@@ -2831,34 +3061,30 @@ dc_txeof(struct dc_softc *sc)
if (txstat & DC_TXSTAT_LATECOLL)
ifp->if_collisions++;
if (!(txstat & DC_TXSTAT_UNDERRUN)) {
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
dc_init_locked(sc);
return;
}
- }
-
+ } else
+ ifp->if_opackets++;
ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
- ifp->if_opackets++;
- if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
- bus_dmamap_sync(sc->dc_mtag,
- sc->dc_cdata.dc_tx_map[idx],
- BUS_DMASYNC_POSTWRITE);
- bus_dmamap_unload(sc->dc_mtag,
- sc->dc_cdata.dc_tx_map[idx]);
- m_freem(sc->dc_cdata.dc_tx_chain[idx]);
- sc->dc_cdata.dc_tx_chain[idx] = NULL;
- }
-
- sc->dc_cdata.dc_tx_cnt--;
- DC_INC(idx, DC_TX_LIST_CNT);
+ bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
+ m_freem(sc->dc_cdata.dc_tx_chain[idx]);
+ sc->dc_cdata.dc_tx_chain[idx] = NULL;
}
sc->dc_cdata.dc_tx_cons = idx;
- if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD)
+ if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-
- if (sc->dc_cdata.dc_tx_cnt == 0)
- sc->dc_wdog_timer = 0;
+ if (sc->dc_cdata.dc_tx_cnt == 0)
+ sc->dc_wdog_timer = 0;
+ }
+ if (setup > 0)
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
}
static void
@@ -2867,13 +3093,20 @@ dc_tick(void *xsc)
struct dc_softc *sc;
struct mii_data *mii;
struct ifnet *ifp;
- u_int32_t r;
+ uint32_t r;
sc = xsc;
DC_LOCK_ASSERT(sc);
ifp = sc->dc_ifp;
mii = device_get_softc(sc->dc_miibus);
+ /*
+ * Reclaim transmitted frames for controllers that do
+ * not generate TX completion interrupt for every frame.
+ */
+ if (sc->dc_flags & DC_TX_USE_TX_INTR)
+ dc_txeof(sc);
+
if (sc->dc_flags & DC_REDUCED_MII_POLL) {
if (sc->dc_flags & DC_21143_NWAY) {
r = CSR_READ_4(sc, DC_10BTSTAT);
@@ -2896,11 +3129,8 @@ dc_tick(void *xsc)
*/
if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
- sc->dc_cdata.dc_tx_cnt == 0) {
+ sc->dc_cdata.dc_tx_cnt == 0)
mii_tick(mii);
- if (!(mii->mii_media_status & IFM_ACTIVE))
- sc->dc_link = 0;
- }
}
} else
mii_tick(mii);
@@ -2924,12 +3154,8 @@ dc_tick(void *xsc)
* that time, packets will stay in the send queue, and once the
* link comes up, they will be flushed out to the wire.
*/
- if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
- IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
- sc->dc_link++;
- if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
- dc_start_locked(ifp);
- }
+ if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ dc_start_locked(ifp);
if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
@@ -2944,47 +3170,57 @@ dc_tick(void *xsc)
static void
dc_tx_underrun(struct dc_softc *sc)
{
- u_int32_t isr;
- int i;
+ uint32_t netcfg, isr;
+ int i, reinit;
- if (DC_IS_DAVICOM(sc))
- dc_init_locked(sc);
+ reinit = 0;
+ netcfg = CSR_READ_4(sc, DC_NETCFG);
+ device_printf(sc->dc_dev, "TX underrun -- ");
+ if ((sc->dc_flags & DC_TX_STORENFWD) == 0) {
+ if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) {
+ printf("using store and forward mode\n");
+ netcfg |= DC_NETCFG_STORENFWD;
+ } else {
+ printf("increasing TX threshold\n");
+ sc->dc_txthresh += DC_TXTHRESH_INC;
+ netcfg &= ~DC_NETCFG_TX_THRESH;
+ netcfg |= sc->dc_txthresh;
+ }
- if (DC_IS_INTEL(sc)) {
- /*
- * The real 21143 requires that the transmitter be idle
- * in order to change the transmit threshold or store
- * and forward state.
- */
- DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
+ if (DC_IS_INTEL(sc)) {
+ /*
+ * The real 21143 requires that the transmitter be idle
+ * in order to change the transmit threshold or store
+ * and forward state.
+ */
+ CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON);
- for (i = 0; i < DC_TIMEOUT; i++) {
- isr = CSR_READ_4(sc, DC_ISR);
- if (isr & DC_ISR_TX_IDLE)
- break;
- DELAY(10);
- }
- if (i == DC_TIMEOUT) {
- device_printf(sc->dc_dev,
- "%s: failed to force tx to idle state\n",
- __func__);
- dc_init_locked(sc);
+ for (i = 0; i < DC_TIMEOUT; i++) {
+ isr = CSR_READ_4(sc, DC_ISR);
+ if (isr & DC_ISR_TX_IDLE)
+ break;
+ DELAY(10);
+ }
+ if (i == DC_TIMEOUT) {
+ device_printf(sc->dc_dev,
+ "%s: failed to force tx to idle state\n",
+ __func__);
+ reinit++;
+ }
}
+ } else {
+ printf("resetting\n");
+ reinit++;
}
- device_printf(sc->dc_dev, "TX underrun -- ");
- sc->dc_txthresh += DC_TXTHRESH_INC;
- if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
- printf("using store and forward mode\n");
- DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
+ if (reinit == 0) {
+ CSR_WRITE_4(sc, DC_NETCFG, netcfg);
+ if (DC_IS_INTEL(sc))
+ CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON);
} else {
- printf("increasing TX threshold\n");
- DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
- DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
+ sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ dc_init_locked(sc);
}
-
- if (DC_IS_INTEL(sc))
- DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
}
#ifdef DEVICE_POLLING
@@ -3011,7 +3247,7 @@ dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
dc_start_locked(ifp);
if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
- u_int32_t status;
+ uint32_t status;
status = CSR_READ_4(sc, DC_ISR);
status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
@@ -3025,7 +3261,7 @@ dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
CSR_WRITE_4(sc, DC_ISR, status);
if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
- u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
+ uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
if (dc_rx_resync(sc))
@@ -3040,7 +3276,7 @@ dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
if (status & DC_ISR_BUS_ERR) {
if_printf(ifp, "%s: bus error\n", __func__);
- dc_reset(sc);
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
dc_init_locked(sc);
}
}
@@ -3054,17 +3290,20 @@ dc_intr(void *arg)
{
struct dc_softc *sc;
struct ifnet *ifp;
- u_int32_t status;
+ uint32_t r, status;
+ int n;
sc = arg;
if (sc->suspended)
return;
- if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
- return;
-
DC_LOCK(sc);
+ status = CSR_READ_4(sc, DC_ISR);
+ if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) {
+ DC_UNLOCK(sc);
+ return;
+ }
ifp = sc->dc_ifp;
#ifdef DEVICE_POLLING
if (ifp->if_capenable & IFCAP_POLLING) {
@@ -3072,29 +3311,17 @@ dc_intr(void *arg)
return;
}
#endif
-
- /* Suppress unwanted interrupts */
- if (!(ifp->if_flags & IFF_UP)) {
- if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
- dc_stop(sc);
- DC_UNLOCK(sc);
- return;
- }
-
/* Disable interrupts. */
CSR_WRITE_4(sc, DC_IMR, 0x00000000);
- while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
- status != 0xFFFFFFFF &&
- (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-
+ for (n = 16; n > 0; n--) {
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+ break;
+ /* Ack interrupts. */
CSR_WRITE_4(sc, DC_ISR, status);
if (status & DC_ISR_RX_OK) {
- int curpkts;
- curpkts = ifp->if_ipackets;
- dc_rxeof(sc);
- if (curpkts == ifp->if_ipackets) {
+ if (dc_rxeof(sc) == 0) {
while (dc_rx_resync(sc))
dc_rxeof(sc);
}
@@ -3116,26 +3343,31 @@ dc_intr(void *arg)
if ((status & DC_ISR_RX_WATDOGTIMEO)
|| (status & DC_ISR_RX_NOBUF)) {
- int curpkts;
- curpkts = ifp->if_ipackets;
- dc_rxeof(sc);
- if (curpkts == ifp->if_ipackets) {
+ r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
+ ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
+ if (dc_rxeof(sc) == 0) {
while (dc_rx_resync(sc))
dc_rxeof(sc);
}
}
+ if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ dc_start_locked(ifp);
+
if (status & DC_ISR_BUS_ERR) {
- dc_reset(sc);
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
dc_init_locked(sc);
+ DC_UNLOCK(sc);
+ return;
}
+ status = CSR_READ_4(sc, DC_ISR);
+ if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0)
+ break;
}
/* Re-enable interrupts. */
- CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
-
- if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
- dc_start_locked(ifp);
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
DC_UNLOCK(sc);
}
@@ -3148,16 +3380,11 @@ static int
dc_encap(struct dc_softc *sc, struct mbuf **m_head)
{
bus_dma_segment_t segs[DC_MAXFRAGS];
+ bus_dmamap_t map;
struct dc_desc *f;
struct mbuf *m;
int cur, defragged, error, first, frag, i, idx, nseg;
- /*
- * If there's no way we can send any packets, return now.
- */
- if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD)
- return (ENOBUFS);
-
m = NULL;
defragged = 0;
if (sc->dc_flags & DC_TX_COALESCE &&
@@ -3191,7 +3418,7 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head)
}
idx = sc->dc_cdata.dc_tx_prod;
- error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
+ error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
if (error == EFBIG) {
if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT,
@@ -3201,7 +3428,7 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head)
return (defragged != 0 ? error : ENOBUFS);
}
*m_head = m;
- error = bus_dmamap_load_mbuf_sg(sc->dc_mtag,
+ error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
if (error != 0) {
m_freem(*m_head);
@@ -3218,26 +3445,34 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head)
return (EIO);
}
+ /* Check descriptor overruns. */
+ if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
+ bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
+ return (ENOBUFS);
+ }
+ bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
+ BUS_DMASYNC_PREWRITE);
+
first = cur = frag = sc->dc_cdata.dc_tx_prod;
for (i = 0; i < nseg; i++) {
if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
(frag == (DC_TX_LIST_CNT - 1)) &&
(first != sc->dc_cdata.dc_tx_first)) {
- bus_dmamap_unload(sc->dc_mtag,
+ bus_dmamap_unload(sc->dc_tx_mtag,
sc->dc_cdata.dc_tx_map[first]);
m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
- f = &sc->dc_ldata->dc_tx_list[frag];
+ f = &sc->dc_ldata.dc_tx_list[frag];
f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
if (i == 0) {
f->dc_status = 0;
f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
} else
f->dc_status = htole32(DC_TXSTAT_OWN);
- f->dc_data = htole32(segs[i].ds_addr);
+ f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr));
cur = frag;
DC_INC(frag, DC_TX_LIST_CNT);
}
@@ -3245,20 +3480,30 @@ dc_encap(struct dc_softc *sc, struct mbuf **m_head)
sc->dc_cdata.dc_tx_prod = frag;
sc->dc_cdata.dc_tx_cnt += nseg;
sc->dc_cdata.dc_tx_chain[cur] = *m_head;
- sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
+ sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
- sc->dc_ldata->dc_tx_list[first].dc_ctl |=
+ sc->dc_ldata.dc_tx_list[first].dc_ctl |=
htole32(DC_TXCTL_FINT);
if (sc->dc_flags & DC_TX_INTR_ALWAYS)
- sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
- if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
- sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
- sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
+ sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
+ if (sc->dc_flags & DC_TX_USE_TX_INTR &&
+ ++sc->dc_cdata.dc_tx_pkts >= 8) {
+ sc->dc_cdata.dc_tx_pkts = 0;
+ sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
+ }
+ sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
+
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+ /*
+ * Swap the last and the first dmamaps to ensure the map for
+ * this transmission is placed at the last descriptor.
+ */
+ map = sc->dc_cdata.dc_tx_map[cur];
+ sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first];
+ sc->dc_cdata.dc_tx_map[first] = map;
- bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx],
- BUS_DMASYNC_PREWRITE);
- bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap,
- BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
return (0);
}
@@ -3284,23 +3529,27 @@ static void
dc_start_locked(struct ifnet *ifp)
{
struct dc_softc *sc;
- struct mbuf *m_head = NULL;
- unsigned int queued = 0;
- int idx;
+ struct mbuf *m_head;
+ int queued;
sc = ifp->if_softc;
DC_LOCK_ASSERT(sc);
- if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
- return;
-
- if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+ IFF_DRV_RUNNING || sc->dc_link == 0)
return;
- idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
+ sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
- while (sc->dc_cdata.dc_tx_chain[idx] == NULL) {
+ for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
+ /*
+ * If there's no way we can send any packets, return now.
+ */
+ if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ break;
+ }
IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
if (m_head == NULL)
break;
@@ -3312,7 +3561,6 @@ dc_start_locked(struct ifnet *ifp)
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
break;
}
- idx = sc->dc_cdata.dc_tx_prod;
queued++;
/*
@@ -3320,11 +3568,6 @@ dc_start_locked(struct ifnet *ifp)
* to him.
*/
BPF_MTAP(ifp, m_head);
-
- if (sc->dc_flags & DC_TX_ONE) {
- ifp->if_drv_flags |= IFF_DRV_OACTIVE;
- break;
- }
}
if (queued > 0) {
@@ -3354,9 +3597,13 @@ dc_init_locked(struct dc_softc *sc)
{
struct ifnet *ifp = sc->dc_ifp;
struct mii_data *mii;
+ struct ifmedia *ifm;
DC_LOCK_ASSERT(sc);
+ if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
+ return;
+
mii = device_get_softc(sc->dc_miibus);
/*
@@ -3364,11 +3611,15 @@ dc_init_locked(struct dc_softc *sc)
*/
dc_stop(sc);
dc_reset(sc);
+ if (DC_IS_INTEL(sc)) {
+ ifm = &mii->mii_media;
+ dc_apply_fixup(sc, ifm->ifm_media);
+ }
/*
* Set cache alignment and burst length.
*/
- if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
+ if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc))
CSR_WRITE_4(sc, DC_BUSCTL, 0);
else
CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
@@ -3481,6 +3732,11 @@ dc_init_locked(struct dc_softc *sc)
CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
+ /* Initialize TX jabber and RX watchdog timer. */
+ if (DC_IS_ULI(sc))
+ CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK |
+ DC_WDOG_HOSTUNJAB);
+
/* Enable transmitter. */
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
@@ -3507,12 +3763,14 @@ dc_init_locked(struct dc_softc *sc)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
- mii_mediachg(mii);
- dc_setcfg(sc, sc->dc_if_media);
-
ifp->if_drv_flags |= IFF_DRV_RUNNING;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ dc_ifmedia_upd_locked(sc);
+
+ /* Clear missed frames and overflow counter. */
+ CSR_READ_4(sc, DC_FRAMESDISCARDED);
+
/* Don't start the ticker if this is a homePNA link. */
if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
sc->dc_link = 1;
@@ -3534,23 +3792,37 @@ static int
dc_ifmedia_upd(struct ifnet *ifp)
{
struct dc_softc *sc;
- struct mii_data *mii;
- struct ifmedia *ifm;
+ int error;
sc = ifp->if_softc;
- mii = device_get_softc(sc->dc_miibus);
DC_LOCK(sc);
- mii_mediachg(mii);
- ifm = &mii->mii_media;
-
- if (DC_IS_DAVICOM(sc) &&
- IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
- dc_setcfg(sc, ifm->ifm_media);
- else
- sc->dc_link = 0;
+ error = dc_ifmedia_upd_locked(sc);
DC_UNLOCK(sc);
+ return (error);
+}
- return (0);
+static int
+dc_ifmedia_upd_locked(struct dc_softc *sc)
+{
+ struct mii_data *mii;
+ struct ifmedia *ifm;
+ int error;
+
+ DC_LOCK_ASSERT(sc);
+
+ sc->dc_link = 0;
+ mii = device_get_softc(sc->dc_miibus);
+ error = mii_mediachg(mii);
+ if (error == 0) {
+ ifm = &mii->mii_media;
+ if (DC_IS_INTEL(sc))
+ dc_setcfg(sc, ifm->ifm_media);
+ else if (DC_IS_DAVICOM(sc) &&
+ IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
+ dc_setcfg(sc, ifm->ifm_media);
+ }
+
+ return (error);
}
/*
@@ -3600,7 +3872,7 @@ dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
if (need_setfilt)
dc_setfilt(sc);
} else {
- sc->dc_txthresh = 0;
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
dc_init_locked(sc);
}
} else {
@@ -3609,14 +3881,13 @@ dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
}
sc->dc_if_flags = ifp->if_flags;
DC_UNLOCK(sc);
- error = 0;
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
DC_LOCK(sc);
- dc_setfilt(sc);
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ dc_setfilt(sc);
DC_UNLOCK(sc);
- error = 0;
break;
case SIOCGIFMEDIA:
case SIOCSIFMEDIA:
@@ -3674,8 +3945,7 @@ dc_watchdog(void *xsc)
ifp->if_oerrors++;
device_printf(sc->dc_dev, "watchdog timeout\n");
- dc_stop(sc);
- dc_reset(sc);
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
dc_init_locked(sc);
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
@@ -3693,36 +3963,49 @@ dc_stop(struct dc_softc *sc)
struct dc_list_data *ld;
struct dc_chain_data *cd;
int i;
- u_int32_t ctl;
+ uint32_t ctl, netcfg;
DC_LOCK_ASSERT(sc);
ifp = sc->dc_ifp;
- ld = sc->dc_ldata;
+ ld = &sc->dc_ldata;
cd = &sc->dc_cdata;
callout_stop(&sc->dc_stat_ch);
callout_stop(&sc->dc_wdog_ch);
sc->dc_wdog_timer = 0;
+ sc->dc_link = 0;
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
- DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
+ netcfg = CSR_READ_4(sc, DC_NETCFG);
+ if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
+ CSR_WRITE_4(sc, DC_NETCFG,
+ netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
CSR_WRITE_4(sc, DC_IMR, 0x00000000);
+ /* Wait the completion of TX/RX SM. */
+ if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
+ dc_netcfg_wait(sc);
+
CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
- sc->dc_link = 0;
/*
* Free data in the RX lists.
*/
for (i = 0; i < DC_RX_LIST_CNT; i++) {
if (cd->dc_rx_chain[i] != NULL) {
+ bus_dmamap_sync(sc->dc_rx_mtag,
+ cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->dc_rx_mtag,
+ cd->dc_rx_map[i]);
m_freem(cd->dc_rx_chain[i]);
cd->dc_rx_chain[i] = NULL;
}
}
- bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list));
+ bzero(ld->dc_rx_list, DC_RX_LIST_SZ);
+ bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
/*
* Free the TX list buffers.
@@ -3730,17 +4013,22 @@ dc_stop(struct dc_softc *sc)
for (i = 0; i < DC_TX_LIST_CNT; i++) {
if (cd->dc_tx_chain[i] != NULL) {
ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
- if ((ctl & DC_TXCTL_SETUP) ||
- !(ctl & DC_TXCTL_LASTFRAG)) {
- cd->dc_tx_chain[i] = NULL;
- continue;
+ if (ctl & DC_TXCTL_SETUP) {
+ bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
+ BUS_DMASYNC_POSTWRITE);
+ } else {
+ bus_dmamap_sync(sc->dc_tx_mtag,
+ cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->dc_tx_mtag,
+ cd->dc_tx_map[i]);
+ m_freem(cd->dc_tx_chain[i]);
}
- bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]);
- m_freem(cd->dc_tx_chain[i]);
cd->dc_tx_chain[i] = NULL;
}
}
- bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list));
+ bzero(ld->dc_tx_list, DC_TX_LIST_SZ);
+ bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
}
/*
@@ -3804,3 +4092,52 @@ dc_shutdown(device_t dev)
return (0);
}
+
+static int
+dc_check_multiport(struct dc_softc *sc)
+{
+ struct dc_softc *dsc;
+ devclass_t dc;
+ device_t child;
+ uint8_t *eaddr;
+ int unit;
+
+ dc = devclass_find("dc");
+ for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {
+ child = devclass_get_device(dc, unit);
+ if (child == NULL)
+ continue;
+ if (child == sc->dc_dev)
+ continue;
+ if (device_get_parent(child) != device_get_parent(sc->dc_dev))
+ continue;
+ if (unit > device_get_unit(sc->dc_dev))
+ continue;
+ if (device_is_attached(child) == 0)
+ continue;
+ dsc = device_get_softc(child);
+ device_printf(sc->dc_dev,
+ "Using station address of %s as base\n",
+ device_get_nameunit(child));
+ bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN);
+ eaddr = (uint8_t *)sc->dc_eaddr;
+ eaddr[5]++;
+ /* Prepare SROM to parse again. */
+ if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL &&
+ sc->dc_romwidth != 0) {
+ free(sc->dc_srom, M_DEVBUF);
+ sc->dc_romwidth = dsc->dc_romwidth;
+ sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth),
+ M_DEVBUF, M_NOWAIT);
+ if (sc->dc_srom == NULL) {
+ device_printf(sc->dc_dev,
+ "Could not allocate SROM buffer\n");
+ return (ENOMEM);
+ }
+ bcopy(dsc->dc_srom, sc->dc_srom,
+ DC_ROM_SIZE(sc->dc_romwidth));
+ }
+ return (0);
+ }
+ return (ENOENT);
+}
diff --git a/freebsd/sys/dev/dc/if_dcreg.h b/freebsd/sys/dev/dc/if_dcreg.h
index b918ce49..0a61b7d1 100644
--- a/freebsd/sys/dev/dc/if_dcreg.h
+++ b/freebsd/sys/dev/dc/if_dcreg.h
@@ -36,23 +36,23 @@
* 21143 and clone common register definitions.
*/
-#define DC_BUSCTL 0x00 /* bus control */
-#define DC_TXSTART 0x08 /* tx start demand */
-#define DC_RXSTART 0x10 /* rx start demand */
-#define DC_RXADDR 0x18 /* rx descriptor list start addr */
-#define DC_TXADDR 0x20 /* tx descriptor list start addr */
-#define DC_ISR 0x28 /* interrupt status register */
-#define DC_NETCFG 0x30 /* network config register */
-#define DC_IMR 0x38 /* interrupt mask */
-#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
-#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
-#define DC_ROM 0x50 /* ROM programming address */
-#define DC_TIMER 0x58 /* general timer */
-#define DC_10BTSTAT 0x60 /* SIA status */
-#define DC_SIARESET 0x68 /* SIA connectivity */
-#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
-#define DC_WATCHDOG 0x78 /* SIA and general purpose port */
-#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */
+#define DC_BUSCTL 0x00 /* bus control */
+#define DC_TXSTART 0x08 /* tx start demand */
+#define DC_RXSTART 0x10 /* rx start demand */
+#define DC_RXADDR 0x18 /* rx descriptor list start addr */
+#define DC_TXADDR 0x20 /* tx descriptor list start addr */
+#define DC_ISR 0x28 /* interrupt status register */
+#define DC_NETCFG 0x30 /* network config register */
+#define DC_IMR 0x38 /* interrupt mask */
+#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */
+#define DC_SIO 0x48 /* MII and ROM/EEPROM access */
+#define DC_ROM 0x50 /* ROM programming address */
+#define DC_TIMER 0x58 /* general timer */
+#define DC_10BTSTAT 0x60 /* SIA status */
+#define DC_SIARESET 0x68 /* SIA connectivity */
+#define DC_10BTCTRL 0x70 /* SIA transmit and receive */
+#define DC_WATCHDOG 0x78 /* SIA and general purpose port */
+#define DC_SIAGP 0x78 /* SIA and general purpose port (X3201) */
/*
* There are two general 'types' of MX chips that we need to be
@@ -64,437 +64,453 @@
* 'magic' numbers we write to CSR16. The PNIC II falls into the
* 98713A/98715/98715A/98725 category.
*/
-#define DC_TYPE_98713 0x1
-#define DC_TYPE_98713A 0x2
-#define DC_TYPE_987x5 0x3
+#define DC_TYPE_98713 0x1
+#define DC_TYPE_98713A 0x2
+#define DC_TYPE_987x5 0x3
/* Other type of supported chips. */
-#define DC_TYPE_21143 0x4 /* Intel 21143 */
-#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
-#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
-#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */
-#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
-#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
-#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
+#define DC_TYPE_21143 0x4 /* Intel 21143 */
+#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */
+#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */
+#define DC_TYPE_AN983 0x7 /* ADMtek AN983 Centaur */
+#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */
+#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */
+#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */
#define DC_TYPE_XIRCOM 0xB /* Xircom X3201 */
-#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
+#define DC_TYPE_CONEXANT 0xC /* Conexant LANfinity RS7112 */
+#define DC_TYPE_ULI_M5261 0xD /* ALi/ULi M5261 */
+#define DC_TYPE_ULI_M5263 0xE /* ALi/ULi M5263 */
-#define DC_IS_MACRONIX(x) \
+#define DC_IS_MACRONIX(x) \
(x->dc_type == DC_TYPE_98713 || \
x->dc_type == DC_TYPE_98713A || \
x->dc_type == DC_TYPE_987x5)
-#define DC_IS_ADMTEK(x) \
+#define DC_IS_ADMTEK(x) \
(x->dc_type == DC_TYPE_AL981 || \
x->dc_type == DC_TYPE_AN983)
-#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
-#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
-#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
-#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983)
-#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
-#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
-#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
+#define DC_IS_ULI(x) \
+ (x->dc_type == DC_TYPE_ULI_M5261 || \
+ x->dc_type == DC_TYPE_ULI_M5263)
+
+#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143)
+#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX)
+#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981)
+#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN983)
+#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102)
+#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII)
+#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC)
#define DC_IS_XIRCOM(x) (x->dc_type == DC_TYPE_XIRCOM)
-#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
+#define DC_IS_CONEXANT(x) (x->dc_type == DC_TYPE_CONEXANT)
/* MII/symbol mode port types */
-#define DC_PMODE_MII 0x1
-#define DC_PMODE_SYM 0x2
-#define DC_PMODE_SIA 0x3
+#define DC_PMODE_MII 0x1
+#define DC_PMODE_SYM 0x2
+#define DC_PMODE_SIA 0x3
/*
* Bus control bits.
*/
-#define DC_BUSCTL_RESET 0x00000001
-#define DC_BUSCTL_ARBITRATION 0x00000002
-#define DC_BUSCTL_SKIPLEN 0x0000007C
-#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
-#define DC_BUSCTL_BURSTLEN 0x00003F00
-#define DC_BUSCTL_CACHEALIGN 0x0000C000
-#define DC_BUSCTL_TXPOLL 0x000E0000
-#define DC_BUSCTL_DBO 0x00100000
-#define DC_BUSCTL_MRME 0x00200000
-#define DC_BUSCTL_MRLE 0x00800000
-#define DC_BUSCTL_MWIE 0x01000000
-#define DC_BUSCTL_ONNOW_ENB 0x04000000
-
-#define DC_SKIPLEN_1LONG 0x00000004
-#define DC_SKIPLEN_2LONG 0x00000008
-#define DC_SKIPLEN_3LONG 0x00000010
-#define DC_SKIPLEN_4LONG 0x00000020
-#define DC_SKIPLEN_5LONG 0x00000040
-
-#define DC_CACHEALIGN_NONE 0x00000000
-#define DC_CACHEALIGN_8LONG 0x00004000
-#define DC_CACHEALIGN_16LONG 0x00008000
-#define DC_CACHEALIGN_32LONG 0x0000C000
-
-#define DC_BURSTLEN_USECA 0x00000000
-#define DC_BURSTLEN_1LONG 0x00000100
-#define DC_BURSTLEN_2LONG 0x00000200
-#define DC_BURSTLEN_4LONG 0x00000400
-#define DC_BURSTLEN_8LONG 0x00000800
-#define DC_BURSTLEN_16LONG 0x00001000
-#define DC_BURSTLEN_32LONG 0x00002000
-
-#define DC_TXPOLL_OFF 0x00000000
-#define DC_TXPOLL_1 0x00020000
-#define DC_TXPOLL_2 0x00040000
-#define DC_TXPOLL_3 0x00060000
-#define DC_TXPOLL_4 0x00080000
-#define DC_TXPOLL_5 0x000A0000
-#define DC_TXPOLL_6 0x000C0000
-#define DC_TXPOLL_7 0x000E0000
+#define DC_BUSCTL_RESET 0x00000001
+#define DC_BUSCTL_ARBITRATION 0x00000002
+#define DC_BUSCTL_SKIPLEN 0x0000007C
+#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080
+#define DC_BUSCTL_BURSTLEN 0x00003F00
+#define DC_BUSCTL_CACHEALIGN 0x0000C000
+#define DC_BUSCTL_TXPOLL 0x000E0000
+#define DC_BUSCTL_DBO 0x00100000
+#define DC_BUSCTL_MRME 0x00200000
+#define DC_BUSCTL_MRLE 0x00800000
+#define DC_BUSCTL_MWIE 0x01000000
+#define DC_BUSCTL_ONNOW_ENB 0x04000000
+
+#define DC_SKIPLEN_1LONG 0x00000004
+#define DC_SKIPLEN_2LONG 0x00000008
+#define DC_SKIPLEN_3LONG 0x00000010
+#define DC_SKIPLEN_4LONG 0x00000020
+#define DC_SKIPLEN_5LONG 0x00000040
+
+#define DC_CACHEALIGN_NONE 0x00000000
+#define DC_CACHEALIGN_8LONG 0x00004000
+#define DC_CACHEALIGN_16LONG 0x00008000
+#define DC_CACHEALIGN_32LONG 0x0000C000
+
+#define DC_BURSTLEN_USECA 0x00000000
+#define DC_BURSTLEN_1LONG 0x00000100
+#define DC_BURSTLEN_2LONG 0x00000200
+#define DC_BURSTLEN_4LONG 0x00000400
+#define DC_BURSTLEN_8LONG 0x00000800
+#define DC_BURSTLEN_16LONG 0x00001000
+#define DC_BURSTLEN_32LONG 0x00002000
+
+#define DC_TXPOLL_OFF 0x00000000
+#define DC_TXPOLL_1 0x00020000
+#define DC_TXPOLL_2 0x00040000
+#define DC_TXPOLL_3 0x00060000
+#define DC_TXPOLL_4 0x00080000
+#define DC_TXPOLL_5 0x000A0000
+#define DC_TXPOLL_6 0x000C0000
+#define DC_TXPOLL_7 0x000E0000
/*
* Interrupt status bits.
*/
-#define DC_ISR_TX_OK 0x00000001
-#define DC_ISR_TX_IDLE 0x00000002
-#define DC_ISR_TX_NOBUF 0x00000004
-#define DC_ISR_TX_JABBERTIMEO 0x00000008
-#define DC_ISR_LINKGOOD 0x00000010
-#define DC_ISR_TX_UNDERRUN 0x00000020
-#define DC_ISR_RX_OK 0x00000040
-#define DC_ISR_RX_NOBUF 0x00000080
-#define DC_ISR_RX_READ 0x00000100
-#define DC_ISR_RX_WATDOGTIMEO 0x00000200
-#define DC_ISR_TX_EARLY 0x00000400
-#define DC_ISR_TIMER_EXPIRED 0x00000800
-#define DC_ISR_LINKFAIL 0x00001000
-#define DC_ISR_BUS_ERR 0x00002000
-#define DC_ISR_RX_EARLY 0x00004000
-#define DC_ISR_ABNORMAL 0x00008000
-#define DC_ISR_NORMAL 0x00010000
-#define DC_ISR_RX_STATE 0x000E0000
-#define DC_ISR_TX_STATE 0x00700000
-#define DC_ISR_BUSERRTYPE 0x03800000
-#define DC_ISR_100MBPSLINK 0x08000000
-#define DC_ISR_MAGICKPACK 0x10000000
-
-#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
-#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
-#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
-#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
-#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
-#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
-#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
-#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
+#define DC_ISR_TX_OK 0x00000001
+#define DC_ISR_TX_IDLE 0x00000002
+#define DC_ISR_TX_NOBUF 0x00000004
+#define DC_ISR_TX_JABBERTIMEO 0x00000008
+#define DC_ISR_LINKGOOD 0x00000010
+#define DC_ISR_TX_UNDERRUN 0x00000020
+#define DC_ISR_RX_OK 0x00000040
+#define DC_ISR_RX_NOBUF 0x00000080
+#define DC_ISR_RX_READ 0x00000100
+#define DC_ISR_RX_WATDOGTIMEO 0x00000200
+#define DC_ISR_TX_EARLY 0x00000400
+#define DC_ISR_TIMER_EXPIRED 0x00000800
+#define DC_ISR_LINKFAIL 0x00001000
+#define DC_ISR_BUS_ERR 0x00002000
+#define DC_ISR_RX_EARLY 0x00004000
+#define DC_ISR_ABNORMAL 0x00008000
+#define DC_ISR_NORMAL 0x00010000
+#define DC_ISR_RX_STATE 0x000E0000
+#define DC_ISR_TX_STATE 0x00700000
+#define DC_ISR_BUSERRTYPE 0x03800000
+#define DC_ISR_100MBPSLINK 0x08000000
+#define DC_ISR_MAGICKPACK 0x10000000
+
+#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */
+#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */
+#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */
+#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */
+#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */
+#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */
+#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */
+#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */
#define DC_HAS_BROKEN_RXSTATE(x) \
(DC_IS_CENTAUR(x) || DC_IS_CONEXANT(x) || (DC_IS_DAVICOM(x) && \
pci_get_revid((x)->dc_dev) >= DC_REVISION_DM9102A))
-#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
-#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
-#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
-#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
-#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
-#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
-#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
-#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
+#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */
+#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */
+#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */
+#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */
+#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */
+#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */
+#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */
+#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */
/*
* Network config bits.
*/
-#define DC_NETCFG_RX_HASHPERF 0x00000001
-#define DC_NETCFG_RX_ON 0x00000002
-#define DC_NETCFG_RX_HASHONLY 0x00000004
-#define DC_NETCFG_RX_BADFRAMES 0x00000008
-#define DC_NETCFG_RX_INVFILT 0x00000010
-#define DC_NETCFG_BACKOFFCNT 0x00000020
-#define DC_NETCFG_RX_PROMISC 0x00000040
-#define DC_NETCFG_RX_ALLMULTI 0x00000080
-#define DC_NETCFG_FULLDUPLEX 0x00000200
-#define DC_NETCFG_LOOPBACK 0x00000C00
-#define DC_NETCFG_FORCECOLL 0x00001000
-#define DC_NETCFG_TX_ON 0x00002000
-#define DC_NETCFG_TX_THRESH 0x0000C000
-#define DC_NETCFG_TX_BACKOFF 0x00020000
-#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
-#define DC_NETCFG_HEARTBEAT 0x00080000
-#define DC_NETCFG_STORENFWD 0x00200000
-#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
-#define DC_NETCFG_PCS 0x00800000
-#define DC_NETCFG_SCRAMBLER 0x01000000
-#define DC_NETCFG_NO_RXCRC 0x02000000
-#define DC_NETCFG_RX_ALL 0x40000000
-#define DC_NETCFG_CAPEFFECT 0x80000000
-
-#define DC_OPMODE_NORM 0x00000000
-#define DC_OPMODE_INTLOOP 0x00000400
-#define DC_OPMODE_EXTLOOP 0x00000800
+#define DC_NETCFG_RX_HASHPERF 0x00000001
+#define DC_NETCFG_RX_ON 0x00000002
+#define DC_NETCFG_RX_HASHONLY 0x00000004
+#define DC_NETCFG_RX_BADFRAMES 0x00000008
+#define DC_NETCFG_RX_INVFILT 0x00000010
+#define DC_NETCFG_BACKOFFCNT 0x00000020
+#define DC_NETCFG_RX_PROMISC 0x00000040
+#define DC_NETCFG_RX_ALLMULTI 0x00000080
+#define DC_NETCFG_FULLDUPLEX 0x00000200
+#define DC_NETCFG_LOOPBACK 0x00000C00
+#define DC_NETCFG_FORCECOLL 0x00001000
+#define DC_NETCFG_TX_ON 0x00002000
+#define DC_NETCFG_TX_THRESH 0x0000C000
+#define DC_NETCFG_TX_BACKOFF 0x00020000
+#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */
+#define DC_NETCFG_HEARTBEAT 0x00080000
+#define DC_NETCFG_STORENFWD 0x00200000
+#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */
+#define DC_NETCFG_PCS 0x00800000
+#define DC_NETCFG_SCRAMBLER 0x01000000
+#define DC_NETCFG_NO_RXCRC 0x02000000
+#define DC_NETCFG_RX_ALL 0x40000000
+#define DC_NETCFG_CAPEFFECT 0x80000000
+
+#define DC_OPMODE_NORM 0x00000000
+#define DC_OPMODE_INTLOOP 0x00000400
+#define DC_OPMODE_EXTLOOP 0x00000800
#if 0
-#define DC_TXTHRESH_72BYTES 0x00000000
-#define DC_TXTHRESH_96BYTES 0x00004000
-#define DC_TXTHRESH_128BYTES 0x00008000
-#define DC_TXTHRESH_160BYTES 0x0000C000
+#define DC_TXTHRESH_72BYTES 0x00000000
+#define DC_TXTHRESH_96BYTES 0x00004000
+#define DC_TXTHRESH_128BYTES 0x00008000
+#define DC_TXTHRESH_160BYTES 0x0000C000
#endif
-#define DC_TXTHRESH_MIN 0x00000000
-#define DC_TXTHRESH_INC 0x00004000
-#define DC_TXTHRESH_MAX 0x0000C000
+#define DC_TXTHRESH_MIN 0x00000000
+#define DC_TXTHRESH_INC 0x00004000
+#define DC_TXTHRESH_MAX 0x0000C000
/*
* Interrupt mask bits.
*/
-#define DC_IMR_TX_OK 0x00000001
-#define DC_IMR_TX_IDLE 0x00000002
-#define DC_IMR_TX_NOBUF 0x00000004
-#define DC_IMR_TX_JABBERTIMEO 0x00000008
-#define DC_IMR_LINKGOOD 0x00000010
-#define DC_IMR_TX_UNDERRUN 0x00000020
-#define DC_IMR_RX_OK 0x00000040
-#define DC_IMR_RX_NOBUF 0x00000080
-#define DC_IMR_RX_READ 0x00000100
-#define DC_IMR_RX_WATDOGTIMEO 0x00000200
-#define DC_IMR_TX_EARLY 0x00000400
-#define DC_IMR_TIMER_EXPIRED 0x00000800
-#define DC_IMR_LINKFAIL 0x00001000
-#define DC_IMR_BUS_ERR 0x00002000
-#define DC_IMR_RX_EARLY 0x00004000
-#define DC_IMR_ABNORMAL 0x00008000
-#define DC_IMR_NORMAL 0x00010000
-#define DC_IMR_100MBPSLINK 0x08000000
-#define DC_IMR_MAGICKPACK 0x10000000
-
-#define DC_INTRS \
+#define DC_IMR_TX_OK 0x00000001
+#define DC_IMR_TX_IDLE 0x00000002
+#define DC_IMR_TX_NOBUF 0x00000004
+#define DC_IMR_TX_JABBERTIMEO 0x00000008
+#define DC_IMR_LINKGOOD 0x00000010
+#define DC_IMR_TX_UNDERRUN 0x00000020
+#define DC_IMR_RX_OK 0x00000040
+#define DC_IMR_RX_NOBUF 0x00000080
+#define DC_IMR_RX_READ 0x00000100
+#define DC_IMR_RX_WATDOGTIMEO 0x00000200
+#define DC_IMR_TX_EARLY 0x00000400
+#define DC_IMR_TIMER_EXPIRED 0x00000800
+#define DC_IMR_LINKFAIL 0x00001000
+#define DC_IMR_BUS_ERR 0x00002000
+#define DC_IMR_RX_EARLY 0x00004000
+#define DC_IMR_ABNORMAL 0x00008000
+#define DC_IMR_NORMAL 0x00010000
+#define DC_IMR_100MBPSLINK 0x08000000
+#define DC_IMR_MAGICKPACK 0x10000000
+
+#define DC_INTRS \
(DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\
DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \
DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/)
/*
* Serial I/O (EEPROM/ROM) bits.
*/
-#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
-#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
-#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
-#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
-#define DC_SIO_ROMDATA4 0x00000010
-#define DC_SIO_ROMDATA5 0x00000020
-#define DC_SIO_ROMDATA6 0x00000040
-#define DC_SIO_ROMDATA7 0x00000080
-#define DC_SIO_EESEL 0x00000800
-#define DC_SIO_ROMSEL 0x00001000
-#define DC_SIO_ROMCTL_WRITE 0x00002000
-#define DC_SIO_ROMCTL_READ 0x00004000
-#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
-#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
-#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
-#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
-
-#define DC_EECMD_WRITE 0x140
-#define DC_EECMD_READ 0x180
-#define DC_EECMD_ERASE 0x1c0
-
-#define DC_EE_NODEADDR_OFFSET 0x70
-#define DC_EE_NODEADDR 10
+#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */
+#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */
+#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */
+#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */
+#define DC_SIO_ROMDATA4 0x00000010
+#define DC_SIO_ROMDATA5 0x00000020
+#define DC_SIO_ROMDATA6 0x00000040
+#define DC_SIO_ROMDATA7 0x00000080
+#define DC_SIO_EESEL 0x00000800
+#define DC_SIO_ROMSEL 0x00001000
+#define DC_SIO_ROMCTL_WRITE 0x00002000
+#define DC_SIO_ROMCTL_READ 0x00004000
+#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */
+#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */
+#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */
+#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */
+
+#define DC_EECMD_WRITE 0x140
+#define DC_EECMD_READ 0x180
+#define DC_EECMD_ERASE 0x1c0
+
+#define DC_EE_NODEADDR_OFFSET 0x70
+#define DC_EE_NODEADDR 10
/*
* General purpose timer register
*/
-#define DC_TIMER_VALUE 0x0000FFFF
-#define DC_TIMER_CONTINUOUS 0x00010000
+#define DC_TIMER_VALUE 0x0000FFFF
+#define DC_TIMER_CONTINUOUS 0x00010000
/*
* 10baseT status register
*/
-#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
-#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
-#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
-#define DC_TSTAT_AUTOPOLARITY 0x00000008
-#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
-#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
-#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
-#define DC_TSTAT_REMFAULT 0x00000800
-#define DC_TSTAT_ANEGSTAT 0x00007000
-#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
-#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
-
-#define DC_ASTAT_DISABLE 0x00000000
-#define DC_ASTAT_TXDISABLE 0x00001000
-#define DC_ASTAT_ABDETECT 0x00002000
-#define DC_ASTAT_ACKDETECT 0x00003000
-#define DC_ASTAT_CMPACKDETECT 0x00004000
-#define DC_ASTAT_AUTONEGCMP 0x00005000
-#define DC_ASTAT_LINKCHECK 0x00006000
+#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */
+#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */
+#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */
+#define DC_TSTAT_AUTOPOLARITY 0x00000008
+#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */
+#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */
+#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */
+#define DC_TSTAT_REMFAULT 0x00000800
+#define DC_TSTAT_ANEGSTAT 0x00007000
+#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */
+#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */
+
+#define DC_ASTAT_DISABLE 0x00000000
+#define DC_ASTAT_TXDISABLE 0x00001000
+#define DC_ASTAT_ABDETECT 0x00002000
+#define DC_ASTAT_ACKDETECT 0x00003000
+#define DC_ASTAT_CMPACKDETECT 0x00004000
+#define DC_ASTAT_AUTONEGCMP 0x00005000
+#define DC_ASTAT_LINKCHECK 0x00006000
/*
* PHY reset register
*/
-#define DC_SIA_RESET 0x00000001
-#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
+#define DC_SIA_RESET 0x00000001
+#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */
/*
* 10baseT control register
*/
-#define DC_TCTL_ENCODER_ENB 0x00000001
-#define DC_TCTL_LOOPBACK 0x00000002
-#define DC_TCTL_DRIVER_ENB 0x00000004
-#define DC_TCTL_LNKPULSE_ENB 0x00000008
-#define DC_TCTL_HALFDUPLEX 0x00000040
-#define DC_TCTL_AUTONEGENBL 0x00000080
-#define DC_TCTL_RX_SQUELCH 0x00000100
-#define DC_TCTL_COLL_SQUELCH 0x00000200
-#define DC_TCTL_COLL_DETECT 0x00000400
-#define DC_TCTL_SQE_ENB 0x00000800
-#define DC_TCTL_LINKTEST 0x00001000
-#define DC_TCTL_AUTOPOLARITY 0x00002000
-#define DC_TCTL_SET_POL_PLUS 0x00004000
-#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
-#define DC_TCTL_100BTXHALF 0x00010000
-#define DC_TCTL_100BTXFULL 0x00020000
-#define DC_TCTL_100BT4 0x00040000
+#define DC_TCTL_ENCODER_ENB 0x00000001
+#define DC_TCTL_LOOPBACK 0x00000002
+#define DC_TCTL_DRIVER_ENB 0x00000004
+#define DC_TCTL_LNKPULSE_ENB 0x00000008
+#define DC_TCTL_HALFDUPLEX 0x00000040
+#define DC_TCTL_AUTONEGENBL 0x00000080
+#define DC_TCTL_RX_SQUELCH 0x00000100
+#define DC_TCTL_COLL_SQUELCH 0x00000200
+#define DC_TCTL_COLL_DETECT 0x00000400
+#define DC_TCTL_SQE_ENB 0x00000800
+#define DC_TCTL_LINKTEST 0x00001000
+#define DC_TCTL_AUTOPOLARITY 0x00002000
+#define DC_TCTL_SET_POL_PLUS 0x00004000
+#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */
+#define DC_TCTL_100BTXHALF 0x00010000
+#define DC_TCTL_100BTXFULL 0x00020000
+#define DC_TCTL_100BT4 0x00040000
/*
* Watchdog timer register
*/
-#define DC_WDOG_JABBERDIS 0x00000001
-#define DC_WDOG_HOSTUNJAB 0x00000002
-#define DC_WDOG_JABBERCLK 0x00000004
-#define DC_WDOG_RXWDOGDIS 0x00000010
-#define DC_WDOG_RXWDOGCLK 0x00000020
-#define DC_WDOG_MUSTBEZERO 0x00000100
-#define DC_WDOG_AUIBNC 0x00100000
-#define DC_WDOG_ACTIVITY 0x00200000
-#define DC_WDOG_RX_MATCH 0x00400000
-#define DC_WDOG_LINK 0x00800000
-#define DC_WDOG_CTLWREN 0x08000000
+#define DC_WDOG_JABBERDIS 0x00000001
+#define DC_WDOG_HOSTUNJAB 0x00000002
+#define DC_WDOG_JABBERCLK 0x00000004
+#define DC_WDOG_RXWDOGDIS 0x00000010
+#define DC_WDOG_RXWDOGCLK 0x00000020
+#define DC_WDOG_MUSTBEZERO 0x00000100
+#define DC_WDOG_AUIBNC 0x00100000
+#define DC_WDOG_ACTIVITY 0x00200000
+#define DC_WDOG_RX_MATCH 0x00400000
+#define DC_WDOG_LINK 0x00800000
+#define DC_WDOG_CTLWREN 0x08000000
/*
* SIA and General Purpose Port register (X3201)
*/
-#define DC_SIAGP_RXMATCH 0x40000000
-#define DC_SIAGP_INT1 0x20000000
-#define DC_SIAGP_INT0 0x10000000
-#define DC_SIAGP_WRITE_EN 0x08000000
-#define DC_SIAGP_RXMATCH_EN 0x04000000
-#define DC_SIAGP_INT1_EN 0x02000000
-#define DC_SIAGP_INT0_EN 0x01000000
-#define DC_SIAGP_LED3 0x00800000
-#define DC_SIAGP_LED2 0x00400000
-#define DC_SIAGP_LED1 0x00200000
-#define DC_SIAGP_LED0 0x00100000
-#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
-#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
-#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
-#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
+#define DC_SIAGP_RXMATCH 0x40000000
+#define DC_SIAGP_INT1 0x20000000
+#define DC_SIAGP_INT0 0x10000000
+#define DC_SIAGP_WRITE_EN 0x08000000
+#define DC_SIAGP_RXMATCH_EN 0x04000000
+#define DC_SIAGP_INT1_EN 0x02000000
+#define DC_SIAGP_INT0_EN 0x01000000
+#define DC_SIAGP_LED3 0x00800000
+#define DC_SIAGP_LED2 0x00400000
+#define DC_SIAGP_LED1 0x00200000
+#define DC_SIAGP_LED0 0x00100000
+#define DC_SIAGP_MD_GP3_OUTPUT 0x00080000
+#define DC_SIAGP_MD_GP2_OUTPUT 0x00040000
+#define DC_SIAGP_MD_GP1_OUTPUT 0x00020000
+#define DC_SIAGP_MD_GP0_OUTPUT 0x00010000
/*
* Size of a setup frame.
*/
-#define DC_SFRAME_LEN 192
+#define DC_SFRAME_LEN 192
/*
* 21x4x TX/RX list structure.
*/
struct dc_desc {
- u_int32_t dc_status;
- u_int32_t dc_ctl;
- u_int32_t dc_ptr1;
- u_int32_t dc_ptr2;
+ uint32_t dc_status;
+ uint32_t dc_ctl;
+ uint32_t dc_ptr1;
+ uint32_t dc_ptr2;
};
-#define dc_data dc_ptr1
-#define dc_next dc_ptr2
-
-#define DC_RXSTAT_FIFOOFLOW 0x00000001
-#define DC_RXSTAT_CRCERR 0x00000002
-#define DC_RXSTAT_DRIBBLE 0x00000004
-#define DC_RXSTAT_MIIERE 0x00000008
-#define DC_RXSTAT_WATCHDOG 0x00000010
-#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
-#define DC_RXSTAT_COLLSEEN 0x00000040
-#define DC_RXSTAT_GIANT 0x00000080
-#define DC_RXSTAT_LASTFRAG 0x00000100
-#define DC_RXSTAT_FIRSTFRAG 0x00000200
-#define DC_RXSTAT_MULTICAST 0x00000400
-#define DC_RXSTAT_RUNT 0x00000800
-#define DC_RXSTAT_RXTYPE 0x00003000
-#define DC_RXSTAT_DE 0x00004000
-#define DC_RXSTAT_RXERR 0x00008000
-#define DC_RXSTAT_RXLEN 0x3FFF0000
-#define DC_RXSTAT_OWN 0x80000000
-
-#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
-#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
-
-#define DC_RXCTL_BUFLEN1 0x00000FFF
-#define DC_RXCTL_BUFLEN2 0x00FFF000
-#define DC_RXCTL_RLINK 0x01000000
-#define DC_RXCTL_RLAST 0x02000000
-
-#define DC_TXSTAT_DEFER 0x00000001
-#define DC_TXSTAT_UNDERRUN 0x00000002
-#define DC_TXSTAT_LINKFAIL 0x00000003
-#define DC_TXSTAT_COLLCNT 0x00000078
-#define DC_TXSTAT_SQE 0x00000080
-#define DC_TXSTAT_EXCESSCOLL 0x00000100
-#define DC_TXSTAT_LATECOLL 0x00000200
-#define DC_TXSTAT_NOCARRIER 0x00000400
-#define DC_TXSTAT_CARRLOST 0x00000800
-#define DC_TXSTAT_JABTIMEO 0x00004000
-#define DC_TXSTAT_ERRSUM 0x00008000
-#define DC_TXSTAT_OWN 0x80000000
-
-#define DC_TXCTL_BUFLEN1 0x000007FF
-#define DC_TXCTL_BUFLEN2 0x003FF800
-#define DC_TXCTL_FILTTYPE0 0x00400000
-#define DC_TXCTL_PAD 0x00800000
-#define DC_TXCTL_TLINK 0x01000000
-#define DC_TXCTL_TLAST 0x02000000
-#define DC_TXCTL_NOCRC 0x04000000
-#define DC_TXCTL_SETUP 0x08000000
-#define DC_TXCTL_FILTTYPE1 0x10000000
-#define DC_TXCTL_FIRSTFRAG 0x20000000
-#define DC_TXCTL_LASTFRAG 0x40000000
-#define DC_TXCTL_FINT 0x80000000
-
-#define DC_FILTER_PERFECT 0x00000000
-#define DC_FILTER_HASHPERF 0x00400000
-#define DC_FILTER_INVERSE 0x10000000
-#define DC_FILTER_HASHONLY 0x10400000
-
-#define DC_MAXFRAGS 16
+#define dc_data dc_ptr1
+#define dc_next dc_ptr2
+
+#define DC_RXSTAT_FIFOOFLOW 0x00000001
+#define DC_RXSTAT_CRCERR 0x00000002
+#define DC_RXSTAT_DRIBBLE 0x00000004
+#define DC_RXSTAT_MIIERE 0x00000008
+#define DC_RXSTAT_WATCHDOG 0x00000010
+#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */
+#define DC_RXSTAT_COLLSEEN 0x00000040
+#define DC_RXSTAT_GIANT 0x00000080
+#define DC_RXSTAT_LASTFRAG 0x00000100
+#define DC_RXSTAT_FIRSTFRAG 0x00000200
+#define DC_RXSTAT_MULTICAST 0x00000400
+#define DC_RXSTAT_RUNT 0x00000800
+#define DC_RXSTAT_RXTYPE 0x00003000
+#define DC_RXSTAT_DE 0x00004000
+#define DC_RXSTAT_RXERR 0x00008000
+#define DC_RXSTAT_RXLEN 0x3FFF0000
+#define DC_RXSTAT_OWN 0x80000000
+
+#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16)
+#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN)
+
+#define DC_RXCTL_BUFLEN1 0x00000FFF
+#define DC_RXCTL_BUFLEN2 0x00FFF000
+#define DC_RXCTL_RLINK 0x01000000
+#define DC_RXCTL_RLAST 0x02000000
+
+#define DC_TXSTAT_DEFER 0x00000001
+#define DC_TXSTAT_UNDERRUN 0x00000002
+#define DC_TXSTAT_LINKFAIL 0x00000003
+#define DC_TXSTAT_COLLCNT 0x00000078
+#define DC_TXSTAT_SQE 0x00000080
+#define DC_TXSTAT_EXCESSCOLL 0x00000100
+#define DC_TXSTAT_LATECOLL 0x00000200
+#define DC_TXSTAT_NOCARRIER 0x00000400
+#define DC_TXSTAT_CARRLOST 0x00000800
+#define DC_TXSTAT_JABTIMEO 0x00004000
+#define DC_TXSTAT_ERRSUM 0x00008000
+#define DC_TXSTAT_OWN 0x80000000
+
+#define DC_TXCTL_BUFLEN1 0x000007FF
+#define DC_TXCTL_BUFLEN2 0x003FF800
+#define DC_TXCTL_FILTTYPE0 0x00400000
+#define DC_TXCTL_PAD 0x00800000
+#define DC_TXCTL_TLINK 0x01000000
+#define DC_TXCTL_TLAST 0x02000000
+#define DC_TXCTL_NOCRC 0x04000000
+#define DC_TXCTL_SETUP 0x08000000
+#define DC_TXCTL_FILTTYPE1 0x10000000
+#define DC_TXCTL_FIRSTFRAG 0x20000000
+#define DC_TXCTL_LASTFRAG 0x40000000
+#define DC_TXCTL_FINT 0x80000000
+
+#define DC_FILTER_PERFECT 0x00000000
+#define DC_FILTER_HASHPERF 0x00400000
+#define DC_FILTER_INVERSE 0x10000000
+#define DC_FILTER_HASHONLY 0x10400000
+
+#define DC_MAXFRAGS 16
#ifdef DEVICE_POLLING
-#define DC_RX_LIST_CNT 192
+#define DC_RX_LIST_CNT 192
#else
-#define DC_RX_LIST_CNT 64
+#define DC_RX_LIST_CNT 64
#endif
-#define DC_TX_LIST_CNT 256
-#define DC_TX_LIST_RSVD 5
-#define DC_MIN_FRAMELEN 60
-#define DC_RXLEN 1536
+#define DC_TX_LIST_CNT 256
+#define DC_TX_LIST_RSVD 5
+#define DC_MIN_FRAMELEN 60
+#define DC_RXLEN 1536
-#define DC_INC(x, y) (x) = (x + 1) % y
+#define DC_INC(x, y) (x) = (x + 1) % y
+
+#define DC_LIST_ALIGN (sizeof(struct dc_desc))
+#define DC_RXBUF_ALIGN 4
/* Macros to easily get the DMA address of a descriptor. */
-#define DC_RXDESC(sc, i) (sc->dc_laddr + \
- (uintptr_t)(sc->dc_ldata->dc_rx_list + i) - (uintptr_t)sc->dc_ldata)
-#define DC_TXDESC(sc, i) (sc->dc_laddr + \
- (uintptr_t)(sc->dc_ldata->dc_tx_list + i) - (uintptr_t)sc->dc_ldata)
+#define DC_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
+#define DC_RXDESC(sc, i) \
+ (DC_ADDR_LO(sc->dc_ldata.dc_rx_list_paddr + (sizeof(struct dc_desc) * i)))
+#define DC_TXDESC(sc, i) \
+ (DC_ADDR_LO(sc->dc_ldata.dc_tx_list_paddr + (sizeof(struct dc_desc) * i)))
#if BYTE_ORDER == BIG_ENDIAN
-#define DC_SP_MAC(x) ((x) << 16)
+#define DC_SP_MAC(x) ((x) << 16)
#else
-#define DC_SP_MAC(x) (x)
+#define DC_SP_MAC(x) (x)
#endif
struct dc_list_data {
- struct dc_desc dc_rx_list[DC_RX_LIST_CNT];
- struct dc_desc dc_tx_list[DC_TX_LIST_CNT];
+ struct dc_desc *dc_rx_list;
+ bus_addr_t dc_rx_list_paddr;
+ struct dc_desc *dc_tx_list;
+ bus_addr_t dc_tx_list_paddr;
};
+#define DC_RX_LIST_SZ ((sizeof(struct dc_desc) * DC_RX_LIST_CNT))
+#define DC_TX_LIST_SZ ((sizeof(struct dc_desc) * DC_TX_LIST_CNT))
+
struct dc_chain_data {
struct mbuf *dc_rx_chain[DC_RX_LIST_CNT];
struct mbuf *dc_tx_chain[DC_TX_LIST_CNT];
bus_dmamap_t dc_rx_map[DC_RX_LIST_CNT];
bus_dmamap_t dc_tx_map[DC_TX_LIST_CNT];
- u_int32_t *dc_sbuf;
- u_int8_t dc_pad[DC_MIN_FRAMELEN];
+ uint32_t *dc_sbuf;
+ uint8_t dc_pad[DC_MIN_FRAMELEN];
+ int dc_tx_pkts;
int dc_tx_first;
int dc_tx_prod;
int dc_tx_cons;
@@ -504,39 +520,21 @@ struct dc_chain_data {
struct dc_mediainfo {
int dc_media;
- u_int8_t *dc_gp_ptr;
- u_int8_t dc_gp_len;
- u_int8_t *dc_reset_ptr;
- u_int8_t dc_reset_len;
+ uint8_t *dc_gp_ptr;
+ uint8_t dc_gp_len;
+ uint8_t *dc_reset_ptr;
+ uint8_t dc_reset_len;
struct dc_mediainfo *dc_next;
};
struct dc_type {
- u_int32_t dc_devid;
- u_int8_t dc_minrev;
- char *dc_name;
-};
-
-struct dc_mii_frame {
- u_int8_t mii_stdelim;
- u_int8_t mii_opcode;
- u_int8_t mii_phyaddr;
- u_int8_t mii_regaddr;
- u_int8_t mii_turnaround;
- u_int16_t mii_data;
+ uint32_t dc_devid;
+ uint8_t dc_minrev;
+ const char *dc_name;
};
/*
- * MII constants
- */
-#define DC_MII_STARTDELIM 0x01
-#define DC_MII_READOP 0x02
-#define DC_MII_WRITEOP 0x01
-#define DC_MII_TURNAROUND 0x02
-
-
-/*
* Registers specific to clone devices.
* This mainly relates to RX filter programming: not all 21x4x clones
* use the standard DEC filter programming mechanism.
@@ -546,42 +544,42 @@ struct dc_mii_frame {
* ADMtek specific registers and constants for the AL981 and AN983.
* The AN983 doesn't use the magic PHY registers.
*/
-#define DC_AL_CR 0x88 /* command register */
-#define DC_AL_PAR0 0xA4 /* station address */
-#define DC_AL_PAR1 0xA8 /* station address */
-#define DC_AL_MAR0 0xAC /* multicast hash filter */
-#define DC_AL_MAR1 0xB0 /* multicast hash filter */
-#define DC_AL_BMCR 0xB4 /* built in PHY control */
-#define DC_AL_BMSR 0xB8 /* built in PHY status */
-#define DC_AL_VENID 0xBC /* built in PHY ID0 */
-#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
-#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
-#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
-#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
-
-#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */
-#define DC_ADMTEK_PHYADDR 0x1
-#define DC_AL_EE_NODEADDR 4
+#define DC_AL_CR 0x88 /* command register */
+#define DC_AL_PAR0 0xA4 /* station address */
+#define DC_AL_PAR1 0xA8 /* station address */
+#define DC_AL_MAR0 0xAC /* multicast hash filter */
+#define DC_AL_MAR1 0xB0 /* multicast hash filter */
+#define DC_AL_BMCR 0xB4 /* built in PHY control */
+#define DC_AL_BMSR 0xB8 /* built in PHY status */
+#define DC_AL_VENID 0xBC /* built in PHY ID0 */
+#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */
+#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */
+#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */
+#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */
+
+#define DC_AL_CR_ATUR 0x00000001 /* automatic TX underrun recovery */
+#define DC_ADMTEK_PHYADDR 0x1
+#define DC_AL_EE_NODEADDR 4
/* End of ADMtek specific registers */
/*
* ASIX specific registers.
*/
-#define DC_AX_FILTIDX 0x68 /* RX filter index */
-#define DC_AX_FILTDATA 0x70 /* RX filter data */
+#define DC_AX_FILTIDX 0x68 /* RX filter index */
+#define DC_AX_FILTDATA 0x70 /* RX filter data */
/*
* Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
*/
-#define DC_AX_NETCFG_RX_BROAD 0x00000100
+#define DC_AX_NETCFG_RX_BROAD 0x00000100
/*
* RX Filter Index Register values
*/
-#define DC_AX_FILTIDX_PAR0 0x00000000
-#define DC_AX_FILTIDX_PAR1 0x00000001
-#define DC_AX_FILTIDX_MAR0 0x00000002
-#define DC_AX_FILTIDX_MAR1 0x00000003
+#define DC_AX_FILTIDX_PAR0 0x00000000
+#define DC_AX_FILTIDX_PAR1 0x00000001
+#define DC_AX_FILTIDX_MAR0 0x00000002
+#define DC_AX_FILTIDX_MAR1 0x00000003
/* End of ASIX specific registers */
/*
@@ -590,22 +588,22 @@ struct dc_mii_frame {
* a magic packet register, which we need to tweak a bit per the
* Macronix application notes.
*/
-#define DC_MX_MAGICPACKET 0x80
-#define DC_MX_NWAYSTAT 0xA0
+#define DC_MX_MAGICPACKET 0x80
+#define DC_MX_NWAYSTAT 0xA0
/*
* Magic packet register
*/
-#define DC_MX_MPACK_DISABLE 0x00400000
+#define DC_MX_MPACK_DISABLE 0x00400000
/*
* NWAY status register.
*/
-#define DC_MX_NWAY_10BTHALF 0x08000000
-#define DC_MX_NWAY_10BTFULL 0x10000000
-#define DC_MX_NWAY_100BTHALF 0x20000000
-#define DC_MX_NWAY_100BTFULL 0x40000000
-#define DC_MX_NWAY_100BT4 0x80000000
+#define DC_MX_NWAY_10BTHALF 0x08000000
+#define DC_MX_NWAY_10BTFULL 0x10000000
+#define DC_MX_NWAY_100BTHALF 0x20000000
+#define DC_MX_NWAY_100BTFULL 0x40000000
+#define DC_MX_NWAY_100BT4 0x80000000
/*
* These are magic values that must be written into CSR16
@@ -613,10 +611,10 @@ struct dc_mii_frame {
* operating mode. The magic numbers are documented in the
* Macronix 98715 application notes.
*/
-#define DC_MX_MAGIC_98713 0x0F370000
-#define DC_MX_MAGIC_98713A 0x0B3C0000
-#define DC_MX_MAGIC_98715 0x0B3C0000
-#define DC_MX_MAGIC_98725 0x0B3C0000
+#define DC_MX_MAGIC_98713 0x0F370000
+#define DC_MX_MAGIC_98713A 0x0B3C0000
+#define DC_MX_MAGIC_98715 0x0B3C0000
+#define DC_MX_MAGIC_98725 0x0B3C0000
/* End of Macronix specific registers */
/*
@@ -624,20 +622,20 @@ struct dc_mii_frame {
* The PNIC has its own special NWAY support, which doesn't work,
* and shortcut ways of reading the EEPROM and MII bus.
*/
-#define DC_PN_GPIO 0x60 /* general purpose pins control */
-#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
-#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
-#define DC_PN_MII 0xA0 /* MII access register */
-#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
+#define DC_PN_GPIO 0x60 /* general purpose pins control */
+#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */
+#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */
+#define DC_PN_MII 0xA0 /* MII access register */
+#define DC_PN_NWAY 0xB8 /* Internal NWAY register */
/* Serial I/O EEPROM register */
-#define DC_PN_SIOCTL_DATA 0x0000003F
-#define DC_PN_SIOCTL_OPCODE 0x00000300
-#define DC_PN_SIOCTL_BUSY 0x80000000
+#define DC_PN_SIOCTL_DATA 0x0000003F
+#define DC_PN_SIOCTL_OPCODE 0x00000300
+#define DC_PN_SIOCTL_BUSY 0x80000000
-#define DC_PN_EEOPCODE_ERASE 0x00000300
-#define DC_PN_EEOPCODE_READ 0x00000600
-#define DC_PN_EEOPCODE_WRITE 0x00000100
+#define DC_PN_EEOPCODE_ERASE 0x00000300
+#define DC_PN_EEOPCODE_READ 0x00000600
+#define DC_PN_EEOPCODE_WRITE 0x00000100
/*
* The first two general purpose pins control speed selection and
@@ -646,63 +644,63 @@ struct dc_mii_frame {
* loopback bits set accordingly when changing media. Physically, this
* will set the state of a relay mounted on the card.
*/
-#define DC_PN_GPIO_DATA0 0x000000001
-#define DC_PN_GPIO_DATA1 0x000000002
-#define DC_PN_GPIO_DATA2 0x000000004
-#define DC_PN_GPIO_DATA3 0x000000008
-#define DC_PN_GPIO_CTL0 0x000000010
-#define DC_PN_GPIO_CTL1 0x000000020
-#define DC_PN_GPIO_CTL2 0x000000040
-#define DC_PN_GPIO_CTL3 0x000000080
-#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
-#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
-#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
-#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
-#define DC_PN_GPIO_SETBIT(sc, r) \
+#define DC_PN_GPIO_DATA0 0x000000001
+#define DC_PN_GPIO_DATA1 0x000000002
+#define DC_PN_GPIO_DATA2 0x000000004
+#define DC_PN_GPIO_DATA3 0x000000008
+#define DC_PN_GPIO_CTL0 0x000000010
+#define DC_PN_GPIO_CTL1 0x000000020
+#define DC_PN_GPIO_CTL2 0x000000040
+#define DC_PN_GPIO_CTL3 0x000000080
+#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */
+#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */
+#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2
+#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3
+#define DC_PN_GPIO_SETBIT(sc, r) \
DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4)))
-#define DC_PN_GPIO_CLRBIT(sc, r) \
+#define DC_PN_GPIO_CLRBIT(sc, r) \
{ \
DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
}
-
+
/* shortcut MII access register */
-#define DC_PN_MII_DATA 0x0000FFFF
-#define DC_PN_MII_RESERVER 0x00020000
-#define DC_PN_MII_REGADDR 0x007C0000
-#define DC_PN_MII_PHYADDR 0x0F800000
-#define DC_PN_MII_OPCODE 0x30000000
-#define DC_PN_MII_BUSY 0x80000000
+#define DC_PN_MII_DATA 0x0000FFFF
+#define DC_PN_MII_RESERVER 0x00020000
+#define DC_PN_MII_REGADDR 0x007C0000
+#define DC_PN_MII_PHYADDR 0x0F800000
+#define DC_PN_MII_OPCODE 0x30000000
+#define DC_PN_MII_BUSY 0x80000000
-#define DC_PN_MIIOPCODE_READ 0x60020000
-#define DC_PN_MIIOPCODE_WRITE 0x50020000
+#define DC_PN_MIIOPCODE_READ 0x60020000
+#define DC_PN_MIIOPCODE_WRITE 0x50020000
/* Internal NWAY bits */
-#define DC_PN_NWAY_RESET 0x00000001 /* reset */
-#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
-#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
-#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
-#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
-#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
-#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
-#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
-#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
-#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
-#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
-#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
-#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
-#define DC_PN_NWAY_CAP10HDX 0x00002000
-#define DC_PN_NWAY_CAP10FDX 0x00004000
-#define DC_PN_NWAY_CAP100FDX 0x00008000
-#define DC_PN_NWAY_CAP100HDX 0x00010000
-#define DC_PN_NWAY_CAP100T4 0x00020000
-#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
-#define DC_PN_NWAY_REMFAULT 0x04000000
-#define DC_PN_NWAY_LPAR10HDX 0x08000000
-#define DC_PN_NWAY_LPAR10FDX 0x10000000
-#define DC_PN_NWAY_LPAR100FDX 0x20000000
-#define DC_PN_NWAY_LPAR100HDX 0x40000000
-#define DC_PN_NWAY_LPAR100T4 0x80000000
+#define DC_PN_NWAY_RESET 0x00000001 /* reset */
+#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */
+#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */
+#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */
+#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */
+#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */
+#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */
+#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */
+#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */
+#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */
+#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */
+#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */
+#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */
+#define DC_PN_NWAY_CAP10HDX 0x00002000
+#define DC_PN_NWAY_CAP10FDX 0x00004000
+#define DC_PN_NWAY_CAP100FDX 0x00008000
+#define DC_PN_NWAY_CAP100HDX 0x00010000
+#define DC_PN_NWAY_CAP100T4 0x00020000
+#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */
+#define DC_PN_NWAY_REMFAULT 0x04000000
+#define DC_PN_NWAY_LPAR10HDX 0x08000000
+#define DC_PN_NWAY_LPAR10FDX 0x10000000
+#define DC_PN_NWAY_LPAR100FDX 0x20000000
+#define DC_PN_NWAY_LPAR100HDX 0x40000000
+#define DC_PN_NWAY_LPAR100T4 0x80000000
/* End of PNIC specific registers */
@@ -710,44 +708,64 @@ struct dc_mii_frame {
* CONEXANT specific registers.
*/
-#define DC_CONEXANT_PHYADDR 0x1
-#define DC_CONEXANT_EE_NODEADDR 0x19A
+#define DC_CONEXANT_PHYADDR 0x1
+#define DC_CONEXANT_EE_NODEADDR 0x19A
/* End of CONEXANT specific registers */
+/*
+ * ULi M5263 specific registers.
+ */
+#define DC_ULI_FILTER_NPERF 14
+
+#define DC_ULI_PHY_DATA_MASK 0x0000FFFF
+#define DC_ULI_PHY_REG_MASK 0x001F0000
+#define DC_ULI_PHY_ADDR_MASK 0x03E00000
+#define DC_ULI_PHY_OP_WRITE 0x04000000
+#define DC_ULI_PHY_OP_READ 0x08000000
+#define DC_ULI_PHY_OP_DONE 0x10000000
+
+#define DC_ULI_PHY_DATA_SHIFT 0
+#define DC_ULI_PHY_REG_SHIFT 16
+#define DC_ULI_PHY_ADDR_SHIFT 21
+
+/* End of ULi M5263 specific registers */
struct dc_softc {
struct ifnet *dc_ifp; /* interface info */
device_t dc_dev; /* device info */
bus_space_handle_t dc_bhandle; /* bus space handle */
bus_space_tag_t dc_btag; /* bus space tag */
- bus_dma_tag_t dc_ltag; /* tag for descriptor ring */
- bus_dmamap_t dc_lmap; /* map for descriptor ring */
- u_int32_t dc_laddr; /* DMA address of dc_ldata */
- bus_dma_tag_t dc_mtag; /* tag for mbufs */
+ bus_dma_tag_t dc_ptag; /* parent DMA tag */
bus_dmamap_t dc_sparemap;
+ bus_dma_tag_t dc_rx_ltag; /* tag for RX descriptors */
+ bus_dmamap_t dc_rx_lmap;
+ bus_dma_tag_t dc_tx_ltag; /* tag for TX descriptors */
+ bus_dmamap_t dc_tx_lmap;
bus_dma_tag_t dc_stag; /* tag for the setup frame */
bus_dmamap_t dc_smap; /* map for the setup frame */
- u_int32_t dc_saddr; /* DMA address of setup frame */
+ bus_addr_t dc_saddr; /* DMA address of setup frame */
+ bus_dma_tag_t dc_rx_mtag; /* tag for RX mbufs */
+ bus_dma_tag_t dc_tx_mtag; /* tag for TX mbufs */
void *dc_intrhand;
struct resource *dc_irq;
struct resource *dc_res;
const struct dc_type *dc_info; /* adapter info */
device_t dc_miibus;
- u_int8_t dc_type;
- u_int8_t dc_pmode;
- u_int8_t dc_link;
- u_int8_t dc_cachesize;
+ uint8_t dc_type;
+ uint8_t dc_pmode;
+ uint8_t dc_link;
+ uint8_t dc_cachesize;
int dc_romwidth;
int dc_pnic_rx_bug_save;
unsigned char *dc_pnic_rx_buf;
int dc_if_flags;
- int dc_if_media;
- u_int32_t dc_flags;
- u_int32_t dc_txthresh;
- u_int8_t *dc_srom;
+ uint32_t dc_flags;
+ uint32_t dc_txthresh;
+ uint32_t dc_eaddr[2];
+ uint8_t *dc_srom;
struct dc_mediainfo *dc_mi;
- struct dc_list_data *dc_ldata;
+ struct dc_list_data dc_ldata;
struct dc_chain_data dc_cdata;
struct callout dc_stat_ch;
struct callout dc_wdog_ch;
@@ -764,38 +782,36 @@ struct dc_softc {
#define DC_UNLOCK(_sc) mtx_unlock(&(_sc)->dc_mtx)
#define DC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->dc_mtx, MA_OWNED)
-#define DC_TX_POLL 0x00000001
-#define DC_TX_COALESCE 0x00000002
-#define DC_TX_ADMTEK_WAR 0x00000004
-#define DC_TX_USE_TX_INTR 0x00000008
-#define DC_RX_FILTER_TULIP 0x00000010
-#define DC_TX_INTR_FIRSTFRAG 0x00000020
-#define DC_PNIC_RX_BUG_WAR 0x00000040
-#define DC_TX_FIXED_RING 0x00000080
-#define DC_TX_STORENFWD 0x00000100
-#define DC_REDUCED_MII_POLL 0x00000200
-#define DC_TX_INTR_ALWAYS 0x00000400
-#define DC_21143_NWAY 0x00000800
-#define DC_128BIT_HASH 0x00001000
-#define DC_64BIT_HASH 0x00002000
-#define DC_TULIP_LEDS 0x00004000
-#define DC_TX_ONE 0x00008000
-#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */
+#define DC_TX_POLL 0x00000001
+#define DC_TX_COALESCE 0x00000002
+#define DC_TX_ADMTEK_WAR 0x00000004
+#define DC_TX_USE_TX_INTR 0x00000008
+#define DC_RX_FILTER_TULIP 0x00000010
+#define DC_TX_INTR_FIRSTFRAG 0x00000020
+#define DC_PNIC_RX_BUG_WAR 0x00000040
+#define DC_TX_FIXED_RING 0x00000080
+#define DC_TX_STORENFWD 0x00000100
+#define DC_REDUCED_MII_POLL 0x00000200
+#define DC_TX_INTR_ALWAYS 0x00000400
+#define DC_21143_NWAY 0x00000800
+#define DC_128BIT_HASH 0x00001000
+#define DC_64BIT_HASH 0x00002000
+#define DC_TULIP_LEDS 0x00004000
+#define DC_TX_ALIGN 0x00010000 /* align mbuf on tx */
/*
* register space access macros
*/
-#define CSR_WRITE_4(sc, reg, val) \
+#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val)
-#define CSR_READ_4(sc, reg) \
+#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg)
-#define CSR_BARRIER_4(sc, reg, flags) \
+#define CSR_BARRIER_4(sc, reg, flags) \
bus_space_barrier(sc->dc_btag, sc->dc_bhandle, reg, 4, flags)
-#define DC_TIMEOUT 1000
-#define ETHER_ALIGN 2
+#define DC_TIMEOUT 1000
/*
* General constants that are fun to know.
@@ -804,12 +820,12 @@ struct dc_softc {
/*
* DEC PCI vendor ID
*/
-#define DC_VENDORID_DEC 0x1011
+#define DC_VENDORID_DEC 0x1011
/*
* DEC/Intel 21143 PCI device ID
*/
-#define DC_DEVICEID_21143 0x0019
+#define DC_DEVICEID_21143 0x0019
/*
* Macronix PCI vendor ID
@@ -819,118 +835,118 @@ struct dc_softc {
/*
* Macronix PMAC device IDs.
*/
-#define DC_DEVICEID_98713 0x0512
-#define DC_DEVICEID_987x5 0x0531
-#define DC_DEVICEID_98727 0x0532
-#define DC_DEVICEID_98732 0x0532
+#define DC_DEVICEID_98713 0x0512
+#define DC_DEVICEID_987x5 0x0531
+#define DC_DEVICEID_98727 0x0532
+#define DC_DEVICEID_98732 0x0532
/* Macronix PCI revision codes. */
-#define DC_REVISION_98713 0x00
-#define DC_REVISION_98713A 0x10
-#define DC_REVISION_98715 0x20
-#define DC_REVISION_98715AEC_C 0x25
-#define DC_REVISION_98725 0x30
+#define DC_REVISION_98713 0x00
+#define DC_REVISION_98713A 0x10
+#define DC_REVISION_98715 0x20
+#define DC_REVISION_98715AEC_C 0x25
+#define DC_REVISION_98725 0x30
/*
* Compex PCI vendor ID.
*/
-#define DC_VENDORID_CP 0x11F6
+#define DC_VENDORID_CP 0x11F6
/*
* Compex PMAC PCI device IDs.
*/
-#define DC_DEVICEID_98713_CP 0x9881
+#define DC_DEVICEID_98713_CP 0x9881
/*
* Lite-On PNIC PCI vendor ID
*/
-#define DC_VENDORID_LO 0x11AD
+#define DC_VENDORID_LO 0x11AD
/*
* 82c168/82c169 PNIC device IDs. Both chips have the same device
* ID but different revisions. Revision 0x10 is the 82c168, and
* 0x20 is the 82c169.
*/
-#define DC_DEVICEID_82C168 0x0002
+#define DC_DEVICEID_82C168 0x0002
-#define DC_REVISION_82C168 0x10
-#define DC_REVISION_82C169 0x20
+#define DC_REVISION_82C168 0x10
+#define DC_REVISION_82C169 0x20
/*
* Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A
* with wake on lan/magic packet support.
*/
-#define DC_DEVICEID_82C115 0xc115
+#define DC_DEVICEID_82C115 0xc115
/*
* Davicom vendor ID.
*/
-#define DC_VENDORID_DAVICOM 0x1282
+#define DC_VENDORID_DAVICOM 0x1282
/*
* Davicom device IDs.
*/
-#define DC_DEVICEID_DM9009 0x9009
-#define DC_DEVICEID_DM9100 0x9100
-#define DC_DEVICEID_DM9102 0x9102
+#define DC_DEVICEID_DM9009 0x9009
+#define DC_DEVICEID_DM9100 0x9100
+#define DC_DEVICEID_DM9102 0x9102
/*
* The DM9102A has the same PCI device ID as the DM9102,
* but a higher revision code.
*/
-#define DC_REVISION_DM9102 0x10
-#define DC_REVISION_DM9102A 0x30
+#define DC_REVISION_DM9102 0x10
+#define DC_REVISION_DM9102A 0x30
/*
* ADMtek vendor ID.
*/
-#define DC_VENDORID_ADMTEK 0x1317
+#define DC_VENDORID_ADMTEK 0x1317
/*
* ADMtek device IDs.
*/
-#define DC_DEVICEID_AL981 0x0981
-#define DC_DEVICEID_AN983 0x0985
-#define DC_DEVICEID_AN985 0x1985
-#define DC_DEVICEID_ADM9511 0x9511
-#define DC_DEVICEID_ADM9513 0x9513
+#define DC_DEVICEID_AL981 0x0981
+#define DC_DEVICEID_AN983 0x0985
+#define DC_DEVICEID_AN985 0x1985
+#define DC_DEVICEID_ADM9511 0x9511
+#define DC_DEVICEID_ADM9513 0x9513
/*
* 3COM PCI vendor ID
*/
-#define DC_VENDORID_3COM 0x10b7
+#define DC_VENDORID_3COM 0x10b7
/*
* 3COM OfficeConnect 10/100B (3CSOHO100B-TX)
*/
-#define DC_DEVICEID_3CSOHOB 0x9300
+#define DC_DEVICEID_3CSOHOB 0x9300
/*
* ASIX vendor ID.
*/
-#define DC_VENDORID_ASIX 0x125B
+#define DC_VENDORID_ASIX 0x125B
/*
* ASIX device IDs.
*/
-#define DC_DEVICEID_AX88140A 0x1400
+#define DC_DEVICEID_AX88140A 0x1400
/*
* The ASIX AX88140 and ASIX AX88141 have the same vendor and
* device IDs but different revision values.
*/
-#define DC_REVISION_88140 0x00
-#define DC_REVISION_88141 0x10
+#define DC_REVISION_88140 0x00
+#define DC_REVISION_88141 0x10
/*
* Accton vendor ID.
*/
-#define DC_VENDORID_ACCTON 0x1113
+#define DC_VENDORID_ACCTON 0x1113
/*
* Accton device IDs.
*/
-#define DC_DEVICEID_EN1217 0x1217
+#define DC_DEVICEID_EN1217 0x1217
#define DC_DEVICEID_EN2242 0x1216
/*
@@ -956,69 +972,80 @@ struct dc_softc {
/*
* Abocom vendor ID
*/
-#define DC_VENDORID_ABOCOM 0x13d1
+#define DC_VENDORID_ABOCOM 0x13d1
/*
* Abocom device IDs.
*/
-#define DC_DEVICEID_FE2500 0xAB02
-#define DC_DEVICEID_FE2500MX 0xab08
+#define DC_DEVICEID_FE2500 0xAB02
+#define DC_DEVICEID_FE2500MX 0xab08
/*
* Conexant vendor ID.
*/
-#define DC_VENDORID_CONEXANT 0x14f1
+#define DC_VENDORID_CONEXANT 0x14f1
/*
* Conexant device IDs.
*/
-#define DC_DEVICEID_RS7112 0x1803
+#define DC_DEVICEID_RS7112 0x1803
/*
* Planex vendor ID
*/
-#define DC_VENDORID_PLANEX 0x14ea
+#define DC_VENDORID_PLANEX 0x14ea
/*
* Planex device IDs.
*/
-#define DC_DEVICEID_FNW3602T 0xab08
+#define DC_DEVICEID_FNW3602T 0xab08
/*
* Not sure who this vendor should be, so we'll go with HAWKING until
* I can locate the right one.
*/
-#define DC_VENDORID_HAWKING 0x17b3
+#define DC_VENDORID_HAWKING 0x17b3
/*
* Sure looks like an abocom device ID, but it found on my hawking PN672TX
* card. Use that for now, and upgrade later.
*/
-#define DC_DEVICEID_HAWKING_PN672TX 0xab08
+#define DC_DEVICEID_HAWKING_PN672TX 0xab08
/*
* Microsoft device ID.
*/
-#define DC_VENDORID_MICROSOFT 0x1414
+#define DC_VENDORID_MICROSOFT 0x1414
/*
* Supported Microsoft PCI and cardbus NICs. These are really
* ADMtek parts in disguise.
*/
-#define DC_DEVICEID_MSMN120 0x0001
-#define DC_DEVICEID_MSMN130 0x0002
+#define DC_DEVICEID_MSMN120 0x0001
+#define DC_DEVICEID_MSMN130 0x0002
/*
* Linksys vendor ID.
*/
-#define DC_VENDORID_LINKSYS 0x1737
+#define DC_VENDORID_LINKSYS 0x1737
/*
* Linksys device IDs.
*/
-#define DC_DEVICEID_PCMPC200_AB08 0xab08
-#define DC_DEVICEID_PCMPC200_AB09 0xab09
+#define DC_DEVICEID_PCMPC200_AB08 0xab08
+#define DC_DEVICEID_PCMPC200_AB09 0xab09
+
+/*
+ * ULi vendor ID.
+ */
+#define DC_VENDORID_ULI 0x10b9
+
+/*
+ * ULi device IDs.
+ */
+#define DC_DEVICEID_M5261 0x5261
+#define DC_DEVICEID_M5263 0x5263
#define DC_DEVID(vendor, device) ((device) << 16 | (vendor))
@@ -1027,112 +1054,114 @@ struct dc_softc {
* other PCI registers.
*/
-#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */
-#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */
-#define DC_PCI_CFDD 0x40 /* Device and driver area */
-#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
-#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
-#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
-#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
-#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
+#define DC_PCI_CFBIO PCIR_BAR(0) /* Base I/O address */
+#define DC_PCI_CFBMA PCIR_BAR(1) /* Base memory address */
+#define DC_PCI_CFDD 0x40 /* Device and driver area */
+#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */
+#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */
+#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */
+#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */
+#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */
-#define DC_21143_PB_REV 0x00000030
-#define DC_21143_TB_REV 0x00000030
-#define DC_21143_PC_REV 0x00000030
-#define DC_21143_TC_REV 0x00000030
-#define DC_21143_PD_REV 0x00000041
-#define DC_21143_TD_REV 0x00000041
+#define DC_21143_PB_REV 0x00000030
+#define DC_21143_TB_REV 0x00000030
+#define DC_21143_PC_REV 0x00000030
+#define DC_21143_TC_REV 0x00000030
+#define DC_21143_PD_REV 0x00000041
+#define DC_21143_TD_REV 0x00000041
/* Configuration and driver area */
-#define DC_CFDD_DRVUSE 0x0000FFFF
-#define DC_CFDD_SNOOZE_MODE 0x40000000
-#define DC_CFDD_SLEEP_MODE 0x80000000
+#define DC_CFDD_DRVUSE 0x0000FFFF
+#define DC_CFDD_SNOOZE_MODE 0x40000000
+#define DC_CFDD_SLEEP_MODE 0x80000000
/* Configuration wake-up command register */
-#define DC_CWUC_MUST_BE_ZERO 0x00000001
-#define DC_CWUC_SECUREON_ENB 0x00000002
-#define DC_CWUC_FORCE_WUL 0x00000004
-#define DC_CWUC_BNC_ABILITY 0x00000008
-#define DC_CWUC_AUI_ABILITY 0x00000010
-#define DC_CWUC_TP10_ABILITY 0x00000020
-#define DC_CWUC_MII_ABILITY 0x00000040
-#define DC_CWUC_SYM_ABILITY 0x00000080
-#define DC_CWUC_LOCK 0x00000100
+#define DC_CWUC_MUST_BE_ZERO 0x00000001
+#define DC_CWUC_SECUREON_ENB 0x00000002
+#define DC_CWUC_FORCE_WUL 0x00000004
+#define DC_CWUC_BNC_ABILITY 0x00000008
+#define DC_CWUC_AUI_ABILITY 0x00000010
+#define DC_CWUC_TP10_ABILITY 0x00000020
+#define DC_CWUC_MII_ABILITY 0x00000040
+#define DC_CWUC_SYM_ABILITY 0x00000080
+#define DC_CWUC_LOCK 0x00000100
/*
* SROM nonsense.
*/
-#define DC_IB_CTLRCNT 0x13
-#define DC_IB_LEAF0_CNUM 0x1A
-#define DC_IB_LEAF0_OFFSET 0x1B
+#define DC_ROM_SIZE(bits) (2 << (bits))
+
+#define DC_IB_CTLRCNT 0x13
+#define DC_IB_LEAF0_CNUM 0x1A
+#define DC_IB_LEAF0_OFFSET 0x1B
struct dc_info_leaf {
- u_int16_t dc_conntype;
- u_int8_t dc_blkcnt;
- u_int8_t dc_rsvd;
- u_int16_t dc_infoblk;
+ uint16_t dc_conntype;
+ uint8_t dc_blkcnt;
+ uint8_t dc_rsvd;
+ uint16_t dc_infoblk;
};
-#define DC_CTYPE_10BT 0x0000
-#define DC_CTYPE_10BT_NWAY 0x0100
-#define DC_CTYPE_10BT_FDX 0x0204
-#define DC_CTYPE_10B2 0x0001
-#define DC_CTYPE_10B5 0x0002
-#define DC_CTYPE_100BT 0x0003
-#define DC_CTYPE_100BT_FDX 0x0205
-#define DC_CTYPE_100T4 0x0006
-#define DC_CTYPE_100FX 0x0007
-#define DC_CTYPE_100FX_FDX 0x0208
-#define DC_CTYPE_MII_10BT 0x0009
-#define DC_CTYPE_MII_10BT_FDX 0x020A
-#define DC_CTYPE_MII_100BT 0x000D
-#define DC_CTYPE_MII_100BT_FDX 0x020E
-#define DC_CTYPE_MII_100T4 0x000F
-#define DC_CTYPE_MII_100FX 0x0010
-#define DC_CTYPE_MII_100FX_FDX 0x0211
-#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800
-#define DC_CTYPE_PUP_AUTOSENSE 0x8800
-#define DC_CTYPE_NOMEDIA 0xFFFF
-
-#define DC_EBLOCK_SIA 0x0002
-#define DC_EBLOCK_MII 0x0003
-#define DC_EBLOCK_SYM 0x0004
-#define DC_EBLOCK_RESET 0x0005
-#define DC_EBLOCK_PHY_SHUTDOWN 0x0006
+#define DC_CTYPE_10BT 0x0000
+#define DC_CTYPE_10BT_NWAY 0x0100
+#define DC_CTYPE_10BT_FDX 0x0204
+#define DC_CTYPE_10B2 0x0001
+#define DC_CTYPE_10B5 0x0002
+#define DC_CTYPE_100BT 0x0003
+#define DC_CTYPE_100BT_FDX 0x0205
+#define DC_CTYPE_100T4 0x0006
+#define DC_CTYPE_100FX 0x0007
+#define DC_CTYPE_100FX_FDX 0x0208
+#define DC_CTYPE_MII_10BT 0x0009
+#define DC_CTYPE_MII_10BT_FDX 0x020A
+#define DC_CTYPE_MII_100BT 0x000D
+#define DC_CTYPE_MII_100BT_FDX 0x020E
+#define DC_CTYPE_MII_100T4 0x000F
+#define DC_CTYPE_MII_100FX 0x0010
+#define DC_CTYPE_MII_100FX_FDX 0x0211
+#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800
+#define DC_CTYPE_PUP_AUTOSENSE 0x8800
+#define DC_CTYPE_NOMEDIA 0xFFFF
+
+#define DC_EBLOCK_SIA 0x0002
+#define DC_EBLOCK_MII 0x0003
+#define DC_EBLOCK_SYM 0x0004
+#define DC_EBLOCK_RESET 0x0005
+#define DC_EBLOCK_PHY_SHUTDOWN 0x0006
struct dc_leaf_hdr {
- u_int16_t dc_mtype;
- u_int8_t dc_mcnt;
- u_int8_t dc_rsvd;
+ uint16_t dc_mtype;
+ uint8_t dc_mcnt;
+ uint8_t dc_rsvd;
};
struct dc_eblock_hdr {
- u_int8_t dc_len;
- u_int8_t dc_type;
+ uint8_t dc_len;
+ uint8_t dc_type;
};
struct dc_eblock_sia {
struct dc_eblock_hdr dc_sia_hdr;
- u_int8_t dc_sia_code;
+ uint8_t dc_sia_code;
union {
struct dc_sia_ext { /* if (dc_sia_code & DC_SIA_CODE_EXT) */
- u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
- u_int8_t dc_sia_gpio_ctl[2];
- u_int8_t dc_sia_gpio_dat[2];
+ uint8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */
+ uint8_t dc_sia_gpio_ctl[2];
+ uint8_t dc_sia_gpio_dat[2];
} dc_sia_ext;
struct dc_sia_noext {
- u_int8_t dc_sia_gpio_ctl[2];
- u_int8_t dc_sia_gpio_dat[2];
+ uint8_t dc_sia_gpio_ctl[2];
+ uint8_t dc_sia_gpio_dat[2];
} dc_sia_noext;
} dc_un;
};
-#define DC_SIA_CODE_10BT 0x00
-#define DC_SIA_CODE_10B2 0x01
-#define DC_SIA_CODE_10B5 0x02
-#define DC_SIA_CODE_10BT_FDX 0x04
-#define DC_SIA_CODE_EXT 0x40
+#define DC_SIA_CODE_10BT 0x00
+#define DC_SIA_CODE_10B2 0x01
+#define DC_SIA_CODE_10B5 0x02
+#define DC_SIA_CODE_10BT_FDX 0x04
+#define DC_SIA_CODE_EXT 0x40
/*
* Note that the first word in the gpr and reset
@@ -1140,11 +1169,11 @@ struct dc_eblock_sia {
*/
struct dc_eblock_mii {
struct dc_eblock_hdr dc_mii_hdr;
- u_int8_t dc_mii_phynum;
- u_int8_t dc_gpr_len;
-/* u_int16_t dc_gpr_dat[n]; */
-/* u_int8_t dc_reset_len; */
-/* u_int16_t dc_reset_dat[n]; */
+ uint8_t dc_mii_phynum;
+ uint8_t dc_gpr_len;
+/* uint16_t dc_gpr_dat[n]; */
+/* uint8_t dc_reset_len; */
+/* uint16_t dc_reset_dat[n]; */
/* There are other fields after these, but we don't
* care about them since they can be determined by looking
* at the PHY.
@@ -1153,20 +1182,20 @@ struct dc_eblock_mii {
struct dc_eblock_sym {
struct dc_eblock_hdr dc_sym_hdr;
- u_int8_t dc_sym_code;
- u_int8_t dc_sym_gpio_ctl[2];
- u_int8_t dc_sym_gpio_dat[2];
- u_int8_t dc_sym_cmd[2];
+ uint8_t dc_sym_code;
+ uint8_t dc_sym_gpio_ctl[2];
+ uint8_t dc_sym_gpio_dat[2];
+ uint8_t dc_sym_cmd[2];
};
-#define DC_SYM_CODE_100BT 0x03
-#define DC_SYM_CODE_100BT_FDX 0x05
-#define DC_SYM_CODE_100T4 0x06
-#define DC_SYM_CODE_100FX 0x07
-#define DC_SYM_CODE_100FX_FDX 0x08
+#define DC_SYM_CODE_100BT 0x03
+#define DC_SYM_CODE_100BT_FDX 0x05
+#define DC_SYM_CODE_100T4 0x06
+#define DC_SYM_CODE_100FX 0x07
+#define DC_SYM_CODE_100FX_FDX 0x08
struct dc_eblock_reset {
struct dc_eblock_hdr dc_reset_hdr;
- u_int8_t dc_reset_len;
-/* u_int16_t dc_reset_dat[n]; */
+ uint8_t dc_reset_len;
+/* uint16_t dc_reset_dat[n]; */
};
diff --git a/freebsd/sys/dev/dc/pnphy.c b/freebsd/sys/dev/dc/pnphy.c
index b59ddf61..0b589e82 100644
--- a/freebsd/sys/dev/dc/pnphy.c
+++ b/freebsd/sys/dev/dc/pnphy.c
@@ -68,14 +68,6 @@ __FBSDID("$FreeBSD$");
#include <rtems/bsd/local/miibus_if.h>
-#define DC_SETBIT(sc, reg, x) \
- CSR_WRITE_4(sc, reg, \
- CSR_READ_4(sc, reg) | x)
-
-#define DC_CLRBIT(sc, reg, x) \
- CSR_WRITE_4(sc, reg, \
- CSR_READ_4(sc, reg) & ~x)
-
static int pnphy_probe(device_t);
static int pnphy_attach(device_t);
@@ -85,7 +77,7 @@ static device_method_t pnphy_methods[] = {
DEVMETHOD(device_attach, pnphy_attach),
DEVMETHOD(device_detach, mii_phy_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
- { 0, 0 }
+ DEVMETHOD_END
};
static devclass_t pnphy_devclass;
@@ -143,7 +135,7 @@ pnphy_attach(device_t dev)
/*
* Apparently, we can neither isolate nor do loopback.
*/
- sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
+ sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE;
sc->mii_capabilities =
BMSR_100TXFDX | BMSR_100TXHDX | BMSR_10TFDX | BMSR_10THDX;
@@ -172,23 +164,19 @@ pnphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
+ /*
+ * Note that auto-negotiation is broken on this chip.
+ */
switch (IFM_SUBTYPE(ife->ifm_media)) {
- case IFM_AUTO:
- /* NWAY is busted on this chip */
- case IFM_100_T4:
- /*
- * XXX Not supported as a manual setting right now.
- */
- return (EINVAL);
case IFM_100_TX:
mii->mii_media_active = IFM_ETHER | IFM_100_TX;
- if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
+ if ((ife->ifm_media & IFM_FDX) != 0)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return (0);
case IFM_10_T:
mii->mii_media_active = IFM_ETHER | IFM_10_T;
- if ((ife->ifm_media & IFM_GMASK) == IFM_FDX)
+ if ((ife->ifm_media & IFM_FDX) != 0)
mii->mii_media_active |= IFM_FDX;
MIIBUS_STATCHG(sc->mii_dev);
return (0);
@@ -228,15 +216,14 @@ pnphy_status(struct mii_softc *sc)
mii->mii_media_active = IFM_ETHER;
reg = CSR_READ_4(dc_sc, DC_ISR);
-
if (!(reg & DC_ISR_LINKFAIL))
mii->mii_media_status |= IFM_ACTIVE;
-
- if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)
+ reg = CSR_READ_4(dc_sc, DC_NETCFG);
+ if (reg & DC_NETCFG_SPEEDSEL)
mii->mii_media_active |= IFM_10_T;
else
mii->mii_media_active |= IFM_100_TX;
- if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)
+ if (reg & DC_NETCFG_FULLDUPLEX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 05:56:47 +0000