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authorSebastian Huber <sebastian.huber@embedded-brains.de>2013-10-09 22:42:09 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2013-10-10 09:06:58 +0200
commitbceabc95c1c85d793200446fa85f1ddc6313ea29 (patch)
tree973c8bd8deca9fd69913f2895cc91e0e6114d46c /freebsd/sys/dev/bfe
parentAdd FreeBSD sources as a submodule (diff)
downloadrtems-libbsd-bceabc95c1c85d793200446fa85f1ddc6313ea29.tar.bz2
Move files to match FreeBSD layout
Diffstat (limited to 'freebsd/sys/dev/bfe')
-rw-r--r--freebsd/sys/dev/bfe/if_bfe.c1973
-rw-r--r--freebsd/sys/dev/bfe/if_bfereg.h626
2 files changed, 2599 insertions, 0 deletions
diff --git a/freebsd/sys/dev/bfe/if_bfe.c b/freebsd/sys/dev/bfe/if_bfe.c
new file mode 100644
index 00000000..7ce821b8
--- /dev/null
+++ b/freebsd/sys/dev/bfe/if_bfe.c
@@ -0,0 +1,1973 @@
+#include <freebsd/machine/rtems-bsd-config.h>
+
+/*-
+ * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
+ * and Duncan Barclay<dmlb@dmlb.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#include <freebsd/sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <freebsd/sys/param.h>
+#include <freebsd/sys/systm.h>
+#include <freebsd/sys/bus.h>
+#include <freebsd/sys/endian.h>
+#include <freebsd/sys/kernel.h>
+#include <freebsd/sys/malloc.h>
+#include <freebsd/sys/mbuf.h>
+#include <freebsd/sys/module.h>
+#include <freebsd/sys/rman.h>
+#include <freebsd/sys/socket.h>
+#include <freebsd/sys/sockio.h>
+#include <freebsd/sys/sysctl.h>
+
+#include <freebsd/net/bpf.h>
+#include <freebsd/net/if.h>
+#include <freebsd/net/ethernet.h>
+#include <freebsd/net/if_dl.h>
+#include <freebsd/net/if_media.h>
+#include <freebsd/net/if_types.h>
+#include <freebsd/net/if_vlan_var.h>
+
+#include <freebsd/dev/mii/mii.h>
+#include <freebsd/dev/mii/miivar.h>
+
+#include <freebsd/dev/pci/pcireg.h>
+#include <freebsd/dev/pci/pcivar.h>
+
+#include <freebsd/machine/bus.h>
+
+#include <freebsd/dev/bfe/if_bfereg.h>
+
+MODULE_DEPEND(bfe, pci, 1, 1, 1);
+MODULE_DEPEND(bfe, ether, 1, 1, 1);
+MODULE_DEPEND(bfe, miibus, 1, 1, 1);
+
+/* "device miibus" required. See GENERIC if you get errors here. */
+#include <freebsd/local/miibus_if.h>
+
+#define BFE_DEVDESC_MAX 64 /* Maximum device description length */
+
+static struct bfe_type bfe_devs[] = {
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
+ "Broadcom BCM4401 Fast Ethernet" },
+ { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
+ "Broadcom BCM4401-B0 Fast Ethernet" },
+ { 0, 0, NULL }
+};
+
+static int bfe_probe (device_t);
+static int bfe_attach (device_t);
+static int bfe_detach (device_t);
+static int bfe_suspend (device_t);
+static int bfe_resume (device_t);
+static void bfe_release_resources (struct bfe_softc *);
+static void bfe_intr (void *);
+static int bfe_encap (struct bfe_softc *, struct mbuf **);
+static void bfe_start (struct ifnet *);
+static void bfe_start_locked (struct ifnet *);
+static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
+static void bfe_init (void *);
+static void bfe_init_locked (void *);
+static void bfe_stop (struct bfe_softc *);
+static void bfe_watchdog (struct bfe_softc *);
+static int bfe_shutdown (device_t);
+static void bfe_tick (void *);
+static void bfe_txeof (struct bfe_softc *);
+static void bfe_rxeof (struct bfe_softc *);
+static void bfe_set_rx_mode (struct bfe_softc *);
+static int bfe_list_rx_init (struct bfe_softc *);
+static void bfe_list_tx_init (struct bfe_softc *);
+static void bfe_discard_buf (struct bfe_softc *, int);
+static int bfe_list_newbuf (struct bfe_softc *, int);
+static void bfe_rx_ring_free (struct bfe_softc *);
+
+static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
+static int bfe_ifmedia_upd (struct ifnet *);
+static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
+static int bfe_miibus_readreg (device_t, int, int);
+static int bfe_miibus_writereg (device_t, int, int, int);
+static void bfe_miibus_statchg (device_t);
+static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
+ u_long, const int);
+static void bfe_get_config (struct bfe_softc *sc);
+static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
+static void bfe_stats_update (struct bfe_softc *);
+static void bfe_clear_stats (struct bfe_softc *);
+static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
+static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
+static int bfe_resetphy (struct bfe_softc *);
+static int bfe_setupphy (struct bfe_softc *);
+static void bfe_chip_reset (struct bfe_softc *);
+static void bfe_chip_halt (struct bfe_softc *);
+static void bfe_core_reset (struct bfe_softc *);
+static void bfe_core_disable (struct bfe_softc *);
+static int bfe_dma_alloc (struct bfe_softc *);
+static void bfe_dma_free (struct bfe_softc *sc);
+static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
+static void bfe_cam_write (struct bfe_softc *, u_char *, int);
+static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS);
+
+static device_method_t bfe_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, bfe_probe),
+ DEVMETHOD(device_attach, bfe_attach),
+ DEVMETHOD(device_detach, bfe_detach),
+ DEVMETHOD(device_shutdown, bfe_shutdown),
+ DEVMETHOD(device_suspend, bfe_suspend),
+ DEVMETHOD(device_resume, bfe_resume),
+
+ /* bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
+ DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
+ DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
+
+ { 0, 0 }
+};
+
+static driver_t bfe_driver = {
+ "bfe",
+ bfe_methods,
+ sizeof(struct bfe_softc)
+};
+
+static devclass_t bfe_devclass;
+
+DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
+DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
+
+/*
+ * Probe for a Broadcom 4401 chip.
+ */
+static int
+bfe_probe(device_t dev)
+{
+ struct bfe_type *t;
+
+ t = bfe_devs;
+
+ while (t->bfe_name != NULL) {
+ if (pci_get_vendor(dev) == t->bfe_vid &&
+ pci_get_device(dev) == t->bfe_did) {
+ device_set_desc(dev, t->bfe_name);
+ return (BUS_PROBE_DEFAULT);
+ }
+ t++;
+ }
+
+ return (ENXIO);
+}
+
+struct bfe_dmamap_arg {
+ bus_addr_t bfe_busaddr;
+};
+
+static int
+bfe_dma_alloc(struct bfe_softc *sc)
+{
+ struct bfe_dmamap_arg ctx;
+ struct bfe_rx_data *rd;
+ struct bfe_tx_data *td;
+ int error, i;
+
+ /*
+ * parent tag. Apparently the chip cannot handle any DMA address
+ * greater than 1GB.
+ */
+ error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
+ 1, 0, /* alignment, boundary */
+ BFE_DMA_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
+ 0, /* nsegments */
+ BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->bfe_parent_tag);
+ if (error != 0) {
+ device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
+ goto fail;
+ }
+
+ /* Create tag for Tx ring. */
+ error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
+ BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ BFE_TX_LIST_SIZE, /* maxsize */
+ 1, /* nsegments */
+ BFE_TX_LIST_SIZE, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->bfe_tx_tag);
+ if (error != 0) {
+ device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
+ goto fail;
+ }
+
+ /* Create tag for Rx ring. */
+ error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
+ BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ BFE_RX_LIST_SIZE, /* maxsize */
+ 1, /* nsegments */
+ BFE_RX_LIST_SIZE, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->bfe_rx_tag);
+ if (error != 0) {
+ device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
+ goto fail;
+ }
+
+ /* Create tag for Tx buffers. */
+ error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
+ 1, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
+ BFE_MAXTXSEGS, /* nsegments */
+ MCLBYTES, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->bfe_txmbuf_tag);
+ if (error != 0) {
+ device_printf(sc->bfe_dev,
+ "cannot create Tx buffer DMA tag.\n");
+ goto fail;
+ }
+
+ /* Create tag for Rx buffers. */
+ error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
+ 1, 0, /* alignment, boundary */
+ BUS_SPACE_MAXADDR, /* lowaddr */
+ BUS_SPACE_MAXADDR, /* highaddr */
+ NULL, NULL, /* filter, filterarg */
+ MCLBYTES, /* maxsize */
+ 1, /* nsegments */
+ MCLBYTES, /* maxsegsize */
+ 0, /* flags */
+ NULL, NULL, /* lockfunc, lockarg */
+ &sc->bfe_rxmbuf_tag);
+ if (error != 0) {
+ device_printf(sc->bfe_dev,
+ "cannot create Rx buffer DMA tag.\n");
+ goto fail;
+ }
+
+ /* Allocate DMA'able memory and load DMA map. */
+ error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
+ BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
+ if (error != 0) {
+ device_printf(sc->bfe_dev,
+ "cannot allocate DMA'able memory for Tx ring.\n");
+ goto fail;
+ }
+ ctx.bfe_busaddr = 0;
+ error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
+ sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
+ BUS_DMA_NOWAIT);
+ if (error != 0 || ctx.bfe_busaddr == 0) {
+ device_printf(sc->bfe_dev,
+ "cannot load DMA'able memory for Tx ring.\n");
+ goto fail;
+ }
+ sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
+
+ error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
+ BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
+ if (error != 0) {
+ device_printf(sc->bfe_dev,
+ "cannot allocate DMA'able memory for Rx ring.\n");
+ goto fail;
+ }
+ ctx.bfe_busaddr = 0;
+ error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
+ sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
+ BUS_DMA_NOWAIT);
+ if (error != 0 || ctx.bfe_busaddr == 0) {
+ device_printf(sc->bfe_dev,
+ "cannot load DMA'able memory for Rx ring.\n");
+ goto fail;
+ }
+ sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
+
+ /* Create DMA maps for Tx buffers. */
+ for (i = 0; i < BFE_TX_LIST_CNT; i++) {
+ td = &sc->bfe_tx_ring[i];
+ td->bfe_mbuf = NULL;
+ td->bfe_map = NULL;
+ error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
+ if (error != 0) {
+ device_printf(sc->bfe_dev,
+ "cannot create DMA map for Tx.\n");
+ goto fail;
+ }
+ }
+
+ /* Create spare DMA map for Rx buffers. */
+ error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
+ if (error != 0) {
+ device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
+ goto fail;
+ }
+ /* Create DMA maps for Rx buffers. */
+ for (i = 0; i < BFE_RX_LIST_CNT; i++) {
+ rd = &sc->bfe_rx_ring[i];
+ rd->bfe_mbuf = NULL;
+ rd->bfe_map = NULL;
+ rd->bfe_ctrl = 0;
+ error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
+ if (error != 0) {
+ device_printf(sc->bfe_dev,
+ "cannot create DMA map for Rx.\n");
+ goto fail;
+ }
+ }
+
+fail:
+ return (error);
+}
+
+static void
+bfe_dma_free(struct bfe_softc *sc)
+{
+ struct bfe_tx_data *td;
+ struct bfe_rx_data *rd;
+ int i;
+
+ /* Tx ring. */
+ if (sc->bfe_tx_tag != NULL) {
+ if (sc->bfe_tx_map != NULL)
+ bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
+ if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL)
+ bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
+ sc->bfe_tx_map);
+ sc->bfe_tx_map = NULL;
+ sc->bfe_tx_list = NULL;
+ bus_dma_tag_destroy(sc->bfe_tx_tag);
+ sc->bfe_tx_tag = NULL;
+ }
+
+ /* Rx ring. */
+ if (sc->bfe_rx_tag != NULL) {
+ if (sc->bfe_rx_map != NULL)
+ bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
+ if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL)
+ bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
+ sc->bfe_rx_map);
+ sc->bfe_rx_map = NULL;
+ sc->bfe_rx_list = NULL;
+ bus_dma_tag_destroy(sc->bfe_rx_tag);
+ sc->bfe_rx_tag = NULL;
+ }
+
+ /* Tx buffers. */
+ if (sc->bfe_txmbuf_tag != NULL) {
+ for (i = 0; i < BFE_TX_LIST_CNT; i++) {
+ td = &sc->bfe_tx_ring[i];
+ if (td->bfe_map != NULL) {
+ bus_dmamap_destroy(sc->bfe_txmbuf_tag,
+ td->bfe_map);
+ td->bfe_map = NULL;
+ }
+ }
+ bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
+ sc->bfe_txmbuf_tag = NULL;
+ }
+
+ /* Rx buffers. */
+ if (sc->bfe_rxmbuf_tag != NULL) {
+ for (i = 0; i < BFE_RX_LIST_CNT; i++) {
+ rd = &sc->bfe_rx_ring[i];
+ if (rd->bfe_map != NULL) {
+ bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
+ rd->bfe_map);
+ rd->bfe_map = NULL;
+ }
+ }
+ if (sc->bfe_rx_sparemap != NULL) {
+ bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
+ sc->bfe_rx_sparemap);
+ sc->bfe_rx_sparemap = NULL;
+ }
+ bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
+ sc->bfe_rxmbuf_tag = NULL;
+ }
+
+ if (sc->bfe_parent_tag != NULL) {
+ bus_dma_tag_destroy(sc->bfe_parent_tag);
+ sc->bfe_parent_tag = NULL;
+ }
+}
+
+static int
+bfe_attach(device_t dev)
+{
+ struct ifnet *ifp = NULL;
+ struct bfe_softc *sc;
+ int error = 0, rid;
+
+ sc = device_get_softc(dev);
+ mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+ MTX_DEF);
+ callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
+
+ sc->bfe_dev = dev;
+
+ /*
+ * Map control/status registers.
+ */
+ pci_enable_busmaster(dev);
+
+ rid = PCIR_BAR(0);
+ sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->bfe_res == NULL) {
+ device_printf(dev, "couldn't map memory\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ /* Allocate interrupt */
+ rid = 0;
+
+ sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_SHAREABLE | RF_ACTIVE);
+ if (sc->bfe_irq == NULL) {
+ device_printf(dev, "couldn't map interrupt\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ if (bfe_dma_alloc(sc) != 0) {
+ device_printf(dev, "failed to allocate DMA resources\n");
+ error = ENXIO;
+ goto fail;
+ }
+
+ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+ SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
+ "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats,
+ "I", "Statistics");
+
+ /* Set up ifnet structure */
+ ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
+ if (ifp == NULL) {
+ device_printf(dev, "failed to if_alloc()\n");
+ error = ENOSPC;
+ goto fail;
+ }
+ ifp->if_softc = sc;
+ if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = bfe_ioctl;
+ ifp->if_start = bfe_start;
+ ifp->if_init = bfe_init;
+ ifp->if_mtu = ETHERMTU;
+ IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
+ ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
+ IFQ_SET_READY(&ifp->if_snd);
+
+ bfe_get_config(sc);
+
+ /* Reset the chip and turn on the PHY */
+ BFE_LOCK(sc);
+ bfe_chip_reset(sc);
+ BFE_UNLOCK(sc);
+
+ error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
+ bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
+ 0);
+ if (error != 0) {
+ device_printf(dev, "attaching PHYs failed\n");
+ goto fail;
+ }
+
+ ether_ifattach(ifp, sc->bfe_enaddr);
+
+ /*
+ * Tell the upper layer(s) we support long frames.
+ */
+ ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
+ ifp->if_capabilities |= IFCAP_VLAN_MTU;
+ ifp->if_capenable |= IFCAP_VLAN_MTU;
+
+ /*
+ * Hook interrupt last to avoid having to lock softc
+ */
+ error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ NULL, bfe_intr, sc, &sc->bfe_intrhand);
+
+ if (error) {
+ device_printf(dev, "couldn't set up irq\n");
+ goto fail;
+ }
+fail:
+ if (error != 0)
+ bfe_detach(dev);
+ return (error);
+}
+
+static int
+bfe_detach(device_t dev)
+{
+ struct bfe_softc *sc;
+ struct ifnet *ifp;
+
+ sc = device_get_softc(dev);
+
+ ifp = sc->bfe_ifp;
+
+ if (device_is_attached(dev)) {
+ BFE_LOCK(sc);
+ sc->bfe_flags |= BFE_FLAG_DETACH;
+ bfe_stop(sc);
+ BFE_UNLOCK(sc);
+ callout_drain(&sc->bfe_stat_co);
+ if (ifp != NULL)
+ ether_ifdetach(ifp);
+ }
+
+ BFE_LOCK(sc);
+ bfe_chip_reset(sc);
+ BFE_UNLOCK(sc);
+
+ bus_generic_detach(dev);
+ if (sc->bfe_miibus != NULL)
+ device_delete_child(dev, sc->bfe_miibus);
+
+ bfe_release_resources(sc);
+ bfe_dma_free(sc);
+ mtx_destroy(&sc->bfe_mtx);
+
+ return (0);
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static int
+bfe_shutdown(device_t dev)
+{
+ struct bfe_softc *sc;
+
+ sc = device_get_softc(dev);
+ BFE_LOCK(sc);
+ bfe_stop(sc);
+
+ BFE_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+bfe_suspend(device_t dev)
+{
+ struct bfe_softc *sc;
+
+ sc = device_get_softc(dev);
+ BFE_LOCK(sc);
+ bfe_stop(sc);
+ BFE_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+bfe_resume(device_t dev)
+{
+ struct bfe_softc *sc;
+ struct ifnet *ifp;
+
+ sc = device_get_softc(dev);
+ ifp = sc->bfe_ifp;
+ BFE_LOCK(sc);
+ bfe_chip_reset(sc);
+ if (ifp->if_flags & IFF_UP) {
+ bfe_init_locked(sc);
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
+ !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ bfe_start_locked(ifp);
+ }
+ BFE_UNLOCK(sc);
+
+ return (0);
+}
+
+static int
+bfe_miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct bfe_softc *sc;
+ u_int32_t ret;
+
+ sc = device_get_softc(dev);
+ bfe_readphy(sc, reg, &ret);
+
+ return (ret);
+}
+
+static int
+bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
+{
+ struct bfe_softc *sc;
+
+ sc = device_get_softc(dev);
+ bfe_writephy(sc, reg, val);
+
+ return (0);
+}
+
+static void
+bfe_miibus_statchg(device_t dev)
+{
+ struct bfe_softc *sc;
+ struct mii_data *mii;
+ u_int32_t val, flow;
+
+ sc = device_get_softc(dev);
+ mii = device_get_softc(sc->bfe_miibus);
+
+ sc->bfe_flags &= ~BFE_FLAG_LINK;
+ if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+ (IFM_ACTIVE | IFM_AVALID)) {
+ switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ case IFM_10_T:
+ case IFM_100_TX:
+ sc->bfe_flags |= BFE_FLAG_LINK;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* XXX Should stop Rx/Tx engine prior to touching MAC. */
+ val = CSR_READ_4(sc, BFE_TX_CTRL);
+ val &= ~BFE_TX_DUPLEX;
+ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
+ val |= BFE_TX_DUPLEX;
+ flow = 0;
+#ifdef notyet
+ flow = CSR_READ_4(sc, BFE_RXCONF);
+ flow &= ~BFE_RXCONF_FLOW;
+ if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
+ IFM_ETH_RXPAUSE) != 0)
+ flow |= BFE_RXCONF_FLOW;
+ CSR_WRITE_4(sc, BFE_RXCONF, flow);
+ /*
+ * It seems that the hardware has Tx pause issues
+ * so enable only Rx pause.
+ */
+ flow = CSR_READ_4(sc, BFE_MAC_FLOW);
+ flow &= ~BFE_FLOW_PAUSE_ENAB;
+ CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
+#endif
+ }
+ CSR_WRITE_4(sc, BFE_TX_CTRL, val);
+}
+
+static void
+bfe_tx_ring_free(struct bfe_softc *sc)
+{
+ int i;
+
+ for(i = 0; i < BFE_TX_LIST_CNT; i++) {
+ if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
+ bus_dmamap_sync(sc->bfe_txmbuf_tag,
+ sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->bfe_txmbuf_tag,
+ sc->bfe_tx_ring[i].bfe_map);
+ m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
+ sc->bfe_tx_ring[i].bfe_mbuf = NULL;
+ }
+ }
+ bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
+ bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+}
+
+static void
+bfe_rx_ring_free(struct bfe_softc *sc)
+{
+ int i;
+
+ for (i = 0; i < BFE_RX_LIST_CNT; i++) {
+ if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
+ bus_dmamap_sync(sc->bfe_rxmbuf_tag,
+ sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->bfe_rxmbuf_tag,
+ sc->bfe_rx_ring[i].bfe_map);
+ m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
+ sc->bfe_rx_ring[i].bfe_mbuf = NULL;
+ }
+ }
+ bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
+ bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+}
+
+static int
+bfe_list_rx_init(struct bfe_softc *sc)
+{
+ struct bfe_rx_data *rd;
+ int i;
+
+ sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
+ bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
+ for (i = 0; i < BFE_RX_LIST_CNT; i++) {
+ rd = &sc->bfe_rx_ring[i];
+ rd->bfe_mbuf = NULL;
+ rd->bfe_ctrl = 0;
+ if (bfe_list_newbuf(sc, i) != 0)
+ return (ENOBUFS);
+ }
+
+ bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+ CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
+
+ return (0);
+}
+
+static void
+bfe_list_tx_init(struct bfe_softc *sc)
+{
+ int i;
+
+ sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
+ bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
+ for (i = 0; i < BFE_TX_LIST_CNT; i++)
+ sc->bfe_tx_ring[i].bfe_mbuf = NULL;
+
+ bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+}
+
+static void
+bfe_discard_buf(struct bfe_softc *sc, int c)
+{
+ struct bfe_rx_data *r;
+ struct bfe_desc *d;
+
+ r = &sc->bfe_rx_ring[c];
+ d = &sc->bfe_rx_list[c];
+ d->bfe_ctrl = htole32(r->bfe_ctrl);
+}
+
+static int
+bfe_list_newbuf(struct bfe_softc *sc, int c)
+{
+ struct bfe_rxheader *rx_header;
+ struct bfe_desc *d;
+ struct bfe_rx_data *r;
+ struct mbuf *m;
+ bus_dma_segment_t segs[1];
+ bus_dmamap_t map;
+ u_int32_t ctrl;
+ int nsegs;
+
+ m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
+ m->m_len = m->m_pkthdr.len = MCLBYTES;
+
+ if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
+ m, segs, &nsegs, 0) != 0) {
+ m_freem(m);
+ return (ENOBUFS);
+ }
+
+ KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
+ r = &sc->bfe_rx_ring[c];
+ if (r->bfe_mbuf != NULL) {
+ bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
+ BUS_DMASYNC_POSTREAD);
+ bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
+ }
+ map = r->bfe_map;
+ r->bfe_map = sc->bfe_rx_sparemap;
+ sc->bfe_rx_sparemap = map;
+ r->bfe_mbuf = m;
+
+ rx_header = mtod(m, struct bfe_rxheader *);
+ rx_header->len = 0;
+ rx_header->flags = 0;
+ bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
+
+ ctrl = segs[0].ds_len & BFE_DESC_LEN;
+ KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
+ __func__, ctrl));
+ if (c == BFE_RX_LIST_CNT - 1)
+ ctrl |= BFE_DESC_EOT;
+ r->bfe_ctrl = ctrl;
+
+ d = &sc->bfe_rx_list[c];
+ d->bfe_ctrl = htole32(ctrl);
+ /* The chip needs all addresses to be added to BFE_PCI_DMA. */
+ d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
+
+ return (0);
+}
+
+static void
+bfe_get_config(struct bfe_softc *sc)
+{
+ u_int8_t eeprom[128];
+
+ bfe_read_eeprom(sc, eeprom);
+
+ sc->bfe_enaddr[0] = eeprom[79];
+ sc->bfe_enaddr[1] = eeprom[78];
+ sc->bfe_enaddr[2] = eeprom[81];
+ sc->bfe_enaddr[3] = eeprom[80];
+ sc->bfe_enaddr[4] = eeprom[83];
+ sc->bfe_enaddr[5] = eeprom[82];
+
+ sc->bfe_phyaddr = eeprom[90] & 0x1f;
+ sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
+
+ sc->bfe_core_unit = 0;
+ sc->bfe_dma_offset = BFE_PCI_DMA;
+}
+
+static void
+bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
+{
+ u_int32_t bar_orig, pci_rev, val;
+
+ bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
+ pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
+ pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
+
+ val = CSR_READ_4(sc, BFE_SBINTVEC);
+ val |= cores;
+ CSR_WRITE_4(sc, BFE_SBINTVEC, val);
+
+ val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
+ val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
+ CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
+
+ pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
+}
+
+static void
+bfe_clear_stats(struct bfe_softc *sc)
+{
+ uint32_t reg;
+
+ BFE_LOCK_ASSERT(sc);
+
+ CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
+ for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
+ CSR_READ_4(sc, reg);
+ for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
+ CSR_READ_4(sc, reg);
+}
+
+static int
+bfe_resetphy(struct bfe_softc *sc)
+{
+ u_int32_t val;
+
+ bfe_writephy(sc, 0, BMCR_RESET);
+ DELAY(100);
+ bfe_readphy(sc, 0, &val);
+ if (val & BMCR_RESET) {
+ device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
+ return (ENXIO);
+ }
+ return (0);
+}
+
+static void
+bfe_chip_halt(struct bfe_softc *sc)
+{
+ BFE_LOCK_ASSERT(sc);
+ /* disable interrupts - not that it actually does..*/
+ CSR_WRITE_4(sc, BFE_IMASK, 0);
+ CSR_READ_4(sc, BFE_IMASK);
+
+ CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
+ bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
+
+ CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
+ CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
+ DELAY(10);
+}
+
+static void
+bfe_chip_reset(struct bfe_softc *sc)
+{
+ u_int32_t val;
+
+ BFE_LOCK_ASSERT(sc);
+
+ /* Set the interrupt vector for the enet core */
+ bfe_pci_setup(sc, BFE_INTVEC_ENET0);
+
+ /* is core up? */
+ val = CSR_READ_4(sc, BFE_SBTMSLOW) &
+ (BFE_RESET | BFE_REJECT | BFE_CLOCK);
+ if (val == BFE_CLOCK) {
+ /* It is, so shut it down */
+ CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
+ CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
+ bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
+ CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
+ if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
+ bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
+ 100, 0);
+ CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
+ }
+
+ bfe_core_reset(sc);
+ bfe_clear_stats(sc);
+
+ /*
+ * We want the phy registers to be accessible even when
+ * the driver is "downed" so initialize MDC preamble, frequency,
+ * and whether internal or external phy here.
+ */
+
+ /* 4402 has 62.5Mhz SB clock and internal phy */
+ CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
+
+ /* Internal or external PHY? */
+ val = CSR_READ_4(sc, BFE_DEVCTRL);
+ if (!(val & BFE_IPP))
+ CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
+ else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
+ BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
+ DELAY(100);
+ }
+
+ /* Enable CRC32 generation and set proper LED modes */
+ BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
+
+ /* Reset or clear powerdown control bit */
+ BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
+
+ CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
+ BFE_LAZY_FC_MASK));
+
+ /*
+ * We don't want lazy interrupts, so just send them at
+ * the end of a frame, please
+ */
+ BFE_OR(sc, BFE_RCV_LAZY, 0);
+
+ /* Set max lengths, accounting for VLAN tags */
+ CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
+ CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
+
+ /* Set watermark XXX - magic */
+ CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
+
+ /*
+ * Initialise DMA channels
+ * - not forgetting dma addresses need to be added to BFE_PCI_DMA
+ */
+ CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
+ CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
+
+ CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
+ BFE_RX_CTRL_ENABLE);
+ CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
+
+ bfe_resetphy(sc);
+ bfe_setupphy(sc);
+}
+
+static void
+bfe_core_disable(struct bfe_softc *sc)
+{
+ if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
+ return;
+
+ /*
+ * Set reject, wait for it set, then wait for the core to stop
+ * being busy, then set reset and reject and enable the clocks.
+ */
+ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
+ bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
+ bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
+ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
+ BFE_RESET));
+ CSR_READ_4(sc, BFE_SBTMSLOW);
+ DELAY(10);
+ /* Leave reset and reject set */
+ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
+ DELAY(10);
+}
+
+static void
+bfe_core_reset(struct bfe_softc *sc)
+{
+ u_int32_t val;
+
+ /* Disable the core */
+ bfe_core_disable(sc);
+
+ /* and bring it back up */
+ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
+ CSR_READ_4(sc, BFE_SBTMSLOW);
+ DELAY(10);
+
+ /* Chip bug, clear SERR, IB and TO if they are set. */
+ if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
+ CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
+ val = CSR_READ_4(sc, BFE_SBIMSTATE);
+ if (val & (BFE_IBE | BFE_TO))
+ CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
+
+ /* Clear reset and allow it to move through the core */
+ CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
+ CSR_READ_4(sc, BFE_SBTMSLOW);
+ DELAY(10);
+
+ /* Leave the clock set */
+ CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
+ CSR_READ_4(sc, BFE_SBTMSLOW);
+ DELAY(10);
+}
+
+static void
+bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
+{
+ u_int32_t val;
+
+ val = ((u_int32_t) data[2]) << 24;
+ val |= ((u_int32_t) data[3]) << 16;
+ val |= ((u_int32_t) data[4]) << 8;
+ val |= ((u_int32_t) data[5]);
+ CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
+ val = (BFE_CAM_HI_VALID |
+ (((u_int32_t) data[0]) << 8) |
+ (((u_int32_t) data[1])));
+ CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
+ CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
+ ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
+ bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
+}
+
+static void
+bfe_set_rx_mode(struct bfe_softc *sc)
+{
+ struct ifnet *ifp = sc->bfe_ifp;
+ struct ifmultiaddr *ifma;
+ u_int32_t val;
+ int i = 0;
+
+ BFE_LOCK_ASSERT(sc);
+
+ val = CSR_READ_4(sc, BFE_RXCONF);
+
+ if (ifp->if_flags & IFF_PROMISC)
+ val |= BFE_RXCONF_PROMISC;
+ else
+ val &= ~BFE_RXCONF_PROMISC;
+
+ if (ifp->if_flags & IFF_BROADCAST)
+ val &= ~BFE_RXCONF_DBCAST;
+ else
+ val |= BFE_RXCONF_DBCAST;
+
+
+ CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
+ bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
+
+ if (ifp->if_flags & IFF_ALLMULTI)
+ val |= BFE_RXCONF_ALLMULTI;
+ else {
+ val &= ~BFE_RXCONF_ALLMULTI;
+ if_maddr_rlock(ifp);
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ bfe_cam_write(sc,
+ LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
+ }
+ if_maddr_runlock(ifp);
+ }
+
+ CSR_WRITE_4(sc, BFE_RXCONF, val);
+ BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
+}
+
+static void
+bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+ struct bfe_dmamap_arg *ctx;
+
+ if (error != 0)
+ return;
+
+ KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
+
+ ctx = (struct bfe_dmamap_arg *)arg;
+ ctx->bfe_busaddr = segs[0].ds_addr;
+}
+
+static void
+bfe_release_resources(struct bfe_softc *sc)
+{
+
+ if (sc->bfe_intrhand != NULL)
+ bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
+
+ if (sc->bfe_irq != NULL)
+ bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
+
+ if (sc->bfe_res != NULL)
+ bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
+ sc->bfe_res);
+
+ if (sc->bfe_ifp != NULL)
+ if_free(sc->bfe_ifp);
+}
+
+static void
+bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
+{
+ long i;
+ u_int16_t *ptr = (u_int16_t *)data;
+
+ for(i = 0; i < 128; i += 2)
+ ptr[i/2] = CSR_READ_4(sc, 4096 + i);
+}
+
+static int
+bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
+ u_long timeout, const int clear)
+{
+ u_long i;
+
+ for (i = 0; i < timeout; i++) {
+ u_int32_t val = CSR_READ_4(sc, reg);
+
+ if (clear && !(val & bit))
+ break;
+ if (!clear && (val & bit))
+ break;
+ DELAY(10);
+ }
+ if (i == timeout) {
+ device_printf(sc->bfe_dev,
+ "BUG! Timeout waiting for bit %08x of register "
+ "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
+ return (-1);
+ }
+ return (0);
+}
+
+static int
+bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
+{
+ int err;
+
+ /* Clear MII ISR */
+ CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
+ CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
+ (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
+ (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
+ (reg << BFE_MDIO_RA_SHIFT) |
+ (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
+ err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
+ *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
+
+ return (err);
+}
+
+static int
+bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
+{
+ int status;
+
+ CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
+ CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
+ (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
+ (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
+ (reg << BFE_MDIO_RA_SHIFT) |
+ (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
+ (val & BFE_MDIO_DATA_DATA)));
+ status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
+
+ return (status);
+}
+
+/*
+ * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
+ * twice
+ */
+static int
+bfe_setupphy(struct bfe_softc *sc)
+{
+ u_int32_t val;
+
+ /* Enable activity LED */
+ bfe_readphy(sc, 26, &val);
+ bfe_writephy(sc, 26, val & 0x7fff);
+ bfe_readphy(sc, 26, &val);
+
+ /* Enable traffic meter LED mode */
+ bfe_readphy(sc, 27, &val);
+ bfe_writephy(sc, 27, val | (1 << 6));
+
+ return (0);
+}
+
+static void
+bfe_stats_update(struct bfe_softc *sc)
+{
+ struct bfe_hw_stats *stats;
+ struct ifnet *ifp;
+ uint32_t mib[BFE_MIB_CNT];
+ uint32_t reg, *val;
+
+ BFE_LOCK_ASSERT(sc);
+
+ val = mib;
+ CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
+ for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
+ *val++ = CSR_READ_4(sc, reg);
+ for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
+ *val++ = CSR_READ_4(sc, reg);
+
+ ifp = sc->bfe_ifp;
+ stats = &sc->bfe_stats;
+ /* Tx stat. */
+ stats->tx_good_octets += mib[MIB_TX_GOOD_O];
+ stats->tx_good_frames += mib[MIB_TX_GOOD_P];
+ stats->tx_octets += mib[MIB_TX_O];
+ stats->tx_frames += mib[MIB_TX_P];
+ stats->tx_bcast_frames += mib[MIB_TX_BCAST];
+ stats->tx_mcast_frames += mib[MIB_TX_MCAST];
+ stats->tx_pkts_64 += mib[MIB_TX_64];
+ stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
+ stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
+ stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
+ stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
+ stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
+ stats->tx_jabbers += mib[MIB_TX_JABBER];
+ stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
+ stats->tx_frag_frames += mib[MIB_TX_FRAG];
+ stats->tx_underruns += mib[MIB_TX_URUNS];
+ stats->tx_colls += mib[MIB_TX_TCOLS];
+ stats->tx_single_colls += mib[MIB_TX_SCOLS];
+ stats->tx_multi_colls += mib[MIB_TX_MCOLS];
+ stats->tx_excess_colls += mib[MIB_TX_ECOLS];
+ stats->tx_late_colls += mib[MIB_TX_LCOLS];
+ stats->tx_deferrals += mib[MIB_TX_DEFERED];
+ stats->tx_carrier_losts += mib[MIB_TX_CLOST];
+ stats->tx_pause_frames += mib[MIB_TX_PAUSE];
+ /* Rx stat. */
+ stats->rx_good_octets += mib[MIB_RX_GOOD_O];
+ stats->rx_good_frames += mib[MIB_RX_GOOD_P];
+ stats->rx_octets += mib[MIB_RX_O];
+ stats->rx_frames += mib[MIB_RX_P];
+ stats->rx_bcast_frames += mib[MIB_RX_BCAST];
+ stats->rx_mcast_frames += mib[MIB_RX_MCAST];
+ stats->rx_pkts_64 += mib[MIB_RX_64];
+ stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
+ stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
+ stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
+ stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
+ stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
+ stats->rx_jabbers += mib[MIB_RX_JABBER];
+ stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
+ stats->rx_frag_frames += mib[MIB_RX_FRAG];
+ stats->rx_missed_frames += mib[MIB_RX_MISS];
+ stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
+ stats->rx_runts += mib[MIB_RX_USIZE];
+ stats->rx_crc_errs += mib[MIB_RX_CRC];
+ stats->rx_align_errs += mib[MIB_RX_ALIGN];
+ stats->rx_symbol_errs += mib[MIB_RX_SYM];
+ stats->rx_pause_frames += mib[MIB_RX_PAUSE];
+ stats->rx_control_frames += mib[MIB_RX_NPAUSE];
+
+ /* Update counters in ifnet. */
+ ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P];
+ ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS];
+ ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] +
+ (u_long)mib[MIB_TX_ECOLS] +
+ (u_long)mib[MIB_TX_DEFERED] +
+ (u_long)mib[MIB_TX_CLOST];
+
+ ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P];
+
+ ifp->if_ierrors += mib[MIB_RX_JABBER] +
+ mib[MIB_RX_MISS] +
+ mib[MIB_RX_CRCA] +
+ mib[MIB_RX_USIZE] +
+ mib[MIB_RX_CRC] +
+ mib[MIB_RX_ALIGN] +
+ mib[MIB_RX_SYM];
+}
+
+static void
+bfe_txeof(struct bfe_softc *sc)
+{
+ struct bfe_tx_data *r;
+ struct ifnet *ifp;
+ int i, chipidx;
+
+ BFE_LOCK_ASSERT(sc);
+
+ ifp = sc->bfe_ifp;
+
+ chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
+ chipidx /= sizeof(struct bfe_desc);
+
+ i = sc->bfe_tx_cons;
+ if (i == chipidx)
+ return;
+ bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+ /* Go through the mbufs and free those that have been transmitted */
+ for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
+ r = &sc->bfe_tx_ring[i];
+ sc->bfe_tx_cnt--;
+ if (r->bfe_mbuf == NULL)
+ continue;
+ bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
+ BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
+
+ m_freem(r->bfe_mbuf);
+ r->bfe_mbuf = NULL;
+ }
+
+ if (i != sc->bfe_tx_cons) {
+ /* we freed up some mbufs */
+ sc->bfe_tx_cons = i;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+ }
+
+ if (sc->bfe_tx_cnt == 0)
+ sc->bfe_watchdog_timer = 0;
+}
+
+/* Pass a received packet up the stack */
+static void
+bfe_rxeof(struct bfe_softc *sc)
+{
+ struct mbuf *m;
+ struct ifnet *ifp;
+ struct bfe_rxheader *rxheader;
+ struct bfe_rx_data *r;
+ int cons, prog;
+ u_int32_t status, current, len, flags;
+
+ BFE_LOCK_ASSERT(sc);
+ cons = sc->bfe_rx_cons;
+ status = CSR_READ_4(sc, BFE_DMARX_STAT);
+ current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
+
+ ifp = sc->bfe_ifp;
+
+ bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+ for (prog = 0; current != cons; prog++,
+ BFE_INC(cons, BFE_RX_LIST_CNT)) {
+ r = &sc->bfe_rx_ring[cons];
+ m = r->bfe_mbuf;
+ /*
+ * Rx status should be read from mbuf such that we can't
+ * delay bus_dmamap_sync(9). This hardware limiation
+ * results in inefficent mbuf usage as bfe(4) couldn't
+ * reuse mapped buffer from errored frame.
+ */
+ if (bfe_list_newbuf(sc, cons) != 0) {
+ ifp->if_iqdrops++;
+ bfe_discard_buf(sc, cons);
+ continue;
+ }
+ rxheader = mtod(m, struct bfe_rxheader*);
+ len = le16toh(rxheader->len);
+ flags = le16toh(rxheader->flags);
+
+ /* Remove CRC bytes. */
+ len -= ETHER_CRC_LEN;
+
+ /* flag an error and try again */
+ if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
+ m_freem(m);
+ continue;
+ }
+
+ /* Make sure to skip header bytes written by hardware. */
+ m_adj(m, BFE_RX_OFFSET);
+ m->m_len = m->m_pkthdr.len = len;
+
+ m->m_pkthdr.rcvif = ifp;
+ BFE_UNLOCK(sc);
+ (*ifp->if_input)(ifp, m);
+ BFE_LOCK(sc);
+ }
+
+ if (prog > 0) {
+ sc->bfe_rx_cons = cons;
+ bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+ }
+}
+
+static void
+bfe_intr(void *xsc)
+{
+ struct bfe_softc *sc = xsc;
+ struct ifnet *ifp;
+ u_int32_t istat;
+
+ ifp = sc->bfe_ifp;
+
+ BFE_LOCK(sc);
+
+ istat = CSR_READ_4(sc, BFE_ISTAT);
+
+ /*
+ * Defer unsolicited interrupts - This is necessary because setting the
+ * chips interrupt mask register to 0 doesn't actually stop the
+ * interrupts
+ */
+ istat &= BFE_IMASK_DEF;
+ CSR_WRITE_4(sc, BFE_ISTAT, istat);
+ CSR_READ_4(sc, BFE_ISTAT);
+
+ /* not expecting this interrupt, disregard it */
+ if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+ BFE_UNLOCK(sc);
+ return;
+ }
+
+ /* A packet was received */
+ if (istat & BFE_ISTAT_RX)
+ bfe_rxeof(sc);
+
+ /* A packet was sent */
+ if (istat & BFE_ISTAT_TX)
+ bfe_txeof(sc);
+
+ if (istat & BFE_ISTAT_ERRORS) {
+
+ if (istat & BFE_ISTAT_DSCE) {
+ device_printf(sc->bfe_dev, "Descriptor Error\n");
+ bfe_stop(sc);
+ BFE_UNLOCK(sc);
+ return;
+ }
+
+ if (istat & BFE_ISTAT_DPE) {
+ device_printf(sc->bfe_dev,
+ "Descriptor Protocol Error\n");
+ bfe_stop(sc);
+ BFE_UNLOCK(sc);
+ return;
+ }
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ bfe_init_locked(sc);
+ }
+
+ /* We have packets pending, fire them out */
+ if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ bfe_start_locked(ifp);
+
+ BFE_UNLOCK(sc);
+}
+
+static int
+bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
+{
+ struct bfe_desc *d;
+ struct bfe_tx_data *r, *r1;
+ struct mbuf *m;
+ bus_dmamap_t map;
+ bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
+ uint32_t cur, si;
+ int error, i, nsegs;
+
+ BFE_LOCK_ASSERT(sc);
+
+ M_ASSERTPKTHDR((*m_head));
+
+ si = cur = sc->bfe_tx_prod;
+ r = &sc->bfe_tx_ring[cur];
+ error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
+ txsegs, &nsegs, 0);
+ if (error == EFBIG) {
+ m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS);
+ if (m == NULL) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (ENOMEM);
+ }
+ *m_head = m;
+ error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
+ *m_head, txsegs, &nsegs, 0);
+ if (error != 0) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (error);
+ }
+ } else if (error != 0)
+ return (error);
+ if (nsegs == 0) {
+ m_freem(*m_head);
+ *m_head = NULL;
+ return (EIO);
+ }
+
+ if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
+ bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
+ return (ENOBUFS);
+ }
+
+ for (i = 0; i < nsegs; i++) {
+ d = &sc->bfe_tx_list[cur];
+ d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
+ d->bfe_ctrl |= htole32(BFE_DESC_IOC);
+ if (cur == BFE_TX_LIST_CNT - 1)
+ /*
+ * Tell the chip to wrap to the start of
+ * the descriptor list.
+ */
+ d->bfe_ctrl |= htole32(BFE_DESC_EOT);
+ /* The chip needs all addresses to be added to BFE_PCI_DMA. */
+ d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
+ BFE_PCI_DMA);
+ BFE_INC(cur, BFE_TX_LIST_CNT);
+ }
+
+ /* Update producer index. */
+ sc->bfe_tx_prod = cur;
+
+ /* Set EOF on the last descriptor. */
+ cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
+ d = &sc->bfe_tx_list[cur];
+ d->bfe_ctrl |= htole32(BFE_DESC_EOF);
+
+ /* Lastly set SOF on the first descriptor to avoid races. */
+ d = &sc->bfe_tx_list[si];
+ d->bfe_ctrl |= htole32(BFE_DESC_SOF);
+
+ r1 = &sc->bfe_tx_ring[cur];
+ map = r->bfe_map;
+ r->bfe_map = r1->bfe_map;
+ r1->bfe_map = map;
+ r1->bfe_mbuf = *m_head;
+ sc->bfe_tx_cnt += nsegs;
+
+ bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
+
+ return (0);
+}
+
+/*
+ * Set up to transmit a packet.
+ */
+static void
+bfe_start(struct ifnet *ifp)
+{
+ BFE_LOCK((struct bfe_softc *)ifp->if_softc);
+ bfe_start_locked(ifp);
+ BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
+}
+
+/*
+ * Set up to transmit a packet. The softc is already locked.
+ */
+static void
+bfe_start_locked(struct ifnet *ifp)
+{
+ struct bfe_softc *sc;
+ struct mbuf *m_head;
+ int queued;
+
+ sc = ifp->if_softc;
+
+ BFE_LOCK_ASSERT(sc);
+
+ /*
+ * Not much point trying to send if the link is down
+ * or we have nothing to send.
+ */
+ if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+ IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
+ return;
+
+ for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
+ sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
+ IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+ if (m_head == NULL)
+ break;
+
+ /*
+ * Pack the data into the tx ring. If we dont have
+ * enough room, let the chip drain the ring.
+ */
+ if (bfe_encap(sc, &m_head)) {
+ if (m_head == NULL)
+ break;
+ IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+ ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+ break;
+ }
+
+ queued++;
+
+ /*
+ * If there's a BPF listener, bounce a copy of this frame
+ * to him.
+ */
+ BPF_MTAP(ifp, m_head);
+ }
+
+ if (queued) {
+ bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+ /* Transmit - twice due to apparent hardware bug */
+ CSR_WRITE_4(sc, BFE_DMATX_PTR,
+ sc->bfe_tx_prod * sizeof(struct bfe_desc));
+ /*
+ * XXX It seems the following write is not necessary
+ * to kick Tx command. What might be required would be
+ * a way flushing PCI posted write. Reading the register
+ * back ensures the flush operation. In addition,
+ * hardware will execute PCI posted write in the long
+ * run and watchdog timer for the kick command was set
+ * to 5 seconds. Therefore I think the second write
+ * access is not necessary or could be replaced with
+ * read operation.
+ */
+ CSR_WRITE_4(sc, BFE_DMATX_PTR,
+ sc->bfe_tx_prod * sizeof(struct bfe_desc));
+
+ /*
+ * Set a timeout in case the chip goes out to lunch.
+ */
+ sc->bfe_watchdog_timer = 5;
+ }
+}
+
+static void
+bfe_init(void *xsc)
+{
+ BFE_LOCK((struct bfe_softc *)xsc);
+ bfe_init_locked(xsc);
+ BFE_UNLOCK((struct bfe_softc *)xsc);
+}
+
+static void
+bfe_init_locked(void *xsc)
+{
+ struct bfe_softc *sc = (struct bfe_softc*)xsc;
+ struct ifnet *ifp = sc->bfe_ifp;
+ struct mii_data *mii;
+
+ BFE_LOCK_ASSERT(sc);
+
+ mii = device_get_softc(sc->bfe_miibus);
+
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ return;
+
+ bfe_stop(sc);
+ bfe_chip_reset(sc);
+
+ if (bfe_list_rx_init(sc) == ENOBUFS) {
+ device_printf(sc->bfe_dev,
+ "%s: Not enough memory for list buffers\n", __func__);
+ bfe_stop(sc);
+ return;
+ }
+ bfe_list_tx_init(sc);
+
+ bfe_set_rx_mode(sc);
+
+ /* Enable the chip and core */
+ BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
+ /* Enable interrupts */
+ CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
+
+ /* Clear link state and change media. */
+ sc->bfe_flags &= ~BFE_FLAG_LINK;
+ mii_mediachg(mii);
+
+ ifp->if_drv_flags |= IFF_DRV_RUNNING;
+ ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+ callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
+}
+
+/*
+ * Set media options.
+ */
+static int
+bfe_ifmedia_upd(struct ifnet *ifp)
+{
+ struct bfe_softc *sc;
+ struct mii_data *mii;
+ int error;
+
+ sc = ifp->if_softc;
+ BFE_LOCK(sc);
+
+ mii = device_get_softc(sc->bfe_miibus);
+ if (mii->mii_instance) {
+ struct mii_softc *miisc;
+ for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
+ miisc = LIST_NEXT(miisc, mii_list))
+ mii_phy_reset(miisc);
+ }
+ error = mii_mediachg(mii);
+ BFE_UNLOCK(sc);
+
+ return (error);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+ struct bfe_softc *sc = ifp->if_softc;
+ struct mii_data *mii;
+
+ BFE_LOCK(sc);
+ mii = device_get_softc(sc->bfe_miibus);
+ mii_pollstat(mii);
+ ifmr->ifm_active = mii->mii_media_active;
+ ifmr->ifm_status = mii->mii_media_status;
+ BFE_UNLOCK(sc);
+}
+
+static int
+bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+ struct bfe_softc *sc = ifp->if_softc;
+ struct ifreq *ifr = (struct ifreq *) data;
+ struct mii_data *mii;
+ int error = 0;
+
+ switch (command) {
+ case SIOCSIFFLAGS:
+ BFE_LOCK(sc);
+ if (ifp->if_flags & IFF_UP) {
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ bfe_set_rx_mode(sc);
+ else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
+ bfe_init_locked(sc);
+ } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ bfe_stop(sc);
+ BFE_UNLOCK(sc);
+ break;
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ BFE_LOCK(sc);
+ if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+ bfe_set_rx_mode(sc);
+ BFE_UNLOCK(sc);
+ break;
+ case SIOCGIFMEDIA:
+ case SIOCSIFMEDIA:
+ mii = device_get_softc(sc->bfe_miibus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+ break;
+ default:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ }
+
+ return (error);
+}
+
+static void
+bfe_watchdog(struct bfe_softc *sc)
+{
+ struct ifnet *ifp;
+
+ BFE_LOCK_ASSERT(sc);
+
+ if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
+ return;
+
+ ifp = sc->bfe_ifp;
+
+ device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
+
+ ifp->if_oerrors++;
+ ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+ bfe_init_locked(sc);
+
+ if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+ bfe_start_locked(ifp);
+}
+
+static void
+bfe_tick(void *xsc)
+{
+ struct bfe_softc *sc = xsc;
+ struct mii_data *mii;
+
+ BFE_LOCK_ASSERT(sc);
+
+ mii = device_get_softc(sc->bfe_miibus);
+ mii_tick(mii);
+ bfe_stats_update(sc);
+ bfe_watchdog(sc);
+ callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void
+bfe_stop(struct bfe_softc *sc)
+{
+ struct ifnet *ifp;
+
+ BFE_LOCK_ASSERT(sc);
+
+ ifp = sc->bfe_ifp;
+ ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+ sc->bfe_flags &= ~BFE_FLAG_LINK;
+ callout_stop(&sc->bfe_stat_co);
+ sc->bfe_watchdog_timer = 0;
+
+ bfe_chip_halt(sc);
+ bfe_tx_ring_free(sc);
+ bfe_rx_ring_free(sc);
+}
+
+static int
+sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
+{
+ struct bfe_softc *sc;
+ struct bfe_hw_stats *stats;
+ int error, result;
+
+ result = -1;
+ error = sysctl_handle_int(oidp, &result, 0, req);
+
+ if (error != 0 || req->newptr == NULL)
+ return (error);
+
+ if (result != 1)
+ return (error);
+
+ sc = (struct bfe_softc *)arg1;
+ stats = &sc->bfe_stats;
+
+ printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
+ printf("Transmit good octets : %ju\n",
+ (uintmax_t)stats->tx_good_octets);
+ printf("Transmit good frames : %ju\n",
+ (uintmax_t)stats->tx_good_frames);
+ printf("Transmit octets : %ju\n",
+ (uintmax_t)stats->tx_octets);
+ printf("Transmit frames : %ju\n",
+ (uintmax_t)stats->tx_frames);
+ printf("Transmit broadcast frames : %ju\n",
+ (uintmax_t)stats->tx_bcast_frames);
+ printf("Transmit multicast frames : %ju\n",
+ (uintmax_t)stats->tx_mcast_frames);
+ printf("Transmit frames 64 bytes : %ju\n",
+ (uint64_t)stats->tx_pkts_64);
+ printf("Transmit frames 65 to 127 bytes : %ju\n",
+ (uint64_t)stats->tx_pkts_65_127);
+ printf("Transmit frames 128 to 255 bytes : %ju\n",
+ (uint64_t)stats->tx_pkts_128_255);
+ printf("Transmit frames 256 to 511 bytes : %ju\n",
+ (uint64_t)stats->tx_pkts_256_511);
+ printf("Transmit frames 512 to 1023 bytes : %ju\n",
+ (uint64_t)stats->tx_pkts_512_1023);
+ printf("Transmit frames 1024 to max bytes : %ju\n",
+ (uint64_t)stats->tx_pkts_1024_max);
+ printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
+ printf("Transmit oversized frames : %ju\n",
+ (uint64_t)stats->tx_oversize_frames);
+ printf("Transmit fragmented frames : %ju\n",
+ (uint64_t)stats->tx_frag_frames);
+ printf("Transmit underruns : %u\n", stats->tx_colls);
+ printf("Transmit total collisions : %u\n", stats->tx_single_colls);
+ printf("Transmit single collisions : %u\n", stats->tx_single_colls);
+ printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
+ printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
+ printf("Transmit late collisions : %u\n", stats->tx_late_colls);
+ printf("Transmit deferrals : %u\n", stats->tx_deferrals);
+ printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
+ printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
+
+ printf("Receive good octets : %ju\n",
+ (uintmax_t)stats->rx_good_octets);
+ printf("Receive good frames : %ju\n",
+ (uintmax_t)stats->rx_good_frames);
+ printf("Receive octets : %ju\n",
+ (uintmax_t)stats->rx_octets);
+ printf("Receive frames : %ju\n",
+ (uintmax_t)stats->rx_frames);
+ printf("Receive broadcast frames : %ju\n",
+ (uintmax_t)stats->rx_bcast_frames);
+ printf("Receive multicast frames : %ju\n",
+ (uintmax_t)stats->rx_mcast_frames);
+ printf("Receive frames 64 bytes : %ju\n",
+ (uint64_t)stats->rx_pkts_64);
+ printf("Receive frames 65 to 127 bytes : %ju\n",
+ (uint64_t)stats->rx_pkts_65_127);
+ printf("Receive frames 128 to 255 bytes : %ju\n",
+ (uint64_t)stats->rx_pkts_128_255);
+ printf("Receive frames 256 to 511 bytes : %ju\n",
+ (uint64_t)stats->rx_pkts_256_511);
+ printf("Receive frames 512 to 1023 bytes : %ju\n",
+ (uint64_t)stats->rx_pkts_512_1023);
+ printf("Receive frames 1024 to max bytes : %ju\n",
+ (uint64_t)stats->rx_pkts_1024_max);
+ printf("Receive jabber errors : %u\n", stats->rx_jabbers);
+ printf("Receive oversized frames : %ju\n",
+ (uint64_t)stats->rx_oversize_frames);
+ printf("Receive fragmented frames : %ju\n",
+ (uint64_t)stats->rx_frag_frames);
+ printf("Receive missed frames : %u\n", stats->rx_missed_frames);
+ printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
+ printf("Receive undersized frames : %u\n", stats->rx_runts);
+ printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
+ printf("Receive align errors : %u\n", stats->rx_align_errs);
+ printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
+ printf("Receive pause frames : %u\n", stats->rx_pause_frames);
+ printf("Receive control frames : %u\n", stats->rx_control_frames);
+
+ return (error);
+}
diff --git a/freebsd/sys/dev/bfe/if_bfereg.h b/freebsd/sys/dev/bfe/if_bfereg.h
new file mode 100644
index 00000000..b50627ed
--- /dev/null
+++ b/freebsd/sys/dev/bfe/if_bfereg.h
@@ -0,0 +1,626 @@
+/*-
+ * Copyright (c) 2003 Stuart Walsh
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+/* $FreeBSD$ */
+
+#ifndef _BFE_H
+#define _BFE_H
+
+/* PCI registers */
+#define BFE_PCI_MEMLO 0x10
+#define BFE_PCI_MEMHIGH 0x14
+#define BFE_PCI_INTLINE 0x3C
+
+/* Register layout. */
+#define BFE_DEVCTRL 0x00000000 /* Device Control */
+#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
+#define BFE_IPP 0x00000400 /* Internal EPHY Present */
+#define BFE_EPR 0x00008000 /* EPHY Reset */
+#define BFE_PME 0x00001000 /* PHY Mode Enable */
+#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
+#define BFE_PADDR 0x0007c000 /* PHY Address */
+#define BFE_PADDR_SHIFT 18
+
+#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
+#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */
+
+#define BFE_ISTAT 0x00000020 /* Interrupt Status */
+#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */
+#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */
+#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */
+#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */
+#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
+#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
+#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
+#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
+#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
+#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */
+#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
+#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
+#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
+#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\
+ BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
+
+#define BFE_IMASK 0x00000024 /* Interrupt Mask */
+#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \
+ BFE_ISTAT_TX)
+
+#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */
+#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
+#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
+#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */
+#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */
+#define BFE_CTRL_LED_SHIFT 5
+
+#define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */
+#define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */
+#define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
+
+#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */
+#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */
+#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */
+#define BFE_LAZY_FC_SHIFT 24
+
+#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */
+#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
+#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
+#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
+#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */
+#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */
+
+#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */
+#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */
+#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */
+#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
+#define BFE_STAT_SMASK 0x0000f000 /* State Mask */
+#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */
+#define BFE_STAT_SACTIVE 0x00001000 /* State Active */
+#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */
+#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */
+#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */
+#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */
+#define BFE_STAT_ENONE 0x00000000 /* Error None */
+#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
+#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
+#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */
+#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
+#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */
+
+#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
+#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */
+#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
+#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
+
+#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
+#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
+#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
+
+#define BFE_RXCONF 0x00000400 /* EMAC RX Config */
+#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */
+#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */
+#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */
+#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */
+#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */
+#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */
+#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
+#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */
+
+#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
+#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */
+
+#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */
+#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */
+#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */
+
+#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */
+#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */
+#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */
+#define BFE_MDIO_TA_SHIFT 16
+#define BFE_MDIO_TA_VALID 2
+
+#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */
+#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */
+#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */
+#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */
+#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */
+#define BFE_MDIO_RA_SHIFT 18
+#define BFE_MDIO_PMD_SHIFT 23
+#define BFE_MDIO_OP_SHIFT 28
+#define BFE_MDIO_OP_WRITE 1
+#define BFE_MDIO_OP_READ 2
+#define BFE_MDIO_SB_SHIFT 30
+
+#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */
+#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */
+#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
+#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
+#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
+
+#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */
+#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */
+#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */
+
+#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */
+#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */
+#define BFE_CAM_MSEL 0x00000002 /* Mask Select */
+#define BFE_CAM_READ 0x00000004 /* Read */
+#define BFE_CAM_WRITE 0x00000008 /* Read */
+#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */
+#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */
+#define BFE_CAM_INDEX_SHIFT 16
+
+#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */
+#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */
+#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */
+#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */
+#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */
+
+#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */
+#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */
+#define BFE_TX_FMODE 0x00000002 /* Flow Mode */
+#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */
+#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */
+
+#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */
+
+#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
+#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */
+
+/* Status registers */
+#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
+#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
+#define BFE_TX_O 0x00000508 /* MIB TX Octets */
+#define BFE_TX_P 0x0000050C /* MIB TX Packets */
+#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
+#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
+#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
+#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
+#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */
+#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */
+#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */
+#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */
+#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */
+#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */
+#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */
+#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */
+#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */
+#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */
+#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */
+#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */
+#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */
+#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */
+#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */
+#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */
+#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
+#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
+#define BFE_RX_O 0x00000588 /* MIB RX Octets */
+#define BFE_RX_P 0x0000058C /* MIB RX Packets */
+#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */
+#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */
+#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */
+#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */
+#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */
+#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */
+#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */
+#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */
+#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */
+#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */
+#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */
+#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */
+#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */
+#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */
+#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */
+#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */
+#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */
+#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */
+#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
+
+#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */
+#define BFE_PC 0x0000000f /* Pipe Count */
+#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */
+#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */
+#define BFE_AP_TS 0x00000010 /* Use timeslices only */
+#define BFE_AP_TK 0x00000020 /* Use token only */
+#define BFE_AP_RSV 0x00000030 /* Reserved */
+#define BFE_IBE 0x00020000 /* In Band Error */
+#define BFE_TO 0x00040000 /* Timeout */
+
+
+/* Seems the bcm440x has a fairly generic core, we only need be concerned with
+ * a couple of these
+ */
+#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */
+#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
+#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
+#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
+#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
+#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
+#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
+#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
+
+#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */
+#define BFE_RESET 0x00000001 /* Reset */
+#define BFE_REJECT 0x00000002 /* Reject */
+#define BFE_CLOCK 0x00010000 /* Clock Enable */
+#define BFE_FGC 0x00020000 /* Force Gated Clocks On */
+#define BFE_PE 0x40000000 /* Power Management Enable */
+#define BFE_BE 0x80000000 /* BIST Enable */
+
+#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */
+#define BFE_SERR 0x00000001 /* S-error */
+#define BFE_INT 0x00000002 /* Interrupt */
+#define BFE_BUSY 0x00000004 /* Busy */
+#define BFE_GCR 0x20000000 /* Gated Clock Request */
+#define BFE_BISTF 0x40000000 /* BIST Failed */
+#define BFE_BISTD 0x80000000 /* BIST Done */
+
+#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */
+#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */
+#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */
+#define BFE_TAB0_SHIFT 0
+#define BFE_TAB1_SHIFT 16
+
+#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */
+#define BFE_STO_MASK 0x00000003 /* Service Timeout */
+#define BFE_RTO_MASK 0x00000030 /* Request Timeout */
+#define BFE_CID_MASK 0x00ff0000 /* Connection ID */
+#define BFE_RTO_SHIFT 4
+#define BFE_CID_SHIFT 16
+
+#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */
+#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */
+#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */
+#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */
+#define BFE_TEM_SHIFT 4
+#define BFE_BEM_SHIFT 6
+
+#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */
+#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */
+#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */
+#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */
+#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
+#define BFE_LOW_CO_SHIFT 11
+#define BFE_LOW_IF_SHIFT 18
+#define BFE_LOW_IM_SHIFT 24
+
+#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */
+#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */
+#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */
+#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */
+#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */
+#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */
+#define BFE_HIGH_RM_SHIFT 2
+#define BFE_HIGH_SM_SHIFT 4
+#define BFE_HIGH_EM_SHIFT 8
+#define BFE_HIGH_IM_SHIFT 10
+
+#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */
+#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */
+#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */
+#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */
+#define BFE_MAX0_SHIFT 16
+#define BFE_MAX1_SHIFT 20
+
+#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */
+#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */
+#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */
+
+#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */
+#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */
+
+#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */
+#define BFE_CS_MASK 0x00000003 /* Config Space Mask */
+#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */
+#define BFE_SYNCH 0x00000040 /* Sync */
+#define BFE_INIT 0x00000080 /* Initiator */
+#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */
+#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */
+#define BFE_FIRST 0x00010000 /* This Initiator is First */
+#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */
+#define BFE_TP_MASK 0x00f00000 /* Target Ports */
+#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */
+#define BFE_AR_SHIFT 3
+#define BFE_MINLAT_SHIFT 8
+#define BFE_MAXLAT_SHIFT 12
+#define BFE_CW_SHIFT 18
+#define BFE_TP_SHIFT 20
+#define BFE_IP_SHIFT 24
+
+#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */
+#define BFE_RC_MASK 0x0000000f /* Revision Code */
+#define BFE_CC_MASK 0x0000fff0 /* Core Code */
+#define BFE_VC_MASK 0xffff0000 /* Vendor Code */
+#define BFE_CC_SHIFT 4
+#define BFE_VC_SHIFT 16
+
+#define BFE_CORE_ILINE20 0x801
+#define BFE_CORE_SDRAM 0x803
+#define BFE_CORE_PCI 0x804
+#define BFE_CORE_MIPS 0x805
+#define BFE_CORE_ENET 0x806
+#define BFE_CORE_CODEC 0x807
+#define BFE_CORE_USB 0x808
+#define BFE_CORE_ILINE100 0x80a
+#define BFE_CORE_EXTIF 0x811
+
+/* SSB PCI config space registers. */
+#define BFE_BAR0_WIN 0x80
+#define BFE_BAR1_WIN 0x84
+#define BFE_SPROM_CONTROL 0x88
+#define BFE_BAR1_CONTROL 0x8c
+
+/* SSB core and hsot control registers. */
+#define BFE_SSB_CONTROL 0x00000000
+#define BFE_SSB_ARBCONTROL 0x00000010
+#define BFE_SSB_ISTAT 0x00000020
+#define BFE_SSB_IMASK 0x00000024
+#define BFE_SSB_MBOX 0x00000028
+#define BFE_SSB_BCAST_ADDR 0x00000050
+#define BFE_SSB_BCAST_DATA 0x00000054
+#define BFE_SSB_PCI_TRANS_0 0x00000100
+#define BFE_SSB_PCI_TRANS_1 0x00000104
+#define BFE_SSB_PCI_TRANS_2 0x00000108
+#define BFE_SSB_SPROM 0x00000800
+
+#define BFE_SSB_PCI_MEM 0x00000000
+#define BFE_SSB_PCI_IO 0x00000001
+#define BFE_SSB_PCI_CFG0 0x00000002
+#define BFE_SSB_PCI_CFG1 0x00000003
+#define BFE_SSB_PCI_PREF 0x00000004
+#define BFE_SSB_PCI_BURST 0x00000008
+#define BFE_SSB_PCI_MASK0 0xfc000000
+#define BFE_SSB_PCI_MASK1 0xfc000000
+#define BFE_SSB_PCI_MASK2 0xc0000000
+
+#define BFE_DESC_LEN 0x00001fff
+#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */
+#define BFE_DESC_EOT 0x10000000 /* End of Table */
+#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */
+#define BFE_DESC_EOF 0x40000000 /* End of Frame */
+#define BFE_DESC_SOF 0x80000000 /* Start of Frame */
+
+#define BFE_RX_CP_THRESHOLD 256
+#define BFE_RX_HEADER_LEN 28
+
+#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
+#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */
+#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
+#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
+#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
+#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
+#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
+#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
+#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
+#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \
+ BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
+
+#define BFE_MCAST_TBL_SIZE 32
+#define BFE_PCI_DMA 0x40000000
+#define BFE_REG_PCI 0x18002000
+
+#define BCOM_VENDORID 0x14E4
+#define BCOM_DEVICEID_BCM4401 0x4401
+#define BCOM_DEVICEID_BCM4401B0 0x170c
+
+#define PCI_SETBIT(dev, reg, x, s) \
+ pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
+#define PCI_CLRBIT(dev, reg, x, s) \
+ pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
+
+#define BFE_TX_LIST_CNT 128
+#define BFE_RX_LIST_CNT 128
+#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc)
+#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc)
+#define BFE_RX_OFFSET 30
+#define BFE_TX_QLEN 256
+
+#define BFE_RX_RING_ALIGN 4096
+#define BFE_TX_RING_ALIGN 4096
+#define BFE_MAXTXSEGS 16
+#define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */
+#define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
+
+#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)
+
+#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)
+
+#define BFE_OR(sc, name, val) \
+ CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
+
+#define BFE_AND(sc, name, val) \
+ CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
+
+#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED)
+#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx)
+#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx)
+
+#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
+
+struct bfe_tx_data {
+ struct mbuf *bfe_mbuf;
+ bus_dmamap_t bfe_map;
+};
+
+struct bfe_rx_data {
+ struct mbuf *bfe_mbuf;
+ bus_dmamap_t bfe_map;
+ u_int32_t bfe_ctrl;
+};
+
+struct bfe_desc {
+ u_int32_t bfe_ctrl;
+ u_int32_t bfe_addr;
+};
+
+struct bfe_rxheader {
+ u_int16_t len;
+ u_int16_t flags;
+ u_int16_t pad[12];
+};
+
+#define MIB_TX_GOOD_O 0
+#define MIB_TX_GOOD_P 1
+#define MIB_TX_O 2
+#define MIB_TX_P 3
+#define MIB_TX_BCAST 4
+#define MIB_TX_MCAST 5
+#define MIB_TX_64 6
+#define MIB_TX_65_127 7
+#define MIB_TX_128_255 8
+#define MIB_TX_256_511 9
+#define MIB_TX_512_1023 10
+#define MIB_TX_1024_MAX 11
+#define MIB_TX_JABBER 12
+#define MIB_TX_OSIZE 13
+#define MIB_TX_FRAG 14
+#define MIB_TX_URUNS 15
+#define MIB_TX_TCOLS 16
+#define MIB_TX_SCOLS 17
+#define MIB_TX_MCOLS 18
+#define MIB_TX_ECOLS 19
+#define MIB_TX_LCOLS 20
+#define MIB_TX_DEFERED 21
+#define MIB_TX_CLOST 22
+#define MIB_TX_PAUSE 23
+#define MIB_RX_GOOD_O 24
+#define MIB_RX_GOOD_P 25
+#define MIB_RX_O 26
+#define MIB_RX_P 27
+#define MIB_RX_BCAST 28
+#define MIB_RX_MCAST 29
+#define MIB_RX_64 30
+#define MIB_RX_65_127 31
+#define MIB_RX_128_255 32
+#define MIB_RX_256_511 33
+#define MIB_RX_512_1023 34
+#define MIB_RX_1024_MAX 35
+#define MIB_RX_JABBER 36
+#define MIB_RX_OSIZE 37
+#define MIB_RX_FRAG 38
+#define MIB_RX_MISS 39
+#define MIB_RX_CRCA 40
+#define MIB_RX_USIZE 41
+#define MIB_RX_CRC 42
+#define MIB_RX_ALIGN 43
+#define MIB_RX_SYM 44
+#define MIB_RX_PAUSE 45
+#define MIB_RX_NPAUSE 46
+
+#define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1)
+
+struct bfe_hw_stats {
+ uint64_t tx_good_octets;
+ uint64_t tx_good_frames;
+ uint64_t tx_octets;
+ uint64_t tx_frames;
+ uint64_t tx_bcast_frames;
+ uint64_t tx_mcast_frames;
+ uint64_t tx_pkts_64;
+ uint64_t tx_pkts_65_127;
+ uint64_t tx_pkts_128_255;
+ uint64_t tx_pkts_256_511;
+ uint64_t tx_pkts_512_1023;
+ uint64_t tx_pkts_1024_max;
+ uint32_t tx_jabbers;
+ uint64_t tx_oversize_frames;
+ uint64_t tx_frag_frames;
+ uint32_t tx_underruns;
+ uint32_t tx_colls;
+ uint32_t tx_single_colls;
+ uint32_t tx_multi_colls;
+ uint32_t tx_excess_colls;
+ uint32_t tx_late_colls;
+ uint32_t tx_deferrals;
+ uint32_t tx_carrier_losts;
+ uint32_t tx_pause_frames;
+
+ uint64_t rx_good_octets;
+ uint64_t rx_good_frames;
+ uint64_t rx_octets;
+ uint64_t rx_frames;
+ uint64_t rx_bcast_frames;
+ uint64_t rx_mcast_frames;
+ uint64_t rx_pkts_64;
+ uint64_t rx_pkts_65_127;
+ uint64_t rx_pkts_128_255;
+ uint64_t rx_pkts_256_511;
+ uint64_t rx_pkts_512_1023;
+ uint64_t rx_pkts_1024_max;
+ uint32_t rx_jabbers;
+ uint64_t rx_oversize_frames;
+ uint64_t rx_frag_frames;
+ uint32_t rx_missed_frames;
+ uint32_t rx_crc_align_errs;
+ uint32_t rx_runts;
+ uint32_t rx_crc_errs;
+ uint32_t rx_align_errs;
+ uint32_t rx_symbol_errs;
+ uint32_t rx_pause_frames;
+ uint32_t rx_control_frames;
+};
+
+struct bfe_softc
+{
+ struct ifnet *bfe_ifp; /* interface info */
+ device_t bfe_dev;
+ device_t bfe_miibus;
+ bus_dma_tag_t bfe_tag;
+ bus_dma_tag_t bfe_parent_tag;
+ bus_dma_tag_t bfe_tx_tag, bfe_rx_tag;
+ bus_dmamap_t bfe_tx_map, bfe_rx_map;
+ bus_dma_tag_t bfe_txmbuf_tag, bfe_rxmbuf_tag;
+ bus_dmamap_t bfe_rx_sparemap;
+ void *bfe_intrhand;
+ struct resource *bfe_irq;
+ struct resource *bfe_res;
+ struct callout bfe_stat_co;
+ struct bfe_hw_stats bfe_stats;
+ struct bfe_desc *bfe_tx_list, *bfe_rx_list;
+ struct bfe_tx_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */
+ struct bfe_rx_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */
+ struct mtx bfe_mtx;
+ u_int32_t bfe_flags;
+#define BFE_FLAG_DETACH 0x4000
+#define BFE_FLAG_LINK 0x8000
+ u_int32_t bfe_imask;
+ u_int32_t bfe_dma_offset;
+ u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod;
+ u_int32_t bfe_rx_prod, bfe_rx_cons;
+ u_int32_t bfe_tx_dma, bfe_rx_dma;
+ int bfe_watchdog_timer;
+ u_int8_t bfe_phyaddr; /* Address of the card's PHY */
+ u_int8_t bfe_mdc_port;
+ u_int8_t bfe_core_unit;
+ u_char bfe_enaddr[6];
+ int bfe_if_flags;
+};
+
+struct bfe_type
+{
+ u_int16_t bfe_vid;
+ u_int16_t bfe_did;
+ char *bfe_name;
+};
+
+#endif /* _BFE_H */
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