rtems-docs - RTEMS Project documentation.

	Commit message (Collapse)	Author	Files	Lines
2023-05-20	Update company name	Sebastian Huber	1	-1/+1
	The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
2023-04-11	docs/user: add docs for riscv/kendrytek210 BSP variant	Alan Cudmore	1	-52/+188
	This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. V3 clarified the multilib variant description, clarified the multilib variant reference platform, and corrected capitalization on SiFive. V4 improves the instructions for running the K210 BSP on the Renode.io simulator. V5 cleaned up the text to be no more than 80 characters per line. V6 applied word wrap to paragraphs and replaced hard coded RTEMS major versions with macros. Closes #4876
2023-04-11	user/bsps/bsps-riscv.rst: Revert v2 of patch	Joel Sherrill	1	-103/+13

2023-04-11	docs/user: add docs for riscv/kendrytek210 BSP variant	Alan Cudmore	1	-13/+103
	This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. Closes #4876
2023-01-12	riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORT	Sebastian Huber	1	-1/+4
	Updates #4779.
2023-01-09	RISC-V: Update docs on running on QEMU and Spike	Hesham Almatary	1	-3/+23

2023-01-09	RISC-V: Remove the RISCV_ENABLE_HTIF_SUPPORT option	Hesham Almatary	1	-5/+1
	Closes #4779
2023-01-09	Docs: RISC-V Update rv64* BSPs to medany and 0x80000000 start address	Hesham Almatary	1	-15/+12
	Closes #4775
2022-11-15	user: Add documentation for NOEL-V BSP	Daniel Cederman	1	-0/+57

2022-10-31	bsp/riscv: Add a section about running on QEMU	Hesham Almatary	1	-1/+16

2022-10-31	bsps/riscv: Remove inaccurate statement about reliance on a boot loader	Hesham Almatary	1	-3/+1
	The BSP is capable of initialising the hardware being the first software that takes control on hardware reset (after the bootrom). For instance, using on QEMU's virt platforms, RTEMS runs as a bios without BBL. Similarily, RTEMS can also be run on harware/FPGA and loaded using GDB; the bootrom (or a GDB script) should just set the a0/a1 registers with the boot HART ID and DTB address respectively.
2022-10-21	user/bsps: Update riscv for PolarFire SoC	Padmarao Begari	1	-1/+125
	Update the riscv documentation for the Microchip PolarFire SoC BSP variant including information about SMP test procedure for the Microchip PolarFire Icicle Kit.
2022-08-03	versions: Update microblaze, powerpc, riscv and x86_64	Chris Johns	1	-1/+2
	Updates #4695
2019-11-29	user: Add frdme310arty BSP varient	Pragnesh Patel	1	-0/+8
	Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Update #3785.
2019-01-22	user: Stub documentation for griscv BSP	Sebastian Huber	1	-0/+6
	Update #3678.
2019-01-11	Simplify SPDX-License-Identifier comment	Sebastian Huber	1	-1/+1

2019-01-11	Use standard format for copyright lines	Sebastian Huber	1	-1/+2

2019-01-09	user: Add TODO entries for all BSP families	Sebastian Huber	1	-2/+2
	Update #3464.
2018-08-02	user: Add RISC-V BSP section	Sebastian Huber	1	-1/+109
	Update #3433.
2018-06-26	user: Add BSP chapter for each architecture	Sebastian Huber	1	-0/+7
	Update #3464.