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* Update company nameSebastian Huber2023-05-201-1/+1
| | | | | The embedded brains GmbH & Co. KG is the legal successor of embedded brains GmbH.
* docs/user: add docs for riscv/kendrytek210 BSP variantAlan Cudmore2023-04-111-52/+188
| | | | | | | | | | | | | | | | | | | | This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. V3 clarified the multilib variant description, clarified the multilib variant reference platform, and corrected capitalization on SiFive. V4 improves the instructions for running the K210 BSP on the Renode.io simulator. V5 cleaned up the text to be no more than 80 characters per line. V6 applied word wrap to paragraphs and replaced hard coded RTEMS major versions with macros. Closes #4876
* user/bsps/bsps-riscv.rst: Revert v2 of patchJoel Sherrill2023-04-111-103/+13
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* docs/user: add docs for riscv/kendrytek210 BSP variantAlan Cudmore2023-04-111-13/+103
| | | | | | | | | | | | This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. Closes #4876
* riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORTSebastian Huber2023-01-121-1/+4
| | | | Updates #4779.
* RISC-V: Update docs on running on QEMU and SpikeHesham Almatary2023-01-091-3/+23
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* RISC-V: Remove the RISCV_ENABLE_HTIF_SUPPORT optionHesham Almatary2023-01-091-5/+1
| | | | Closes #4779
* Docs: RISC-V Update rv64* BSPs to medany and 0x80000000 start addressHesham Almatary2023-01-091-15/+12
| | | | Closes #4775
* user: Add documentation for NOEL-V BSPDaniel Cederman2022-11-151-0/+57
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* bsp/riscv: Add a section about running on QEMUHesham Almatary2022-10-311-1/+16
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* bsps/riscv: Remove inaccurate statement about reliance on a boot loaderHesham Almatary2022-10-311-3/+1
| | | | | | | | | The BSP is capable of initialising the hardware being the first software that takes control on hardware reset (after the bootrom). For instance, using on QEMU's virt platforms, RTEMS runs as a bios without BBL. Similarily, RTEMS can also be run on harware/FPGA and loaded using GDB; the bootrom (or a GDB script) should just set the a0/a1 registers with the boot HART ID and DTB address respectively.
* user/bsps: Update riscv for PolarFire SoCPadmarao Begari2022-10-211-1/+125
| | | | | | Update the riscv documentation for the Microchip PolarFire SoC BSP variant including information about SMP test procedure for the Microchip PolarFire Icicle Kit.
* versions: Update microblaze, powerpc, riscv and x86_64Chris Johns2022-08-031-1/+2
| | | | Updates #4695
* user: Add frdme310arty BSP varientPragnesh Patel2019-11-291-0/+8
| | | | | | Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Update #3785.
* user: Stub documentation for griscv BSPSebastian Huber2019-01-221-0/+6
| | | | Update #3678.
* Simplify SPDX-License-Identifier commentSebastian Huber2019-01-111-1/+1
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* Use standard format for copyright linesSebastian Huber2019-01-111-1/+2
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* user: Add TODO entries for all BSP familiesSebastian Huber2019-01-091-2/+2
| | | | Update #3464.
* user: Add RISC-V BSP sectionSebastian Huber2018-08-021-1/+109
| | | | Update #3433.
* user: Add BSP chapter for each architectureSebastian Huber2018-06-261-0/+7
Update #3464.
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