diff options
Diffstat (limited to 'user/bsps')
30 files changed, 861 insertions, 109 deletions
diff --git a/user/bsps/aarch64/raspberrypi4.rst b/user/bsps/aarch64/raspberrypi4.rst new file mode 100644 index 0000000..efb09b6 --- /dev/null +++ b/user/bsps/aarch64/raspberrypi4.rst @@ -0,0 +1,109 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +.. Copyright (C) 2022 Mohd Noor Aman + +.. _BSP_aarch64_Raspberrypi_4: + +Raspberry Pi 4B +=============== + +The 'raspberrypi4b' BSP currently supports only the LP64 ABI. ILP32 is not +supported. Raspberry pi 4B all variants and Raspberry Pi 400 are supported. The +default bootloader which is used by the Raspbian OS or other OS can be used to +boot RTEMS. SMP is currently not supported. + +Raspberry Pi 4B has 2 types of interrupt controller, GIC-400 (GICv2) and ARM +legacy generic controller. Both are supported. By default, raspberrypi 4B uses +ARM legacy generic controller. Set ``enable_gic=1`` in the ``config.txt`` file +to enable GIC. + +Clock Driver +------------ + +The clock driver uses the `ARM Generic Timer`. + +Console Driver +-------------- + +Raspberry pi 4B has 2 types of UARTs, ARM PL011 and Mini-uart. The PL011 is a +capable, broadly 16550-compatible UART, while the mini UART has a reduced +feature set. The console driver supports the default Qemu emulated ARM PL011 +PrimeCell UART as well as the physical ARM PL011 PrimeCell UART in the +raspberrypi hardware. Mini-uart is not supported. + +Preparing to boot +------------------ + +Raspberry Pi uses a different mechanism to boot when compared with any ARM SoC. +First the GPU initializes, loads the bootloader (Raspberry pi firmware) and then +looks for the kernel img. This whole process is done by the GPU (VideoCore IV) +till the kernel is loaded. More information can be found on the `Raspberry pi +documentation page +<https://www.raspberrypi.com/documentation/computers/raspberry-pi.html#boot-sequence>`_. +By default the arm64 mode looks for the ``kernel8.img``. Any other kernel can be +loaded by adding ``kernel=<img_name>`` to the ``config.txt`` file. + +The Firmware files are required in order to boot RTEMS. The latest firmware can +be downloaded from the `Raspberry Pi Firmware Repository +<https://github.com/raspberrypi/firmware/>`_. USB boot is supported. All the +files (Firmwares and kernel) must be place in the FAT32 partition only. Add +``arm_64bit=1`` in the ``config.txt`` file in order to boot the BSP in 64bit +kernel mode. + + +UART Setup +^^^^^^^^^^ + +Connect your serial device to the GPIO15 and GPIO14. Add the following to the +``config.txt`` file in order to use the PL011 UART0 and thus disabling the +default Mini-uart. + +.. code-block:: none + + # if user wants to enable GIC, uncomment the next line + # enable_gic=1 + arm_64bit=1 + dtoverlay = disable-bt + enable_uart=1 + +.. note:: + The Raspberry Pi 4B and 400 have an additional four PL011 UARTs. They are not + supported. + +Generating kernel image +^^^^^^^^^^^^^^^^^^^^^^^ + +The following steps show how to run ``hello.exe`` on the BSP. Other executables +can be processed in a similar way. + +To create the kernel image: + +.. code-block:: shell + + $ aarch64-rtems@rtems-ver-major@-objcopy -Obinary hello.exe kernel8.img + +Copy the kernel image to the SD card. + +JTAG Setup +---------- + +The Raspberry Pi 4 doesn't have dedicated JTAG pins. Instead, you must configure +the GPIO pins (GPIO22-GPIO27) to activate the JTAG functionality. The RPi 4 +documentation refers to this as Alt4 functions of those pins. Alt5 does exist +too, which goes from GPIO4, 5, 6, 12 and 13. you can check this out from +`pinout.xyz <https://pinout.xyz/pinout/jtag#>`_ or `eLinux +<https://elinux.org/RPi_BCM2835_GPIOs>`_ + +One more thing to note on JTAG with Raspberry pi 4B is that, by default, All the +GPIO pins are pulled down, according to the `BCM2711 documentation +<https://datasheets.raspberrypi.com/bcm2711/bcm2711-peripherals.pdf>`_. This +wasn't the case in the earlier models. So in order to let the data flow freely, +we will have to disable them. + +.. code-block:: none + + # Disable pull downs + gpio=22-27=np + + # Enable jtag pins (i.e. GPIO22-GPIO27) + enable_jtag_gpio=1 diff --git a/user/bsps/aarch64/xilinx-zynqmp.rst b/user/bsps/aarch64/xilinx-zynqmp.rst index 2b28132..4de0115 100644 --- a/user/bsps/aarch64/xilinx-zynqmp.rst +++ b/user/bsps/aarch64/xilinx-zynqmp.rst @@ -6,19 +6,39 @@ .. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_qemu: .. _BSP_aarch64_qemu_xilinx_zynqmp_ilp32_zu3eg: .. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_zu3eg: +.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_cfc400x: Qemu Xilinx ZynqMP ================== -This BSP supports four variants: `xilinx-zynqmp-ilp32-qemu`, -`xilinx-zynqmp-lp64-qemu`, `xilinx-zynqmp-ilp32-zu3eg`, and -`xilinx-zynqmp-lp64-zu3eg`. Platform-specific hardware initialization is -performed by ARM Trusted Firmware (ATF). Other basic hardware initialization is -performed by the BSP. These BSPs support the GICv2 interrupt controller present -in all ZynqMP systems. The zu3eg BSPs have also been tested to be fully -functional on zu2cg boards and should also work on any other ZynqMP chip variant -since the Processing Subsystem (PS) does not vary among chip variants other than -the number of CPU cores available. +This BSP family supports the following variants: + +* `xilinx-zynqmp-ilp32-qemu` + +* `xilinx-zynqmp-lp64-qemu` + +* `xilinx-zynqmp-ilp32-zu3eg` + +* `xilinx-zynqmp-lp64-zu3eg` + +* `xilinx-zynqmp-lp64-cfc400x` + +Platform-specific hardware initialization is performed by ARM Trusted Firmware +(ATF). Other basic hardware initialization is performed by the BSP. These BSPs +support the GICv2 interrupt controller present in all ZynqMP systems. The zu3eg +BSPs have also been tested to be fully functional on zu2cg boards and should +also work on any other ZynqMP chip variant since the Processing Subsystem (PS) +does not vary among chip variants other than the number of CPU cores available. + +This BSP family has been tested on the following hardware: + +* `Avnet UltraZed-EG SOM` + +* `Innoflight CFC-400X` + +* `Trenz TE0802` + +* `Xilinx ZCU102` Boot on QEMU ------------ @@ -33,6 +53,14 @@ will drop to EL1 for execution. For quick turnaround during testing, it is recommended to use the u-boot BOOT.bin that comes with the PetaLinux prebuilts for the board in question. +Some systems such as the CFC-400X may require a bitstream to be loaded into the +FPGA portion of the chip to operate as expected. This bitstream must be loaded +before RTEMS begins operation since accesses to programmable logic (PL) memory +space can cause the CPU to hang if the FPGA is not initialized. This can be +performed as part of BOOT.bin or by a bootloader such as u-boot. Loading +bitstreams from RTEMS has not been tested on the ZynqMP platform and requires +additional libraries from Xilinx. + Hardware Boot Image Generation ------------------------------ @@ -225,7 +253,7 @@ as well as the physical ARM PL011 PrimeCell UART in the ZynqMP hardware. SDHCI Driver ------------ -The ZynqMP bsp has an SDHCI driver which allows reading to and writing from SD +The ZynqMP bsp has an SDHCI driver which allows writing to and reading from SD cards. These can be tested in qemu using the "-sd" option. For example: .. code-block:: shell @@ -242,7 +270,7 @@ Network Configuration When used with LibBSD, these BSP variants support networking via the four Cadence GEM instances present on all ZynqMP hardware variants. All interfaces are enabled by default, but only interfaces with operational MII busses will be -recognized and usable in RTEMS. Most ZynqMP dev boards use CGEM3. +recognized and usable in RTEMS. Most ZynqMP dev boards use RGMII with CGEM3. When used with lwIP from the rtems-lwip integration repository, these BSP variants support networking via CGEM0 and one of the other CGEM* instances diff --git a/user/bsps/arm/altera-cyclone-v.rst b/user/bsps/arm/altera-cyclone-v.rst index eaa02e3..12e563e 100644 --- a/user/bsps/arm/altera-cyclone-v.rst +++ b/user/bsps/arm/altera-cyclone-v.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2017, 2019 embedded brains GmbH +.. Copyright (C) 2017, 2019 embedded brains GmbH & Co. KG .. Copyright (C) 2017, 2019 Sebastian Huber altera-cyclone-v (Intel Cyclone V) diff --git a/user/bsps/arm/fvp.rst b/user/bsps/arm/fvp.rst index a1e186a..b938e30 100644 --- a/user/bsps/arm/fvp.rst +++ b/user/bsps/arm/fvp.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2022 embedded brains GmbH +.. Copyright (C) 2022 embedded brains GmbH & Co. KG fvp (Fixed Virtual Platform) ============================ diff --git a/user/bsps/arm/imx.rst b/user/bsps/arm/imx.rst index f0ac928..47ad503 100644 --- a/user/bsps/arm/imx.rst +++ b/user/bsps/arm/imx.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2017, 2019 embedded brains GmbH +.. Copyright (C) 2017, 2019 embedded brains GmbH & Co. KG .. Copyright (C) 2017, 2019 Sebastian Huber imx (NXP i.MX) diff --git a/user/bsps/arm/imxrt.rst b/user/bsps/arm/imxrt.rst index e185823..30b1437 100644 --- a/user/bsps/arm/imxrt.rst +++ b/user/bsps/arm/imxrt.rst @@ -1,29 +1,48 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2020 embedded brains GmbH +.. Copyright (C) 2020 embedded brains GmbH & Co. KG .. Copyright (C) 2020 Christian Mauderer imxrt (NXP i.MXRT) ================== -This BSP offers only one variant, the `imxrt1052`. This variant supports the -i.MXRT 1052 processor on a IMXRT1050-EVKB (tested with rev A1). You can also -configure it to work with custom boards. +This BSP offers multiple variants. The `imxrt1052` supports the i.MXRT 1052 +processor on a IMXRT1050-EVKB (tested with rev A1). Some possibilities to adapt +it to a custom board are described below. NOTE: The IMXRT1050-EVKB has an backlight controller that must not be enabled without load. Make sure to either attach a load, disable it by software or disable it by removing the 0-Ohm resistor on it's input. +The `imxrt1166-cm7-saltshaker` supports an application specific board. Adapting +it to another i.MXRT1166 based board works similar like for the `imxrt1052` BSP. + Build Configuration Options --------------------------- Please see the documentation of the `IMXRT_*` and `BSP_*` configuration options for that. You can generate a default set of options with:: - ./waf bsp_defaults --rtems-bsps=arm/imxrt1052 > config.ini + ./waf bspdefaults --rtems-bsps=arm/imxrt1052 > config.ini -Boot Process ------------- +Adapting to a different board +----------------------------- + +This is only a short overview for the most important steps to adapt the BSP to +another board. Details for most steps follow further below. + +#. The device tree has to be adapted to fit the target hardware. +#. A matching clock configuration is necessary (simplest method is to generate + it with the NXP PinMux tool) +#. The `dcd_data` has to be adapted. That is used for example to initialize + SDRAM. +#. `imxrt_flexspi_config` has to be adapted to match the Flash connected to + FlexSPI (if that is used). +#. `BOARD_InitDEBUG_UARTPins` should be adapted to match the used system + console. + +Boot Process of IMXRT1050-EVKB +------------------------------ There are two possible boot processes supported: @@ -82,18 +101,19 @@ ones that need different values): You can find the default definitions in `bsps/arm/imxrt/start/flash-*.c`. Take a look at the `i.MX RT1050 Processor Reference Manual, Rev. 4, 12/2019` chapter -`9.7 Program image` for details about the contents. +`9.7 Program image` or `i.MX RT1166 Processor Reference Manual, Rev. 0, 05/2021` +chapter `10.7 Program image` for details about the contents. FDT --- The BSP uses a FDT based initialization. The FDT is linked into the application. -You can find the default FDT used in the BSP in -`bsps/arm/imxrt/dts/imxrt1050-evkb.dts`. The FDT is split up into two parts. The -core part is put into an `dtsi` file and is installed together with normal -headers into `${PREFIX}/arm-rtems@rtems-ver-major@/imxrt1052/lib/include`. You -can use that to create your own device tree based on that. Basically use -something like:: +You can find the default FDT used in the BSPs in `bsps/arm/imxrt/dts`. The FDT +is split up into two parts. The controller specific part is put into an `dtsi` +file. The board specific one is in the dts file. Both are installed together +with normal headers into +`${PREFIX}/arm-rtems@rtems-ver-major@/${BSP}/lib/include`. You can use that to +create your own device tree based on that. Basically use something like:: /dts-v1/; @@ -137,26 +157,6 @@ You'll get a C file which defines the `imxrt_dtb` array. Make sure that your new C file is compiled and linked into the application. It will overwrite the existing definition of the `imxrt_dtb` in RTEMS. -PLL Settings ------------- - -The commercial variant of the i.MXRT1052 on the evaluation board allows a clock -up to 600MHz for the ARM core. For some industrial variants only up to 528MHz -are specified. To make it possible to adapt to these variants the application -can overwrite the following constant: - -.. code-block:: c - - #include "fsl_clock_config.h" - - const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 100, - .src = 0, - }; - -With the default configuration of a 24MHz oscillator, the loopDivider has to be -88 for the 528MHz. - Clock Driver ------------ @@ -198,10 +198,38 @@ Note that the SPI-pins on the evaluation board are shared with the SD card. Populate R278, R279, R280, R281 on the IMXRT1050-EVKB (Rev A) to use the SPI pins on the Arduino connector. +By default, the native chip selects are used. If you want to use GPIOs as chip +select instead, you can use the `cs-gpios` and `num-cs` attributes just like on +a Linux SPI controller. A maximum of `IMXRT_LPSPI_MAX_CS` pins can be used. + +The hardware doesn't support selecting no native chip select during a transfer. +Therefore one native chip select has to be reserved as a dummy if you want to be +able to use GPIOs. The pin function for this chip select must not be configured +on any pin. Dummy will be the first of the first four chip selects that is not a +native one. Example configuration:: + + &lpspi4 { + status = "okay"; + pinctrl-0 = <&my_pinctrl_lpspi4>; + cs-gpios = <0>, <0>, <&gpio1 1 0>, <0>, <&gpio11 5 1>; + num-cs = <5>; + } + +In this case, CS2 will be the dummy chip select and no pin must be configured +with that function. CS0, CS1 and CS3 are just native chip selects and should be +used via pin functions. GPIO1.1 is used as a high active CS and GPIO11.5 a low +active one. + Limitations: * Only a basic SPI driver is implemented. This is mostly a driver limitation and not a hardware one. +* GPIO CS pins on i.MXRT10xx are not tested. The chip has a lot of errate so + they might not work. +* Switching from one mode (CPOL/CPHA) to another one can lead to single wrong + edges on the CLK line if GPIO CS pins are involved. Make sure to stuff a dummy + transfer with `SPI_NO_CS` set if you use multiple modes together with a GPIO + CS. Network Interface Driver ------------------------ @@ -225,13 +253,58 @@ the SDK. But please note that they are not tested and maybe won't work out of the box. Everything that works with interrupts most likely needs some special treatment. -Caveats -------- +The SDK files are imported to RTEMS from the NXP mcux-sdk git repository that +you can find here: https://github.com/nxp-mcuxpresso/mcux-sdk/ + +The directory structure has been preserved and all files are in a +`bsps/arm/imxrt/mcux-sdk` directory. All patches to the files are marked with +`#ifdef __rtems__` markers. + +The suggested method to import new or updated files is to apply all RTEMS +patches to the mcux-sdk repository, rebase them to the latest mcux-sdk release +and re-import the files. The new base revision should be mentioned in the commit +description to make future updates simpler. + +A import helper script (that might or might not work on newer releases of the +mcux-sdk) can be found here: +https://raw.githubusercontent.com/c-mauderer/nxp-mcux-sdk/d21c3e61eb8602b2cf8f45fed0afa50c6aee932f/export_to_RTEMS.py + +Clocks and SDRAM +---------------- The clock configuration support is quite rudimentary. The same is true for SDRAM. It mostly relies on the DCD and on a static clock configuration that is taken from the NXP SDK example projects. -The MPU settings are currently quite permissive. +If you need to adapt the DCD or clock config to support a different hardware, +you should generate these files using the NXP MCUXpresso Configuration Tools. +You can add the generated files to your application to overwrite the default +RTEMS ones or you can add them to RTEMS in a new BSP variant. + +As a special case, the imxrt1052 BSP will adapt it's PLL setting based on the +chip variant. The commercial variant of the i.MXRT1052 will use a core clock of +600MHz for the ARM core. The industrial variants only uses 528MHz. For other +chip or BSP variants, you should adapt the files generated with the MCUXpresso +Configuration Tools. + +Caveats +------- + +* The MPU settings are currently quite permissive. + +* There is no power management support. + +* On the i.MXRT1166, sleeping of the Cortex M7 can't be disabled even for + debugging purposes. That makes it hard for a debugger to access the + controller. To make debugging a bit easier, it's possible to overwrite the + idle thread with the following one in the application: + + .. code-block:: c -There is no power management support. + void * _CPU_Thread_Idle_body(uintptr_t ignored) + { + (void)ignored; + while (true) { + /* void */ + } + } diff --git a/user/bsps/arm/lpc24xx.rst b/user/bsps/arm/lpc24xx.rst index ecf1d84..f287dc8 100644 --- a/user/bsps/arm/lpc24xx.rst +++ b/user/bsps/arm/lpc24xx.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2017, 2019 embedded brains GmbH +.. Copyright (C) 2017, 2019 embedded brains GmbH & Co. KG .. Copyright (C) 2017, 2019 Sebastian Huber lpc24xx (NXP LPC17XX/LPC24XX/LPC40XX) diff --git a/user/bsps/arm/realview-pbx-a9.rst b/user/bsps/arm/realview-pbx-a9.rst index 15d1fbf..bbe0269 100644 --- a/user/bsps/arm/realview-pbx-a9.rst +++ b/user/bsps/arm/realview-pbx-a9.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +.. Copyright (C) 2020 embedded brains GmbH & Co. KG realview-pbx-a9 =============== diff --git a/user/bsps/arm/stm32h7.rst b/user/bsps/arm/stm32h7.rst index ec7440f..cdf4d43 100644 --- a/user/bsps/arm/stm32h7.rst +++ b/user/bsps/arm/stm32h7.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2020 embedded brains GmbH +.. Copyright (C) 2020 embedded brains GmbH & Co. KG .. Copyright (C) 2022 Karel Gardas <karel@functional.vision> @@ -248,7 +248,7 @@ installed. Please go to its *bin* directory. E.g. $ cd plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.0.200.202202231230/tools/bin Now, you will need to edit provided *config.txt* file inside the -directory. Use your favorite editor. Open the file and scrolls +directory. Use your favorite editor. Open the file and scroll down to its end. You will see following comment: .. code-block:: none @@ -332,7 +332,7 @@ Generate default configuration for the board: .. code-block:: shell - $ ./waf bsp_defaults --rtems-bsps=arm/stm32h747i-disco > stm32h747i-disco.ini + $ ./waf bspdefaults --rtems-bsps=arm/stm32h747i-disco > stm32h747i-disco.ini Regenerate build specification cache (needs a couple of seconds)... To run basic hello world or ticker samples you do not need to modify diff --git a/user/bsps/arm/xilinx-zynqmp-rpu.rst b/user/bsps/arm/xilinx-zynqmp-rpu.rst new file mode 100644 index 0000000..0dfb77e --- /dev/null +++ b/user/bsps/arm/xilinx-zynqmp-rpu.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +.. Copyright (C) 2024 On-Line Applications Research Corporation (OAR) + +.. _BSP_arm_xilinx_zynqmp_rpu: + +Xilinx ZynqMP RPU +================= + +This BSP supports the Cortex-R5 processor on the Xilinx Zynq UltraScale+ MPSoC +platform. Basic hardware initialization is performed by the Cortex-R5 FSBL and +the BSP. This BSP supports the GICv2 interrupt controller available to the +Cortex-R5 subsystem. Since the Cortex-R5 subsystem only varies in speed, this +BSP should be functional across all chip variants as well as on Xilinx's QEMU +branch. SMP operation is not currently supported. + +Clock Driver +------------ + +The clock driver uses one of the available triple timer counters (TTCs) as the +timer interrupt source. + +Console Driver +-------------- + +The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART +as well as the physical ARM PL011 PrimeCell UART in the ZynqMP hardware. + +Boot on ZynqMP Hardware +----------------------- + +On the ZynqMP RPU, RTEMS can be started by Cortes-R5 u-boot, Cortex-A53 u-boot, +via JTAG, or directly as part of BOOT.bin. For quick turnaround during testing, +it is recommended to use Cortex-A53 u-boot to avoid repeated BOOT.bin +generation since the provided Cortex-R5 u-boot is highly limited and has no +network or MMC/SD access. + +Note that if the RPU image is started by the Cortex-A53 u-boot, the program +sections located at ZYNQMP_RPU_RAM_INT_0_ORIGIN and ZYNQMP_RPU_RAM_INT_1_ORIGIN +must be manually relocated from DDR to TCM since the TCMs are not directly +available to the Cortex-A53 cores at their Cortex-R5 internal addresses. This +can be accomplished by disabling dcache in u-boot and using u-boot's "cp" +command. Once this is done, the program can be started at 0x0 by using u-boot's +"cpu" command to first disable core 4 and then release it in split mode. + +Hardware Boot Image Generation +------------------------------ + +When generating BOOT.bin from components, the BIF file should include at least +entries for the Cortex-R5 FSBL ([bootloader,destination_cpu=r5-0]) and the +Cortex-R5 application ([destination_cpu=r5-0]). The Cortex-R5 application should +be either a u-boot or RTEMS ELF binary. The Cortex-R5 u-boot binary can be +obtained by building it from Xilinx's u-boot repository. The Cortex-R5 FSBL can +be obtained setting up an appropriate platform project in Xilinx's current +development system. + +Boot on QEMU +------------ +The executable image is booted by Qemu in ELF format. + +Running Executables on QEMU +--------------------------- + +Xilinx's qemu-devicetrees repository must be used in conjunction with the Xilinx +QEMU available via RSB. Executables generated by this BSP can be run using the +following command: + +.. code-block:: shell + + qemu-system-aarch64 -no-reboot -nographic -M arm-generic-fdt -serial null \ + -serial mon:stdio -device loader,file=example.exe,cpu-num=4 \ + -device loader,addr=0xff5e023c,data=0x80088fde,data-len=4 \ + -device loader,addr=0xff9a0000,data=0x80000218,data-len=4 \ + -hw-dtb /xlnx-qemu-devtrees-path/LATEST/SINGLE_ARCH/board-zynqmp-zcu102.dtb \ + -m 4096 -display none + +Debugging Executables on QEMU +----------------------------- + +Debugging the RPU cores under QEMU presents unique challenges due to requiring +the AArch64 QEMU to emulate the entire processing subsystem. Debugging requires +a multi-arch GDB which can be created by adding "--enable-targets=all" to the +normal GDB configure line and then building as normal. + +To attach to the RPU core once QEMU is started with "-s -S", The following steps +are required: + +.. code-block:: shell + + aarch64-rtems6-gdb + (gdb) tar ext :1234 + (gdb) add-inferior + (gdb) inferior 2 + (gdb) file example.exe + (gdb) attach 2 diff --git a/user/bsps/arm/xilinx-zynqmp.rst b/user/bsps/arm/xilinx-zynqmp.rst index 9a605bb..fa60470 100644 --- a/user/bsps/arm/xilinx-zynqmp.rst +++ b/user/bsps/arm/xilinx-zynqmp.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2019 embedded brains GmbH +.. Copyright (C) 2019 embedded brains GmbH & Co. KG xilinx-zynqmp ============= diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst index 933370f..f99843a 100644 --- a/user/bsps/bsps-aarch64.rst +++ b/user/bsps/bsps-aarch64.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG aarch64 (AArch64) ***************** @@ -9,3 +9,4 @@ aarch64 (AArch64) .. include:: aarch64/a72.rst .. include:: aarch64/xilinx-versal.rst .. include:: aarch64/xilinx-zynqmp.rst +.. include:: aarch64/raspberrypi4.rst
\ No newline at end of file diff --git a/user/bsps/bsps-arm.rst b/user/bsps/bsps-arm.rst index d9b5d01..bd335fa 100644 --- a/user/bsps/bsps-arm.rst +++ b/user/bsps/bsps-arm.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2017, 2019 embedded brains GmbH +.. Copyright (C) 2017, 2019 embedded brains GmbH & Co. KG .. Copyright (C) 2017, 2019 Sebastian Huber arm (ARM) @@ -31,3 +31,4 @@ arm (ARM) arm/xen.rst arm/xilinx-zynq.rst arm/xilinx-zynqmp.rst + arm/xilinx-zynqmp-rpu.rst diff --git a/user/bsps/bsps-bfin.rst b/user/bsps/bsps-bfin.rst index db7f721..eeb426e 100644 --- a/user/bsps/bsps-bfin.rst +++ b/user/bsps/bsps-bfin.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG bfin (Blackfin) *************** diff --git a/user/bsps/bsps-i386.rst b/user/bsps/bsps-i386.rst index 0b273ee..81f5fd8 100644 --- a/user/bsps/bsps-i386.rst +++ b/user/bsps/bsps-i386.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG i386 **** diff --git a/user/bsps/bsps-lm32.rst b/user/bsps/bsps-lm32.rst index 2db5b12..98ffb91 100644 --- a/user/bsps/bsps-lm32.rst +++ b/user/bsps/bsps-lm32.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG lm32 (LatticeMicro32) ********************* diff --git a/user/bsps/bsps-m68k.rst b/user/bsps/bsps-m68k.rst index bdb516b..a820d96 100644 --- a/user/bsps/bsps-m68k.rst +++ b/user/bsps/bsps-m68k.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG m68k (Motorola 68000 / ColdFire) ******************************** diff --git a/user/bsps/bsps-microblaze.rst b/user/bsps/bsps-microblaze.rst index 32aad90..6fe4891 100644 --- a/user/bsps/bsps-microblaze.rst +++ b/user/bsps/bsps-microblaze.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG .. Copyright (C) 2022 On-Line Applications Research Corporation (OAR) microblaze (MicroBlaze) @@ -21,13 +21,21 @@ Clock Driver ------------ The clock driver supports the QEMU emulated Xilinx AXI Timer v2.0. It is -implemented as a simple downcounter. +implemented as a simple downcounter. If device tree support is enabled in the +build configuration, the clock driver will use the node that is compatible with +`xlnx,xps-timer-1.00.a` from the device tree to configure the clock. The +following device tree node properties are used to configure the clock driver: +``reg``, ``clock-frequency``, and ``interrupts``. Console Driver -------------- The console driver supports the QEMU emulated Xilinx AXI UART Lite v2.0. It is -initialized to a baud rate of 115200. +initialized to a baud rate of 115200. If device tree support is enabled in the +build configuration, the console driver will use the node that is compatible +with `xlnx,xps-uartlite-1.00.a` from the device tree to configure the console. +The following device tree node properties are used to configure the console +driver: ``reg``, ``status``, ``port-number``, and ``interrupts``. Network Driver -------------- @@ -61,6 +69,18 @@ to include it in the BSP build. BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH = /path/to/my_dtb.c +QSPI NOR JFFS2 Driver +--------------------- + +The QSPI NOR JFFS2 driver supports the QEMU emulated n25q512a11 QSPI NOR flash +device. It is initialized to a page size of 256 bytes and a sector size of 64 +KiB. If device tree support is enabled in the build configuration, the QSPI NOR +JFFS2 driver will use the node that is compatible with `xlnx,xps-spi-2.00.a` +from the device tree to configure the QSPI NOR JFFS2 driver. The following +device tree node properties are used to configure the QSPI NOR JFFS2 driver: +``reg`` and ``interrupts``. + + Running Executables ------------------- @@ -114,12 +134,21 @@ Clock Driver ------------ The clock driver supports the Xilinx AXI Timer v2.0. It is implemented as a -simple downcounter. +simple downcounter. If device tree support is enabled in the +build configuration, the clock driver will use the node that is compatible with +`xlnx,xps-timer-1.00.a` from the device tree to configure the clock. The +following device tree node properties are used to configure the clock driver: +``reg``, ``clock-frequency``, and ``interrupts``. Console Driver -------------- -The console driver supports the Xilinx AXI UART Lite v2.0. +The console driver supports the Xilinx AXI UART Lite v2.0. It is initialized to +a baud rate of 115200. If device tree support is enabled in the build +configuration, the console driver will use the node that is compatible with +`xlnx,xps-uartlite-1.00.a` from the device tree to configure the console. The +following device tree node properties are used to configure the console driver: +``reg``, ``status``, ``port-number``, and ``interrupts``. Debugging --------- diff --git a/user/bsps/bsps-mips.rst b/user/bsps/bsps-mips.rst index 9f83811..f90732a 100644 --- a/user/bsps/bsps-mips.rst +++ b/user/bsps/bsps-mips.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG mips (MIPS) *********** diff --git a/user/bsps/bsps-moxie.rst b/user/bsps/bsps-moxie.rst index eab88cc..8548777 100644 --- a/user/bsps/bsps-moxie.rst +++ b/user/bsps/bsps-moxie.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG moxie ***** diff --git a/user/bsps/bsps-nios2.rst b/user/bsps/bsps-nios2.rst index ad21dd3..5280025 100644 --- a/user/bsps/bsps-nios2.rst +++ b/user/bsps/bsps-nios2.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG nios2 (Nios II) *************** diff --git a/user/bsps/bsps-or1k.rst b/user/bsps/bsps-or1k.rst index 6295c23..e7d9a10 100644 --- a/user/bsps/bsps-or1k.rst +++ b/user/bsps/bsps-or1k.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG or1k (OpenRISC 1000) ******************** diff --git a/user/bsps/bsps-powerpc.rst b/user/bsps/bsps-powerpc.rst index 3d1ce88..6b63936 100644 --- a/user/bsps/bsps-powerpc.rst +++ b/user/bsps/bsps-powerpc.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG powerpc (PowerPC) ***************** diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 5faa87b..263796e 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG riscv (RISC-V) ************** @@ -8,7 +8,8 @@ riscv (RISC-V) riscv ===== -This BSP offers 13 variants: +**Each variant in this first group corresponds to a GCC multilib option with +different RISC-V standard extensions.** * rv32i @@ -26,26 +27,30 @@ This BSP offers 13 variants: * rv64imac -* rv64imac_medany - * rv64imafd -* rv64imafd_medany - * rv64imafdc -* rv64imafdc_medany +Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs have +medany code model by default, while rv32 BSPs are medlow. The reason is that +RV32 medlow can access the entire 32-bit address space, while RV64 medlow can +only access addresses below 0x80000000. With RV64 medany, it's possible to +perform accesses above 0x80000000. The BSP must be started in machine mode. + +The reference platforms for the rv* variants include the QEMU `virt` and +`spike` machines and the Spike RISC-V ISA simulator. + +**The BSP also provides the following variants for specific hardware targets:** -* frdme310arty +* frdme310arty - The reference platform for this variant is the Arty FPGA board + with the SiFive Freedom E310 reference design. -Each variant corresponds to a GCC multilib. A particular variant reflects an -ISA with ABI and code model choice. +* mpfs64imafdc - The reference platform for this variant is the Microchip + PolarFire SoC Icicle Kit. -The basic hardware initialization is not performed by the BSP. A boot loader -with device tree support must be used to start the BSP, e.g. BBL. The BSP must -be started im machine mode. +* kendrytek210 - The reference platform for this variant is the Kendryte K210 + SoC on the Sipeed MAiX BiT or Maixduino board. -The reference platform for this BSP is the Qemu `virt` machine. Build Configuration Options --------------------------- @@ -68,31 +73,51 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. ``BSP_FDT_BLOB_SIZE_MAX`` The maximum size of the device tree blob in bytes (default is 65536). +``BSP_DTB_IS_SUPPORTED`` + If defined to a non-zero value, then the device tree blob is embedded in + the BSP. + +``BSP_DTB_HEADER_PATH`` + The path to the header file containing the device tree blob. + ``BSP_CONSOLE_BAUD`` - The default baud for console driver devices (default 115200). + The default baud for console driver devices (default is 115200). ``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS`` The maximum number of external interrupts supported by the BSP (default - 64). + is 64). ``RISCV_ENABLE_HTIF_SUPPORT`` - Enables the HTIF support if defined to a non-zero value, otherwise it is - disabled (disabled by default). + Enable the Host/Target Interface (HTIF) support (enabled by default). ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` - The maximum number of NS16550 devices supported by the console driver (2 - by default). + The maximum number of NS16550 devices supported by the console driver + (default is 2). + +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` + Enable the SiFive console UART (disabled by default). ``RISCV_RAM_REGION_BEGIN`` - The begin of the RAM region for linker command file (default is 0x70000000 - for 64-bit with -mcmodel=medlow and 0x80000000 for all other). + The begin of the RAM region for linker command file + (default is 0x80000000). ``RISCV_RAM_REGION_SIZE`` The size of the RAM region for linker command file (default 64MiB). ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` Enables support sifive Freedom E310 Arty board if defined to a non-zero - value,otherwise it is disabled (disabled by default) + value,otherwise it is disabled (disabled by default). + +``RISCV_ENABLE_MPFS_SUPPORT`` + Enables support Microchip PolarFire SoC if defined to a non-zero + value, otherwise it is disabled (disabled by default). + +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` + Enables support for the Kendtryte K210 SoC if defined to a non-zero + value, otherwise it is disabled (disabled by default). + +``RISCV_BOOT_HARTID`` + The boot hartid (processor number) of risc-v cpu by default 0. Interrupt Controller -------------------- @@ -110,20 +135,341 @@ The clock driver uses the CLINT timer. Console Driver -------------- -The console driver supports devices compatible to +The console driver supports devices compatible to: * "ucb,htif0" (depending on the ``RISCV_ENABLE_HTIF_SUPPORT`` BSP option), -* "ns16550a" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option), and +* "ns16550a" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option), -* "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). +* "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option), and -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). They are initialized according to the device tree. The console driver does not configure the pins or peripheral clocks. The console device is selected according to the device tree "/chosen/stdout-path" property value. +QEMU +---- + +All of the BSP variants that start with rv can be run on QEMU's virt +and spike machines. For instance, to run the ``rv64imafdc`` BSP with the +following "config.ini" file. + +.. code-block:: none + + [riscv/rv64imafdc] + +Run the following QEMU command. + +.. code-block:: shell + + $ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE + $ qemu-system-riscv64 -M spike -nographic -bios $RTEMS_EXE + +Spike +---- + +All of the BSP variants that start with rv can be run on Spike. For instance, +to run the ``rv64imafdc`` BSP with the following "config.ini" file. + +.. code-block:: none + + [riscv/rv64imafdc] + +Run the following Spike command. + +.. code-block:: shell + + $ spike --isa=rv64imafdc $RTEMS_EXE + +Unlike QEMU, Spike supports enabling/disabling a subset of the imafdc +extensions and has support for further RISC-V extensions as well. A fault will +be triggered if an executable built with rv64imafdc RISC-V's -march option run +on Spike with --isa=rv64i option. If no --isa option is specified, the default +is rv64imafdc. + +Microchip PolarFire SoC +----------------------- + +The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and a 64-bit RISC-V E51 +monitor core SoC from the Microchip. + +The ``mpfs64imafdc`` BSP variant supports the U54 cores but not the E51 because +the E51 monitor core is reserved for the first stage bootloader (Hart Software +Services). In order to boot from the first U54 core, ``RISCV_BOOT_HARTID`` is +set to 1 by default. + +The device tree blob is embedded in the ``mpfs64imafdc`` BSP variant by default +with the ``BSP_DTB_IS_SUPPORTED`` enabled and the DTB header path +``BSP_DTB_HEADER_PATH`` is set to bsp/mpfs-dtb.h. + +**SMP test procedure for the Microchip PolarFire Icicle Kit:** + +The "config.ini" file. + +.. code-block:: none + + [riscv/mpfs64imafdc] + BUILD_TESTS = True + RTEMS_POSIX_API=True + RTEMS_SMP = True + BSP_START_COPY_FDT_FROM_U_BOOT=False + BSP_VERBOSE_FATAL_EXTENSION = False + +Build RTEMS. + +.. code-block:: shell + + $ ./waf configure --prefix=$HOME/rtems-start/rtems/@rtems-ver-major@ + $ ./waf + +Convert .exe to .elf file. + +.. code-block:: shell + + $ riscv-rtems@rtems-ver-major@-objcopy build/riscv/mpfs64imafdc/testsuites/smptests/smp01.exe build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf + +Generate a payload for the `smp01.elf` using the `hss-payload-generator <https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator>`_. + +* Copy `smp01.elf` file to the HSS/tools/hss-payload-generator/test directory. + +* Go to hss-payload-generator source directory. + +.. code-block:: shell + + $ cd hart-software-services/tools/hss-payload-generator + +* Edit test/uboot.yaml file for the hart entry points and correct name of the + binary file. + +.. code-block:: none + + set-name: 'PolarFire-SoC-HSS::RTEMS' + hart-entry-points: {u54_1: '0x1000000000', u54_2: '0x1000000000', u54_3: '0x1000000000', u54_4: '0x1000000000'} + payloads: + test/smp01.elf: {exec-addr: '0x1000000000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_m, skip-opensbi: true} + +* Generate payload + +.. code-block:: shell + + $ ./hss-payload-generator -c test/uboot.yaml payload.bin + +Once the payload binary is generated, it should be copied to the eMMC/SD. + +`FPGA design with HSS programming file <https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md>`_. + +Program the eMMC/SD with the payload binary. + +* Power Cycle the Microchip PolarFire Icicle Kit and stop at the HSS. + +* type "mmc" and then "usbdmsc" on the HSS terminal(UART0). + +* Load the payload.bin from the Host PC. + +.. code-block:: shell + + $ sudo dd if=payload.bin of=/dev/sdb bs=512 + +Reset the Microchip PolarFire SoC Icicle Kit. + +Serial terminal UART1 displays the SMP example messages + +.. code-block:: none + + *** BEGIN OF TEST SMP 1 *** + *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c + *** TEST STATE: EXPECTED_PASS + *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP + *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB 3cb78b0b815ba05d17f5c6 + 5865d246a8333aa087, Newlib ea99f21) + + CPU 3 start task TA0 + CPU 2 running Task TA0 + CPU 3 start task TA1 + CPU 1 running Task TA1 + CPU 3 start task TA2 + CPU 0 running Task TA2 + + *** END OF TEST SMP 1 *** + +Kendryte K210 +------------- + +The Kendryte K210 SoC is a dual core 64-bit RISC-V SoC with an AI NPU, built in +SRAM, and a variety of peripherals. Currently just the console UART, interrupt +controller, and timer are supported. + +The device tree blob is embedded in the ``kendrytek210`` BSP variant by +default. When the kendrytek210 BSP variant is selected, +``BSP_DTB_IS_SUPPORTED`` enabled and the DTB header path +``BSP_DTB_HEADER_PATH`` is set to ``bsp/kendryte-k210-dtb.h``. + +The ``kendrytek210`` BSP variant has been tested on the following simulator and +boards: + +* Renode.io simulator using the Kendrtye k210 model +* Sipeed MAiX BiT board +* Sipeed Maixduino board +* Sipeed MAiX Dock board + +**Building the Kendryte K210 BSP** + +Configuration file ``config.ini``: + +.. code-block:: none + + [riscv/kendrytek210] + RTEMS_SMP = True + +Build RTEMS: + +.. code-block:: shell + + $ ./waf configure --prefix=$HOME/rtems-start/rtems/@rtems-ver-major@ + $ ./waf + +**Flash an executable to a supported K210 board** + +Binary images can be flashed to the Sipeed boards through the USB port using +the ``kflash.py`` utility available from the python pip utility. + +.. code-block:: shell + + $ riscv-rtems@rtems-ver-major@-objcopy -Obinary ticker.exe ticker.bin + $ kflash.py --uart /dev/ttyUSB0 ticker.bin + +After the image is flashed, the RTEMS image will automatically boot. It will +also run when the board is reset or powered through the USB cable. The USB port +provides the power and console UART. Plug the USB cable into a host PC and +bring up a terminal emulator at 115200 baud, 8 data bits, 1 stop bit, no +parity, and no flow control. On Linux the UART device is often +``/dev/ttyUSB0``. + +**Run a RTEMS application on the Renode.io simulator** + +RTEMS executables compiled with the kendrytek210 BSP can run on the renode.io +simulator using the built-in K210 model. The simulator currently supports the +console UART, interrupt controller, and timer. + +To install renode.io please refer to the `installation instructions <https://github.com/renode/renode#installation>`_. +Once installed, save the following file as `k210_rtems.resc`. + +.. code-block:: shell + + using sysbus + + $bin?=@ticker.exe + + mach create "K210" + + machine LoadPlatformDescription @platforms/cpus/kendryte_k210.repl + + showAnalyzer uart + + sysbus Tag <0x50440000 0x10000> "SYSCTL" + sysbus Tag <0x50440018 0x4> "pll_lock" 0xFFFFFFFF + sysbus Tag <0x5044000C 0x4> "pll1" + sysbus Tag <0x50440008 0x4> "pll0" + sysbus Tag <0x50440020 0x4> "clk_sel0" + sysbus Tag <0x50440028 0x4> "clk_en_cent" + sysbus Tag <0x5044002c 0x4> "clk_en_peri" + + macro reset + """ + sysbus LoadELF $bin + """ + runMacro $reset + +After saving the above file in in the same directory as your RTEMS ELF images, +start renode and load the `k210_rtems.resc` script to start the emulation. + +.. code-block:: shell + + (monitor) s @k210_rtems.resc + +You should see a renode UART window and the RTEMS ticker example output. If you +want to run a different RTEMS image, you can edit the file or enter the +following on the renode console. + +.. code-block:: shell + + (monitor) $bin=@smp08.exe + (monitor) s @k210_rtems.resc + +The above example will run the SMP08 example instead of ticker. + +**Generating the Device Tree Header** + +The kendrytek210 BSP uses a built in device tree blob. If additional peripheral +support is added to the BSP, the device tree may need to be updated. After +editing the device tree source, compile it to a device tree blob with the +following command: + +.. code-block:: shell + + $ dtc -O dtb -b 0 -o kendryte-k210.dtb kendryte-k210.dts + +The dtb file can then be converted to a C array using the rtems-bin2c tool. +The data for the device tree binary can then replace the existing device tree +binary data in the ``kendryte-k210-dtb.h`` header file. + +noel +==== + +This BSP supports the `NOEL-V <https://gaisler.com/noel-v>`_ systems from +Cobham Gaisler. The NOEL-V is a synthesizable VHDL model of a processor that +implements the RISC-V architecture. It is part of the open source `GRLIB +<https://gaisler.com/grlib>`_ IP Library. The following BSP variants correspond +to common NOEL-V configurations: + +* noel32im + +* noel32imafd + +* noel64imac + +* noel64imafd + +* noel64imafdc + +The start of the memory is set to 0x0 to match a standard NOEL-V system, but +can be changed using the ``RISCV_RAM_REGION_BEGIN`` configuration option. The +size of the memory is taken from the information available in the device tree. + +Reference Designs +----------------- + +The BSP has been tested with NOEL-V reference designs for `Digilent Arty A7 +<https://gaisler.com/noel-artya7>`_, `Microchip PolarFire Splash Kit +<https://gaisler.com/noel-pf>`_, and `Xilinx KCU105 +<https://gaisler.com/noel-xcku>`_. See the accompanying quickstart guide for +each reference design to determine which BSP configuration to use. + +Build Configuration Options +--------------------------- + +The following options can be used in the BSP section of the ``waf`` +configuration INI file. The ``waf`` defaults can be used to inspect the values. + +``BSP_CONSOLE_USE_INTERRUPTS`` + Use the Termios interrupt mode in the console driver (true by default). + +``BSP_FDT_BLOB_SIZE_MAX`` + The maximum size of the device tree blob in bytes (262144 by default). + +``RISCV_CONSOLE_MAX_APBUART_DEVICES`` + The maximum number of APBUART devices supported by the console driver + (2 by default). + +``RISCV_RAM_REGION_BEGIN`` + The begin of the RAM region for linker command file (0x0 by default). + +``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS`` + The maximum number of external interrupts supported by the BSP (64 by + default). + griscv ====== diff --git a/user/bsps/bsps-sh.rst b/user/bsps/bsps-sh.rst index b147251..8c245c4 100644 --- a/user/bsps/bsps-sh.rst +++ b/user/bsps/bsps-sh.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG sh (SuperH) *********** diff --git a/user/bsps/bsps-sparc.rst b/user/bsps/bsps-sparc.rst index d0316a9..325c7fa 100644 --- a/user/bsps/bsps-sparc.rst +++ b/user/bsps/bsps-sparc.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG .. Copyright (C) 2020 Chris Johns sparc (SPARC / LEON) @@ -20,11 +20,81 @@ TODO. leon2 ===== -TODO. +This BSP supports LEON2 systems, in particular the `Microchip AT697F +<https://www.microchip.com/en-us/product/AT697F>`_. The following +default build configurations are provided: + +* leon2 - A generic LEON2 system with memory at 0x4000000. + +* at697f - For the AT697F. Built with ``-mcpu=leon -mfix-at697f``. + +The BSP contains UART, timer, and interrupt controller drivers. +Drivers for PCI are available through the :ref:`driver manager <BSP_sparc_leon3_drv_mgr>`. .. _BSP_sparc_leon3: leon3 ===== -TODO. +This BSP supports the LEON3/4/5 systems from Cobham Gaisler. +The following default build configurations are provided: + +* leon3 - A generic `LEON3/4/5 <https://www.gaisler.com/leon5>`_ system with memory at 0x4000000. + +* ut700 - For the `UT700 <https://caes.com/product/ut700>`_. Built with ``-mcpu=leon3 -mfix-ut700``. + +* ut699 - For the `UT699 <https://caes.com/product/ut699>`_. Built with ``-mcpu=leon -mfix-ut699``. + +* gr712rc - For the `GR712RC <https://www.gaisler.com/gr712rc>`_. Built with ``-mcpu=leon3 -mfix-gr712rc``. + +* gr740 - For the `GR740 <https://www.gaisler.com/gr740>`_. Memory located at address 0x0. + +The BSP contains UART, timer, and interrupt controller drivers. Drivers for additional +peripherals are available through the driver manager. + +.. _BSP_sparc_leon3_drv_mgr: + +Driver Manager +-------------- + +The leon3 BSP includes an optional driver manager that handles drivers and +devices on the AMBA and PCI Plug & Play buses. The driver manager can either +be initialized manually by the user, or started automatically on startup by +setting the ``RTEMS_DRVMGR_STARTUP`` option. It can be configured to +automatically instantiate a driver for each hardware device found. + +Drivers for the following devices are provided and handled via the driver manager: + +* SpaceWire (GRSPW, GRSPW2, GRSPW2_DMA) +* SpaceWire Router (GRSPWROUTER) +* SpaceWire Time Distribution Protocol (SPWTDP) +* CAN - non-DMA (OCCAN) and DMA (GRCAN, GRCANFD) +- GPIO (GRGPIO) +- L2 Cache (L2CACHE) +- IOMMU (GRIOMMU) +- ADC/DAC (GRADCDAC) +- Timers (GPTIMER, GRTIMER) +- 1553 BC, RT and BM support (GR1553B) +- I2C Master (I2CMST) +- PCI (GRPCI2, GRPCI, PCIF) +- Memory Controller (MCTRL) +- Memory Scrubber (MEMSCRUB) +- Pulse Width Modulation Generator (GRPWM) +- CCSDS/ECSS Telemetry Encoder/Decoder (GRTM/GRTC) +- CSDS Time Manager (GRCTM) +- Ethernet (GRETH 10/100/1000) (requires network stack) +- Performance counters (L4STAT) +- Serial Peripheral Interface (AHBSTAT) +- AHB Status (AHBSTAT) + +Build Configuration Options +--------------------------- + +The following options can be used in the BSP section of the ``waf`` +configuration INI file. The ``waf`` defaults can be used to inspect the values. + +``CONSOLE_USE_INTERRUPTS`` + Use the Termios interrupt mode in the console driver (false by default). + +``RTEMS_DRVMGR_STARTUP`` + Enable the Driver Manager at startup (false by default). diff --git a/user/bsps/bsps-sparc64.rst b/user/bsps/bsps-sparc64.rst index e7be4ea..7b598b7 100644 --- a/user/bsps/bsps-sparc64.rst +++ b/user/bsps/bsps-sparc64.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG sparc64 (SPARC V9) ****************** diff --git a/user/bsps/bsps-v850.rst b/user/bsps/bsps-v850.rst index 39973db..220ccc0 100644 --- a/user/bsps/bsps-v850.rst +++ b/user/bsps/bsps-v850.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG v850 (V850) *********** diff --git a/user/bsps/bsps-x86_64.rst b/user/bsps/bsps-x86_64.rst index a7f7326..38d84e4 100644 --- a/user/bsps/bsps-x86_64.rst +++ b/user/bsps/bsps-x86_64.rst @@ -1,7 +1,7 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 .. Copyright (C) 2018 Amaan Cheval <amaan.cheval@gmail.com> -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG x86_64 ****** diff --git a/user/bsps/index.rst b/user/bsps/index.rst index bf590e0..5c1b3b7 100644 --- a/user/bsps/index.rst +++ b/user/bsps/index.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG .. _BSPs: |