8 files changed, 66 insertions, 7 deletions
diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
index 2b3d620..1e9b8d6 100644
--- a/cpu-supplement/aarch64.rst
+++ b/cpu-supplement/aarch64.rst
@@ -73,6 +73,11 @@ A flat 64-bit or 32-bit memory model is supported depending on the selected mult
 variant.  All AArch64 CPU variants support a built-in MMU for which basic initialization
 for a flat memory model is handled.
 
+Note that memcpy() and memset() must not be used on device memory as those
+functions are hand-optimized and will take advantage of unaligned accesses.
+*As per ARM*(https://developer.arm.com/documentation/ka004708/latest), unaligned
+accesses are not permitted for device memory.
+
 Interrupt Processing
 ====================
 
diff --git a/cpu-supplement/altera_nios_ii.rst b/cpu-supplement/altera_nios_ii.rst
index e8a6e95..d30a40d 100644
--- a/cpu-supplement/altera_nios_ii.rst
+++ b/cpu-supplement/altera_nios_ii.rst
@@ -13,4 +13,4 @@ SMP is not supported.
 Thread-Local Storage
 ====================
 
-Thread-local storage is not implemented.
+Thread-local storage is supported.
diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index ac9e8c6..b92e6d6 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -132,6 +132,12 @@ Memory Model
 A flat 32-bit memory model is supported.  The board support package must take
 care of initializing the MMU if necessary.
 
+Note that architecture variants which support unaligned accesses must not use
+memcpy() or memset() on device memory as those functions are hand-optimized and
+will take advantage of unaligned accesses where available. *As per ARM*
+(https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Alignment-support/Unaligned-data-access-restrictions-in-ARMv7-and-ARMv6),
+unaligned accesses are not permitted for device memory.
+
 Interrupt Processing
 ====================
 
diff --git a/cpu-supplement/epiphany.rst b/cpu-supplement/epiphany.rst
index c2b2d86..8b491d3 100644
--- a/cpu-supplement/epiphany.rst
+++ b/cpu-supplement/epiphany.rst
@@ -1,6 +1,6 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+.. Copyright (C) 2020 embedded brains GmbH & Co. KG
 
 Epiphany Specific Information
 *****************************
diff --git a/cpu-supplement/index.rst b/cpu-supplement/index.rst
index 733ffcc..25b05dd 100644
--- a/cpu-supplement/index.rst
+++ b/cpu-supplement/index.rst
@@ -8,7 +8,7 @@ RTEMS CPU Architecture Supplement (|version|).
 
 .. topic:: Copyrights and License
 
-    | |copy| 2016, 2018 embedded brains GmbH
+    | |copy| 2016, 2018 embedded brains GmbH & Co. KG
     | |copy| 2016, 2018 Sebastian Huber
     | |copy| 2014, 2015 Hesham Almatary
     | |copy| 2010 Gedare Bloom
diff --git a/cpu-supplement/riscv.rst b/cpu-supplement/riscv.rst
index 4d3fbaf..7b0961e 100644
--- a/cpu-supplement/riscv.rst
+++ b/cpu-supplement/riscv.rst
@@ -1,6 +1,6 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 2018 embedded brains GmbH
+.. Copyright (C) 2018 embedded brains GmbH & Co. KG
 
 RISC-V Specific Information
 ***************************
diff --git a/cpu-supplement/sparc.rst b/cpu-supplement/sparc.rst
index 11b63d9..c5b7210 100644
--- a/cpu-supplement/sparc.rst
+++ b/cpu-supplement/sparc.rst
@@ -1,6 +1,6 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+.. Copyright (C) 2021 embedded brains GmbH & Co. KG
 .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
 
 SPARC Specific Information
diff --git a/cpu-supplement/xilinx_microblaze.rst b/cpu-supplement/xilinx_microblaze.rst
index 2a92b61..350aeff 100644
--- a/cpu-supplement/xilinx_microblaze.rst
+++ b/cpu-supplement/xilinx_microblaze.rst
@@ -1,10 +1,58 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
+.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
 
 Xilinx MicroBlaze Specific Information
 **************************************
 
+This chapter discusses the dependencies of the *MicroBlaze architecture*
+(https://en.wikipedia.org/wiki/MicroBlaze).
+
+**Architecture Documents**
+
+For information on the MicroBlaze architecture, refer to
+*UG984 MicroBlaze Processor Reference Guide*
+(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
+
+CPU Model Dependent Features
+============================
+
+There are no CPU model dependent features in this port.
+
+Calling Conventions
+===================
+
+Please refer to "Chapter 4: MicroBlaze Application Binary Interface" of
+*UG984 MicroBlaze Processor Reference Guide*
+(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf).
+
+Interrupt Processing
+====================
+
+Hardware exceptions, interrupts, and user exceptions are all supported. When a
+hardware exception or user exception occurs, a fatal error will be generated.
+When an interrupt occurs, the interrupt source is determined by reading the
+AXI Interrupt Controller's Interrupt Status Register and masking it with the
+Interrupt Enable Register.
+
+Interrupt Levels
+----------------
+
+There are exactly two interrupt levels on MicroBlaze with respect to RTEMS.
+Level zero corresponds to interrupts disabled. Level one corresponds to
+interrupts enabled. This is the inverse of how most other architectures handle
+interrupt enable status.
+
+Interrupt Stack
+---------------
+
+The memory region for the interrupt stack is defined by the BSP.
+
+Default Fatal Error Processing
+==============================
+
+The default fatal error is BSP-specific.
+
 Symmetric Multiprocessing
 =========================
 
@@ -13,4 +61,4 @@ SMP is not supported.
 Thread-Local Storage
 ====================
 
-Thread-local storage is not implemented.
+Thread-local storage is supported.