diff options
Diffstat (limited to 'cpu-supplement')
| -rw-r--r-- | cpu-supplement/aarch64.rst | 5 | ||||
| -rw-r--r-- | cpu-supplement/altera_nios_ii.rst | 2 | ||||
| -rw-r--r-- | cpu-supplement/arm.rst | 6 | ||||
| -rw-r--r-- | cpu-supplement/epiphany.rst | 2 | ||||
| -rw-r--r-- | cpu-supplement/index.rst | 3 | ||||
| -rw-r--r-- | cpu-supplement/riscv.rst | 2 | ||||
| -rw-r--r-- | cpu-supplement/sparc.rst | 57 | ||||
| -rw-r--r-- | cpu-supplement/xilinx_microblaze.rst | 52 |
8 files changed, 104 insertions, 25 deletions
diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst index 2b3d620..1e9b8d6 100644 --- a/cpu-supplement/aarch64.rst +++ b/cpu-supplement/aarch64.rst @@ -73,6 +73,11 @@ A flat 64-bit or 32-bit memory model is supported depending on the selected mult variant. All AArch64 CPU variants support a built-in MMU for which basic initialization for a flat memory model is handled. +Note that memcpy() and memset() must not be used on device memory as those +functions are hand-optimized and will take advantage of unaligned accesses. +*As per ARM*(https://developer.arm.com/documentation/ka004708/latest), unaligned +accesses are not permitted for device memory. + Interrupt Processing ==================== diff --git a/cpu-supplement/altera_nios_ii.rst b/cpu-supplement/altera_nios_ii.rst index e8a6e95..d30a40d 100644 --- a/cpu-supplement/altera_nios_ii.rst +++ b/cpu-supplement/altera_nios_ii.rst @@ -13,4 +13,4 @@ SMP is not supported. Thread-Local Storage ==================== -Thread-local storage is not implemented. +Thread-local storage is supported. diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst index ac9e8c6..b92e6d6 100644 --- a/cpu-supplement/arm.rst +++ b/cpu-supplement/arm.rst @@ -132,6 +132,12 @@ Memory Model A flat 32-bit memory model is supported. The board support package must take care of initializing the MMU if necessary. +Note that architecture variants which support unaligned accesses must not use +memcpy() or memset() on device memory as those functions are hand-optimized and +will take advantage of unaligned accesses where available. *As per ARM* +(https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Alignment-support/Unaligned-data-access-restrictions-in-ARMv7-and-ARMv6), +unaligned accesses are not permitted for device memory. + Interrupt Processing ==================== diff --git a/cpu-supplement/epiphany.rst b/cpu-supplement/epiphany.rst index c2b2d86..8b491d3 100644 --- a/cpu-supplement/epiphany.rst +++ b/cpu-supplement/epiphany.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) +.. Copyright (C) 2020 embedded brains GmbH & Co. KG Epiphany Specific Information ***************************** diff --git a/cpu-supplement/index.rst b/cpu-supplement/index.rst index 951d6b7..25b05dd 100644 --- a/cpu-supplement/index.rst +++ b/cpu-supplement/index.rst @@ -8,7 +8,7 @@ RTEMS CPU Architecture Supplement (|version|). .. topic:: Copyrights and License - | |copy| 2016, 2018 embedded brains GmbH + | |copy| 2016, 2018 embedded brains GmbH & Co. KG | |copy| 2016, 2018 Sebastian Huber | |copy| 2014, 2015 Hesham Almatary | |copy| 2010 Gedare Bloom @@ -24,6 +24,7 @@ RTEMS CPU Architecture Supplement (|version|). preface port + aarch64 arm atmel_avr blackfin diff --git a/cpu-supplement/riscv.rst b/cpu-supplement/riscv.rst index 4d3fbaf..7b0961e 100644 --- a/cpu-supplement/riscv.rst +++ b/cpu-supplement/riscv.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 2018 embedded brains GmbH +.. Copyright (C) 2018 embedded brains GmbH & Co. KG RISC-V Specific Information *************************** diff --git a/cpu-supplement/sparc.rst b/cpu-supplement/sparc.rst index 4f39f34..c5b7210 100644 --- a/cpu-supplement/sparc.rst +++ b/cpu-supplement/sparc.rst @@ -1,5 +1,6 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 +.. Copyright (C) 2021 embedded brains GmbH & Co. KG .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) SPARC Specific Information @@ -563,35 +564,52 @@ state changes occur in the processor itself. The return address reported by the processor for synchronous traps is the instruction which caused the trap and the following instruction. +Trap Table +---------- + +A SPARC processor uses a trap table to execute the trap handler associated with +a trap. The trap table location is defined by the Trap Base Register +(``TBR``). The trap table has 256 entries. Each entry has space for four +instructions (16 bytes). RTEMS uses a statically initialized trap table. The +start address of the trap table is associated with the ``trap_table`` global +symbol. The first action of the system initialization (entry points ``_start`` +and ``hard_reset``) is to set the ``TBR`` to ``trap_table``. The interrupt +traps (trap numbers 16 to 31) are connected with the RTEMS interrupt handling. +Some traps are connected to standard services defined by the SPARC +architecture, for example the window overflow, underflow, and flush handling. +Most traps are connected to a fatal error handler. The fatal error trap +handler saves the processor context to an exception frame and starts the system +termination procedure. + Vectoring of Interrupt Handler ------------------------------ -Upon receipt of an interrupt the SPARC automatically performs the following -actions: +Upon receipt of an interrupt a SPARC processor automatically performs the +following actions: -- disables traps (sets the ET bit of the ``PSR`` to 0), +- disables traps (sets the ``PSR.ET`` bit to 0 in the ``PSR``), -- the S bit of the ``PSR`` is copied into the Previous Supervisor Mode (PS) bit of - the ``PSR``, +- the ``PSR.S`` bit is copied into the Previous Supervisor Mode (``PSR.PS``) + bit in the ``PSR``, - the ``CWP`` is decremented by one (modulo the number of register windows) to activate a trap window, -- the PC and nPC are loaded into local register 1 and 2 (l0 and l1), +- the PC and nPC are loaded into local register 1 and 2 (``%l0`` and ``%l1``), -- the trap type (tt) field of the Trap Base Register (``TBR``) is set to the - appropriate value, and +- the trap type (``tt``) field of the Trap Base Register (``TBR``) is set to + the appropriate value, and - if the trap is not a reset, then the PC is written with the contents of the - ``TBR`` and the nPC is written with ``TBR`` + 4. If the trap is a reset, then the PC - is set to zero and the nPC is set to 4. + ``TBR`` and the nPC is written with ``TBR`` + 4. If the trap is a reset, + then the PC is set to zero and the nPC is set to 4. Trap processing on the SPARC has two features which are noticeably different than interrupt processing on other architectures. First, the value of ``PSR`` register in effect immediately before the trap occurred is not explicitly saved. Instead only reversible alterations are made to it. Second, the -Processor Interrupt Level (pil) is not set to correspond to that of the -interrupt being processed. When a trap occurs, ALL subsequent traps are +Processor Interrupt Level (``PSR.PIL``) is not set to correspond to that of the +interrupt being processed. When a trap occurs, **all** subsequent traps are disabled. In order to safely invoke a subroutine during trap handling, traps must be enabled to allow for the possibility of register window overflow and underflow traps. @@ -698,15 +716,16 @@ Interrupt Stack The SPARC architecture does not provide for a dedicated interrupt stack. Thus by default, trap handlers would execute on the stack of the RTEMS task which they interrupted. This artificially inflates the stack requirements for each -task since EVERY task stack would have to include enough space to account for -the worst case interrupt stack requirements in addition to it's own worst case -usage. RTEMS addresses this problem on the SPARC by providing a dedicated +task since **every** task stack would have to include enough space to account +for the worst case interrupt stack requirements in addition to it's own worst +case usage. RTEMS addresses this problem on the SPARC by providing a dedicated interrupt stack managed by software. -During system initialization, RTEMS allocates the interrupt stack from the -Workspace Area. The amount of memory allocated for the interrupt stack is -determined by the interrupt_stack_size field in the CPU Configuration Table. -As part of processing a non-nested interrupt, RTEMS will switch to the +The interrupt stack is statically allocated by RTEMS. There is one interrupt +stack for each configured processor. The interrupt stack is used to initialize +the system. The amount of memory allocated for the interrupt stack is +determined by the ``CONFIGURE_INTERRUPT_STACK_SIZE`` application configuration +option. As part of processing a non-nested interrupt, RTEMS will switch to the interrupt stack before invoking the installed handler. Default Fatal Error Processing diff --git a/cpu-supplement/xilinx_microblaze.rst b/cpu-supplement/xilinx_microblaze.rst index 2a92b61..350aeff 100644 --- a/cpu-supplement/xilinx_microblaze.rst +++ b/cpu-supplement/xilinx_microblaze.rst @@ -1,10 +1,58 @@ .. SPDX-License-Identifier: CC-BY-SA-4.0 -.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) +.. Copyright (C) 2022 On-Line Applications Research Corporation (OAR) Xilinx MicroBlaze Specific Information ************************************** +This chapter discusses the dependencies of the *MicroBlaze architecture* +(https://en.wikipedia.org/wiki/MicroBlaze). + +**Architecture Documents** + +For information on the MicroBlaze architecture, refer to +*UG984 MicroBlaze Processor Reference Guide* +(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf). + +CPU Model Dependent Features +============================ + +There are no CPU model dependent features in this port. + +Calling Conventions +=================== + +Please refer to "Chapter 4: MicroBlaze Application Binary Interface" of +*UG984 MicroBlaze Processor Reference Guide* +(https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_2/ug984-vivado-microblaze-ref.pdf). + +Interrupt Processing +==================== + +Hardware exceptions, interrupts, and user exceptions are all supported. When a +hardware exception or user exception occurs, a fatal error will be generated. +When an interrupt occurs, the interrupt source is determined by reading the +AXI Interrupt Controller's Interrupt Status Register and masking it with the +Interrupt Enable Register. + +Interrupt Levels +---------------- + +There are exactly two interrupt levels on MicroBlaze with respect to RTEMS. +Level zero corresponds to interrupts disabled. Level one corresponds to +interrupts enabled. This is the inverse of how most other architectures handle +interrupt enable status. + +Interrupt Stack +--------------- + +The memory region for the interrupt stack is defined by the BSP. + +Default Fatal Error Processing +============================== + +The default fatal error is BSP-specific. + Symmetric Multiprocessing ========================= @@ -13,4 +61,4 @@ SMP is not supported. Thread-Local Storage ==================== -Thread-local storage is not implemented. +Thread-local storage is supported. |