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author | Chris Johns <chrisj@rtems.org> | 2016-11-03 16:58:08 +1100 |
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committer | Chris Johns <chrisj@rtems.org> | 2016-11-03 16:58:08 +1100 |
commit | 72a62ad88f82fe1ffee50024db4dd0f3fa5806f7 (patch) | |
tree | 6b0e527e67141f8126ba56b8a3c1eb90aeed5849 /cpu_supplement/openrisc_1000.rst | |
parent | waf: Use separate doctrees so avoid sphinx clashes. (diff) | |
download | rtems-docs-72a62ad88f82fe1ffee50024db4dd0f3fa5806f7.tar.bz2 |
Rename all manuals with an _ to have a -. It helps released naming of files.
Diffstat (limited to 'cpu_supplement/openrisc_1000.rst')
-rw-r--r-- | cpu_supplement/openrisc_1000.rst | 97 |
1 files changed, 0 insertions, 97 deletions
diff --git a/cpu_supplement/openrisc_1000.rst b/cpu_supplement/openrisc_1000.rst deleted file mode 100644 index c9d6127..0000000 --- a/cpu_supplement/openrisc_1000.rst +++ /dev/null @@ -1,97 +0,0 @@ -.. comment SPDX-License-Identifier: CC-BY-SA-4.0 - -.. COMMENT: COPYRIGHT (c) 1989-2007. -.. COMMENT: On-Line Applications Research Corporation (OAR). -.. COMMENT: All rights reserved. - -OpenRISC 1000 Specific Information -################################## - -This chapter discusses the`OpenRISC 1000 architecture -http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There -are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS -supports basic features that all implementations should have. - -**Architecture Documents** - -For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000 -architecture manual http://openrisc.github.io/or1k.html. - -Calling Conventions -=================== - -Please refer to the`Function Calling Sequence -http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882. - -Floating Point Unit -------------------- - -A floating point unit is currently not supported. - -Memory Model -============ - -A flat 32-bit memory model is supported. - -Interrupt Processing -==================== - -OpenRISC 1000 architecture has 13 exception types: - -- Reset - -- Bus Error - -- Data Page Fault - -- Instruction Page Fault - -- Tick Timer - -- Alignment - -- Illegal Instruction - -- External Interrupt - -- D-TLB Miss - -- I-TLB Miss - -- Range - -- System Call - -- Floating Point - -- Trap - -Interrupt Levels ----------------- - -There are only two levels: interrupts enabled and interrupts disabled. - -Interrupt Stack ---------------- - -The OpenRISC RTEMS port uses a dedicated software interrupt stack. The stack -for interrupts is allocated during interrupt driver initialization. When an -interrupt is entered, the _ISR_Handler routine is responsible for switching -from the interrupted task stack to RTEMS software interrupt stack. - -Default Fatal Error Processing -============================== - -The default fatal error handler for this architecture performs the following -actions: - -- disables operating system supported interrupts (IRQ), - -- places the error code in ``r0``, and - -- executes an infinite loop to simulate a halt processor instruction. - -Symmetric Multiprocessing -========================= - -SMP is not supported. |