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authorGedare Bloom <gedare@rtems.org>2021-06-08 14:42:26 -0600
committerGedare Bloom <gedare@rtems.org>2021-06-08 14:42:26 -0600
commit1a281869a945ea403c97e149d65ce78170095188 (patch)
treee2baf45ce1a2ffc83c7a41d737c0c52366895c68
parent528a2b66e92f529d345dfa7c195bc03905f3817d (diff)
downloadrtems-docs-1a281869a945ea403c97e149d65ce78170095188.tar.bz2
user: add bsps/aarch64/a72.rst
-rw-r--r--user/bsps/aarch64/a72.rst35
-rw-r--r--user/bsps/bsps-aarch64.rst1
2 files changed, 36 insertions, 0 deletions
diff --git a/user/bsps/aarch64/a72.rst b/user/bsps/aarch64/a72.rst
new file mode 100644
index 0000000..e8e4b3d
--- /dev/null
+++ b/user/bsps/aarch64/a72.rst
@@ -0,0 +1,35 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+
+.. _BSP_aarch64_qemu_a72_ilp32:
+.. _BSP_aarch64_qemu_a72_lp64:
+
+Qemu A72
+========
+
+This BSP supports two variants, `qemu_a72_ilp32` and `qemu_a72_lp64`. The basic
+hardware initialization is performed by the BSP. These BSPs support the GICv3
+interrupt controller.
+
+Boot via ELF
+------------
+The executable image is booted by Qemu in ELF format.
+
+Clock Driver
+------------
+
+The clock driver uses the `ARM Generic Timer`.
+
+Console Driver
+--------------
+
+The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART.
+
+Running Executables
+-------------------
+
+Executables generated by these BSPs can be run using the following command::
+
+qemu-system-aarch64 -no-reboot -nographic -serial mon:stdio \
+ -machine virt,gic-version=3 -cpu cortex-a72 -m 4096 -kernel example.exe
diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst
index 0d4b23c..566a750 100644
--- a/user/bsps/bsps-aarch64.rst
+++ b/user/bsps/bsps-aarch64.rst
@@ -6,4 +6,5 @@ aarch64 (AArch64)
*****************
.. include:: aarch64/a53.rst
+.. include:: aarch64/a72.rst
.. include:: aarch64/xilinx-zynqmp.rst