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SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
brief: |
Invalidates the instruction cache lines covering the memory area.
copyrights:
- Copyright (C) 2014, 2021 embedded brains GmbH (http://www.embedded-brains.de)
definition:
default:
attributes: null
body: null
params:
- const void *${.:/params[0]/name}
- ${/c/if/size_t:/name} ${.:/params[1]/name}
return: void
variants: []
description: |
The cache lines covering the area are marked as invalid. A later
instruction fetch from the area will result in a load from memory.
enabled-by: true
index-entries: []
interface-type: function
links:
- role: interface-placement
uid: header
- role: interface-ingroup
uid: group
- role: constraint
uid: /constraint/directive-ctx-any
- role: constraint
uid: /constraint/directive-no-preempt
name: rtems_cache_invalidate_multiple_instruction_lines
notes: |
In SMP configurations, on processors without instruction cache snooping, this
operation will invalidate the instruction cache lines on all processors.
params:
- description: |
is the begin address of the memory area to invalidate.
dir: null
name: begin
- description: |
is the size in bytes of the memory area to invalidate.
dir: null
name: size
return: null
type: interface
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