path: root/spec/dev/grlib/if/griommu.yml

SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
brief: |
  This structure defines the ${.:/register-block-group} register block memory
  map.
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
description: null
enabled-by: true
identifier: RTEMSDeviceGRIOMMU
index-entries: []
interface-type: register-block
links:
- role: interface-ingroup
  uid: group
- role: interface-placement
  uid: griommu-header
definition:
- default:
    count: 1
    name: CAP0
  offset: 0x0
  variants: []
- default:
    count: 1
    name: CAP1
  offset: 0x4
  variants: []
- default:
    count: 1
    name: CAP2
  offset: 0x8
  variants: []
- default:
    count: 1
    name: CTRL
  offset: 0x10
  variants: []
- default:
    count: 1
    name: FLUSH
  offset: 0x14
  variants: []
- default:
    count: 1
    name: STATUS
  offset: 0x18
  variants: []
- default:
    count: 1
    name: IMASK
  offset: 0x1c
  variants: []
- default:
    count: 1
    name: AHBFAS
  offset: 0x20
  variants: []
- default:
    count: 1
    name: MSTCFG
  offset: 0x40
  variants: []
- default:
    count: 1
    name: MSTCFG
  offset: 0x64
  variants: []
- default:
    count: 1
    name: GRPCTRL
  offset: 0x80
  variants: []
- default:
    count: 1
    name: GRPCTRL
  offset: 0x9c
  variants: []
- default:
    count: 1
    name: DIAGCTRL
  offset: 0xc0
  variants: []
- default:
    count: 1
    name: DIAGD
  offset: 0xc4
  variants: []
- default:
    count: 1
    name: DIAGD
  offset: 0xe0
  variants: []
- default:
    count: 1
    name: DIAGT
  offset: 0xe4
  variants: []
- default:
    count: 1
    name: DERRI
  offset: 0xe8
  variants: []
- default:
    count: 1
    name: TERRI
  offset: 0xec
  variants: []
- default:
    count: 1
    name: ASMPCTRL
  offset: 0x100
  variants: []
- default:
    count: 1
    name: ASMPCTRL
  offset: 0x10c
  variants: []
register-prefix: null
register-block-group: GRIOMMU
register-block-size: 272
registers:
- bits:
  - default:
    - access: [r]
      brief: null
      description: null
      name: 'A'
      start: 31
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'AC'
      start: 30
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'CA'
      start: 29
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'CP'
      start: 28
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'NARB'
      start: 20
      width: 4
    - access: [r]
      brief: null
      description: null
      name: 'CS'
      start: 19
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'FT'
      start: 17
      width: 2
    - access: [r]
      brief: null
      description: null
      name: 'ST'
      start: 16
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'I'
      start: 15
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'IT'
      start: 14
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'IA'
      start: 13
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'IP'
      start: 12
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'MB'
      start: 8
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'GRPS'
      start: 4
      width: 4
    - access: [r]
      brief: null
      description: null
      name: 'MSTS'
      start: 0
      width: 4
    variants: []
  brief: |
    Capability register 0
  description: null
  name: CAP0
  width: 32
- bits:
  - default:
    - access: [r]
      brief: null
      description: null
      name: 'CADDR'
      start: 20
      width: 12
    - access: [r]
      brief: null
      description: null
      name: 'CMASK'
      start: 16
      width: 4
    - access: [r]
      brief: null
      description: null
      name: 'CTAGBITS'
      start: 8
      width: 8
    - access: [r]
      brief: null
      description: null
      name: 'CISIZE'
      start: 5
      width: 3
    - access: [r]
      brief: null
      description: null
      name: 'CLINES'
      start: 0
      width: 5
    variants: []
  brief: |
    Capability register 1
  description: null
  name: CAP1
  width: 32
- bits:
  - default:
    - access: [r]
      brief: null
      description: null
      name: 'TMASK'
      start: 24
      width: 8
    - access: [r]
      brief: null
      description: null
      name: 'MTYPE'
      start: 18
      width: 2
    - access: [r]
      brief: null
      description: null
      name: 'TTYPE'
      start: 16
      width: 2
    - access: [r]
      brief: null
      description: null
      name: 'TTAGBITS'
      start: 8
      width: 8
    - access: [r]
      brief: null
      description: null
      name: 'ISIZE'
      start: 5
      width: 3
    - access: [r]
      brief: null
      description: null
      name: 'TLBENT'
      start: 0
      width: 5
    variants: []
  brief: |
    Capability register 2
  description: null
  name: CAP2
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'PGSZ'
      start: 18
      width: 3
    - access: [r, w]
      brief: null
      description: null
      name: 'LB'
      start: 17
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'SP'
      start: 16
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'ITR'
      start: 12
      width: 4
    - access: [r, w]
      brief: null
      description: null
      name: 'DP'
      start: 11
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'SIV'
      start: 10
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'HPROT'
      start: 8
      width: 2
    - access: [r, w]
      brief: null
      description: null
      name: 'AU'
      start: 7
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'WP'
      start: 6
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'DM'
      start: 5
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'GS'
      start: 4
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'CE'
      start: 3
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'PM'
      start: 1
      width: 2
    - access: [r, w]
      brief: null
      description: null
      name: 'EN'
      start: 0
      width: 1
    variants: []
  brief: |
    Control register
  description: null
  name: CTRL
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'FGRP'
      start: 4
      width: 4
    - access: [r, w]
      brief: null
      description: null
      name: 'GF'
      start: 1
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'F'
      start: 0
      width: 1
    variants: []
  brief: |
    TLB/cache flush register
  description: null
  name: FLUSH
  width: 32
- bits:
  - default:
    - access: [r, w1c]
      brief: null
      description: null
      name: 'PE'
      start: 5
      width: 1
    - access: [r, w1c]
      brief: null
      description: null
      name: 'DE'
      start: 4
      width: 1
    - access: [r, w1c]
      brief: null
      description: null
      name: 'FC'
      start: 3
      width: 1
    - access: [r, w1c]
      brief: null
      description: null
      name: 'FL'
      start: 2
      width: 1
    - access: [r, w1c]
      brief: null
      description: null
      name: 'AD'
      start: 1
      width: 1
    - access: [r, w1c]
      brief: null
      description: null
      name: 'TE'
      start: 0
      width: 1
    variants: []
  brief: |
    Status register
  description: null
  name: STATUS
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'PEI'
      start: 5
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'FCI'
      start: 3
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'FLI'
      start: 2
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'ADI'
      start: 1
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'TEI'
      start: 0
      width: 1
    variants: []
  brief: |
    Interrupt mask register
  description: null
  name: IMASK
  width: 32
- bits:
  - default:
    - access: [r]
      brief: null
      description: null
      name: 'FADDR_31_5'
      start: 5
      width: 27
    - access: [r]
      brief: null
      description: null
      name: 'FW'
      start: 4
      width: 1
    - access: [r]
      brief: null
      description: null
      name: 'FMASTER'
      start: 0
      width: 4
    variants: []
  brief: |
    AHB failing access register
  description: null
  name: AHBFAS
  width: 32
- bits:
  - default:
    - access: [r]
      brief: null
      description: null
      name: 'VENDOR'
      start: 24
      width: 8
    - access: [r]
      brief: null
      description: null
      name: 'DEVICE'
      start: 12
      width: 12
    - access: [r, w]
      brief: null
      description: null
      name: 'BS'
      start: 4
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'GROUP'
      start: 0
      width: 4
    variants: []
  brief: |
    Master configuration register 0 - 9
  description: null
  name: MSTCFG
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'BASE_31_4'
      start: 4
      width: 28
    - access: [r, w]
      brief: null
      description: null
      name: 'P'
      start: 1
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'AG'
      start: 0
      width: 1
    variants: []
  brief: |
    Group control register 0 - 7
  description: null
  name: GRPCTRL
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'DA'
      start: 31
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'RW'
      start: 30
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'DP'
      start: 21
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'TP'
      start: 20
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'SETADDR'
      start: 0
      width: 19
    variants: []
  brief: |
    Diagnostic cache access register
  description: null
  name: DIAGCTRL
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'CDATAN'
      start: 0
      width: 32
    variants: []
  brief: |
    Diagnostic cache access data register 0 - 7
  description: null
  name: DIAGD
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'TAG'
      start: 1
      width: 31
    - access: [r, w]
      brief: null
      description: null
      name: 'V'
      start: 0
      width: 1
    variants: []
  brief: |
    Diagnostic cache access tag register
  description: null
  name: DIAGT
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'DPERRINJ'
      start: 0
      width: 32
    variants: []
  brief: |
    Data RAM error injection register
  description: null
  name: DERRI
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'TPERRINJ'
      start: 0
      width: 32
    variants: []
  brief: |
    Tag RAM error injection register
  description: null
  name: TERRI
  width: 32
- bits:
  - default:
    - access: [r, w]
      brief: null
      description: null
      name: 'FC'
      start: 18
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'SC'
      start: 17
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'MC'
      start: 16
      width: 1
    - access: [r, w]
      brief: null
      description: null
      name: 'GRPACCSZCTRL'
      start: 0
      width: 16
    variants: []
  brief: |
    ASMP access control registers 0 - 3
  description: null
  name: ASMPCTRL
  width: 32
name: griommu
notes: null
type: interface