1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
|
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
brief: |
This structure defines the ${.:/register-block-group} register block memory
map.
copyrights:
- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
description: null
enabled-by: true
identifier: RTEMSDeviceGRGPIO
index-entries: []
interface-type: register-block
links:
- role: interface-ingroup
uid: group
- role: interface-placement
uid: grgpio-header
definition:
- default:
count: 1
name: DATA
offset: 0x0
variants: []
- default:
count: 1
name: OUTPUT
offset: 0x4
variants: []
- default:
count: 1
name: DIRECTION
offset: 0x8
variants: []
- default:
count: 1
name: IMASK
offset: 0xc
variants: []
- default:
count: 1
name: IPOL
offset: 0x10
variants: []
- default:
count: 1
name: IEDGE
offset: 0x14
variants: []
- default:
count: 1
name: BYPASS
offset: 0x18
variants: []
- default:
count: 1
name: CAP
offset: 0x1c
variants: []
- default:
count: 8
name: IRQMAPR
offset: 0x20
variants: []
- default:
count: 1
name: IAVAIL
offset: 0x40
variants: []
- default:
count: 1
name: IFLAG
offset: 0x44
variants: []
- default:
count: 1
name: IPEN
offset: 0x48
variants: []
- default:
count: 1
name: PULSE
offset: 0x4c
variants: []
- default:
count: 1
name: LOR:LOR_OUTPUT
offset: 0x54
variants: []
- default:
count: 1
name: LOR:LOR_DIRECTION
offset: 0x58
variants: []
- default:
count: 1
name: LOR:LOR_IMASK
offset: 0x5c
variants: []
- default:
count: 1
name: LAND:LAND_OUTPUT
offset: 0x64
variants: []
- default:
count: 1
name: LAND:LAND_DIRECTION
offset: 0x68
variants: []
- default:
count: 1
name: LAND:LAND_IMASK
offset: 0x6c
variants: []
- default:
count: 1
name: LXOR:LXOR_OUTPUT
offset: 0x74
variants: []
- default:
count: 1
name: LXOR:LXOR_DIRECTION
offset: 0x78
variants: []
- default:
count: 1
name: LXOR:LXOR_IMASK
offset: 0x7c
variants: []
register-prefix: null
register-block-group: GRGPIO
register-block-size: 128
registers:
- bits:
- default:
- access: [r]
brief: null
description: null
name: 'DATA'
start: 0
width: 32
variants: []
brief: |
I/O port data register
description: null
name: DATA
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'DATA'
start: 0
width: 32
variants: []
brief: |
I/O port output register
description: null
name: OUTPUT
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'DIR'
start: 0
width: 32
variants: []
brief: |
I/O port direction register
description: null
name: DIRECTION
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'MASK'
start: 0
width: 32
variants: []
brief: |
Interrupt mask register
description: null
name: IMASK
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'POL'
start: 0
width: 32
variants: []
brief: |
Interrupt polarity register
description: null
name: IPOL
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'EDGE'
start: 0
width: 32
variants: []
brief: |
Interrupt edge register
description: null
name: IEDGE
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'BYPASS'
start: 0
width: 32
variants: []
brief: |
Bypass register
description: null
name: BYPASS
width: 32
- bits:
- default:
- access: [r]
brief: null
description: null
name: 'PU'
start: 18
width: 1
- access: [r]
brief: null
description: null
name: 'IER'
start: 17
width: 1
- access: [r]
brief: null
description: null
name: 'IFL'
start: 16
width: 1
- access: [r]
brief: null
description: null
name: 'IRQGEN'
start: 8
width: 5
- access: [r]
brief: null
description: null
name: 'NLINES'
start: 0
width: 5
variants: []
brief: |
Capability register
description: null
name: CAP
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'IRQMAP_I_0'
start: 24
width: 5
- access: [r, w]
brief: null
description: null
name: 'IRQMAP_I_1'
start: 16
width: 5
- access: [r, w]
brief: null
description: null
name: 'IRQMAP_I_2'
start: 8
width: 5
- access: [r, w]
brief: null
description: null
name: 'IRQMAP_I_3'
start: 0
width: 5
variants: []
brief: |
Interrupt map register n, where n = 0 .. 3
description: null
name: IRQMAPR
width: 32
- bits:
- default:
- access: [r]
brief: null
description: null
name: 'IMASK'
start: 0
width: 32
variants: []
brief: |
Interrupt available register
description: null
name: IAVAIL
width: 32
- bits:
- default:
- access: [r, w1c]
brief: null
description: null
name: 'IFLAG'
start: 0
width: 32
variants: []
brief: |
Interrupt flag register
description: null
name: IFLAG
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'IPEN'
start: 0
width: 32
variants: []
brief: |
Interrupt enable register
description: null
name: IPEN
width: 32
- bits:
- default:
- access: [r, w]
brief: null
description: null
name: 'PULSE'
start: 0
width: 32
variants: []
brief: |
Pulse register
description: null
name: PULSE
width: 32
- bits:
- default:
- access: [w]
brief: null
description: null
name: 'DATA'
start: 0
width: 32
variants: []
brief: |
Logical-OR registers
description: null
name: LOR
width: 32
- bits:
- default:
- access: [w]
brief: null
description: null
name: 'DATA'
start: 0
width: 32
variants: []
brief: |
Logical-AND registers
description: null
name: LAND
width: 32
- bits:
- default:
- access: [w]
brief: null
description: null
name: 'DATA'
start: 0
width: 32
variants: []
brief: |
Logical-XOR registers
description: null
name: LXOR
width: 32
name: grgpio
notes: null
type: interface
|