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-rw-r--r--spec/rtems/intr/if/lock-isr-disable.yml18
1 files changed, 13 insertions, 5 deletions
diff --git a/spec/rtems/intr/if/lock-isr-disable.yml b/spec/rtems/intr/if/lock-isr-disable.yml
index 088e00f8..acf184b3 100644
--- a/spec/rtems/intr/if/lock-isr-disable.yml
+++ b/spec/rtems/intr/if/lock-isr-disable.yml
@@ -1,12 +1,15 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
-brief: '%'
+brief: |
+ Disables maskable interrupts on the current processor.
copyrights:
-- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
- Copyright (C) 1988, 2008 On-Line Applications Research Corporation (OAR)
definition:
default: ${/score/isr/if/lock-isr-disable:/name}( ${.:/params[0]/name} )
variants: []
-description: null
+description: |
+ This directive disables maskable interrupts on the current processor and
+ stores the previous interrupt level in ${.:/params[0]/name}.
enabled-by: true
index-entries: []
interface-type: macro
@@ -15,11 +18,16 @@ links:
uid: header
- role: interface-ingroup
uid: group
+- role: constraint
+ uid: /constraint/directive-ctx-any
+- role: constraint
+ uid: /constraint/directive-no-preempt
name: rtems_interrupt_lock_interrupt_disable
notes: null
params:
-- description: '%'
- dir: null
+- description: |
+ is the ISR lock context for an acquire and release pair.
+ dir: out
name: _lock_context
return:
return: null