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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-05 14:41:18 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-05-22 15:47:26 +0200 |
| commit | a0032254c179e687de41f1ad48c68871404fae20 (patch) | |
| tree | 98fb054752c77b7c5d7f0cdb9de004470798df33 /spec/dev/grlib/if/spwpnp.yml | |
| parent | Fix JSON format errors (diff) | |
| download | rtems-central-a0032254c179e687de41f1ad48c68871404fae20.tar.bz2 | |
spec: Register blocks access -> properties
Diffstat (limited to 'spec/dev/grlib/if/spwpnp.yml')
| -rw-r--r-- | spec/dev/grlib/if/spwpnp.yml | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/spec/dev/grlib/if/spwpnp.yml b/spec/dev/grlib/if/spwpnp.yml index eed21f7c..5c103702 100644 --- a/spec/dev/grlib/if/spwpnp.yml +++ b/spec/dev/grlib/if/spwpnp.yml @@ -90,13 +90,13 @@ register-block-size: 49156 registers: - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'VEND' start: 16 width: 16 - - access: [r] + - properties: [r] brief: null description: null name: 'PROD' @@ -110,19 +110,19 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'MAJOR' start: 24 width: 8 - - access: [r] + - properties: [r] brief: null description: null name: 'MINOR' start: 16 width: 8 - - access: [r] + - properties: [r] brief: null description: null name: 'PATCH' @@ -136,7 +136,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'STATUS' @@ -150,7 +150,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'ACTIVE' @@ -164,7 +164,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'RA' @@ -178,7 +178,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'RA' @@ -192,7 +192,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'RA' @@ -206,7 +206,7 @@ registers: width: 32 - bits: - default: - - access: [r, w, cas] + - properties: [r, w, cas] brief: null description: null name: 'DID' @@ -220,13 +220,13 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'VEND' start: 16 width: 16 - - access: [r] + - properties: [r] brief: null description: null name: 'PROD' @@ -240,7 +240,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'USN' @@ -254,7 +254,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'LEN' @@ -268,7 +268,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'LEN' @@ -282,7 +282,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'PC' @@ -296,7 +296,7 @@ registers: width: 32 - bits: - default: - - access: [r] + - properties: [r] brief: null description: null name: 'AC' |