| Age | Commit message (Collapse) | Author |
|---|
|
At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.
|
|
This patch adds driver for Mini UART present in Raspberry Pi 3
and above, this UART is currently used as the primary UART in
these models.
The Mini UART is similar to ns16550, this driver is built
upon libchip/ns16550.
|
|
Place idle and MPCI stacks into extra linker sections. This can be
optionally used by applications to control the placement of the stacks.
Update #3835.
|
|
This avoids to pull in via printk() the Termios support which pulls in
the file system support. This fixes a spconfig02 test failure.
|
|
Update #3869.
|
|
Update #3869.
|
|
This uses the tx-threshold to reduce gaps in SPI transmissions.
Update #3869.
|
|
Update #3869.
|
|
The new area is used by the i.MX 6UltraLite for example.
Update #3869.
|
|
Update #3869.
|
|
Update #3869.
|
|
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5 instead of RTEMS_SYSINIT_ORDER_LAST
to allow applications and support functions to place system
initialization handlers behind the standard handlers.
Update #3838.
|
|
The work area initialization was done by the BSP through
bsp_work_area_initialize(). This approach predated the system
initialization through the system initialization linker set. The
workspace and C program heap were unconditionally initialized. The aim
is to support RTEMS application configurations which do not need the
workspace and C program heap. In these configurations, the workspace
and C prgram heap should not get initialized.
Change all bsp_work_area_initialize() to implement _Memory_Get()
instead. Move the dirty memory, sbrk(), per-CPU data, workspace, and
malloc() heap initialization into separate system initialization steps.
This makes it also easier to test the individual initialization steps.
This change adds a dependency to _Heap_Extend() to all BSPs. This
dependency will be removed in a follow up change.
Update #3838.
|
|
The code covered by BSP_GET_WORK_AREA_DEBUG was basically dead code
since there was no normal way to activate it (e.g. via a BSP
configuration option). A follow up patch will bring back this feature
through a CONFIGURE_VERBOSE_SYSTEM_INITIALIZATION configuration option.
Update #3838.
|
|
Update #3838.
|
|
This adds support for the GICv3 interrupt controller along with the
redistributor to control SGIs and PPIs which wasn't present in GICv2
implementations. GICv3 implementations only optionally support
memory-mapped GICC interface interaction and require system register
access be implemented, so the GICC interface is accessed only
through system registers.
|
|
Replaces the legacy termios API with new termios API (#3034)
Replaces the custom PL011 serial driver with RTEMS arm-pl011.
Update #3034
|
|
This commit adds FDT support to the BSP.
|
|
The BSP tried to get the size of the SDRAM based on the revision code.
Unfortunately the code had some bugs so that the default size has been
used. Beneath that the MMU table hasn't been adapted.
This patch queries the SDRAM size via a special VC Mailbox call instead.
For the MMU adaption a simmilar method to the one in the imx BSP is
used.
|
|
The imx BSP contained a hack to change the workspace entry of the MMU
table. This makes the used define visible for other BSPs too so that the
same hack can be used for example in raspberry pi too.
|
|
Close #3789.
|
|
Update #3818.
|
|
Create the Xen BSP for Xen on ARM.
|
|
Xen will mask the virtual timer before injecting the interrupt to the
guest.
|
|
Xen currently only supports the zImage loader for 32 bit guests on ARM
targets.
|
|
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
|
|
This BSP family uses only one linker command file. Use the standard
name.
Update #3818.
|
|
|
|
The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.
Enable it by default on the realview_pbx_a9_qemu BSP.
|
|
Use NULL-pointer protection also for Qemu variant.
Do all calculations in the linker command file. This is a preparation
for the new build system.
|
|
Do all calculations in the linker command file. This is a preparation
for the new build system.
|
|
This allows to mix SC16IS752 chips with other interrupts.
|
|
|
|
For level triggered interrupts currently the handler would have been
called two times (assuming no one cleared the mask in a handler which
would have been bad because the handler couldn't process all other that
got cleared by accident). This patch allows the handler only to return
if nothing is left to do.
|
|
|
|
|
|
- The TI's CortexA7 MP MPIDR register returns 0
Updates #3760
|
|
- Update the linkcmd file to support configure settings
- Set the workspace size based on the revision value
|
|
Closes #3777
|
|
Closes #3780
|
|
Remove static stuff that is never used.
|
|
- Port the jbang code from C++ to C to enable DBGEN.
- Hook the libdebugger ARM backend support to return the base address
of the debug register set.
|
|
Closes #3760
|
|
Add NULL-pointer protection. Make MMU table read-only. Move vector
table to start section.
Close #3774.
|
|
This fixes the corruption of r3 by the call to
bsp_start_arm_drop_hyp_mode().
Moving the code makes it easier to review changes in start.S.
Close #3773.
|
|
This makes it easier to review changes in start.S.
Update #3773.
|
|
There are no known ARMv7-M chips with a dual lockstep mode.
Update #3773.
|
