diff options
Diffstat (limited to 'cpukit/score/cpu/i386/include/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/i386/include/rtems/score/cpu.h | 38 |
1 files changed, 22 insertions, 16 deletions
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h b/cpukit/score/cpu/i386/include/rtems/score/cpu.h index 5d14455563..632bf5ff38 100644 --- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h @@ -115,9 +115,10 @@ extern "C" { #define I386_CONTEXT_CONTROL_EDI_OFFSET 20 #define I386_CONTEXT_CONTROL_GS_0_OFFSET 24 #define I386_CONTEXT_CONTROL_GS_1_OFFSET 28 +#define I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32 #ifdef RTEMS_SMP - #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32 + #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 36 #endif /* structures */ @@ -136,6 +137,7 @@ typedef struct { uint32_t esi; /* extended source index register */ uint32_t edi; /* extended destination index flags register */ segment_descriptors gs; /* gs segment descriptor */ + uint32_t isr_dispatch_disable; #ifdef RTEMS_SMP volatile bool is_executing; #endif @@ -262,25 +264,27 @@ typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); extern cpuExcHandlerType _currentExcHandler; extern void rtems_exception_init_mngt(void); -#ifdef RTEMS_SMP - /* Throw compile-time error to indicate incomplete support */ - #error "i386 targets do not support SMP.\ - See: https://devel.rtems.org/ticket/3335" - - /* - * This size must match the size of the CPU_Interrupt_frame, which must be - * used in the SMP context switch code, which is incomplete at the moment. - */ - #define CPU_INTERRUPT_FRAME_SIZE 4 -#endif - /* * This port does not pass any frame info to the * interrupt handler. */ typedef struct { - uint32_t todo_replace_with_apt_registers; +/* allow for 16B alignment (worst case 12 Bytes more) and isr right after pushfl */ + uint32_t reserved[3]; +/* registers saved by _ISR_Handler */ + uint32_t isr_vector; + uint32_t ebx; + uint32_t ebp; + uint32_t esp; +/* registers saved by rtems_irq_prologue_##_vector */ + uint32_t edx; + uint32_t ecx; + uint32_t eax; +/* registers saved by CPU */ + uint32_t eip; + uint32_t cs; + uint32_t eflags; } CPU_Interrupt_frame; typedef enum { @@ -499,6 +503,8 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) /* end of Fatal Error manager macros */ +#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE + /* * Bitfield handler macros * @@ -615,7 +621,7 @@ void _CPU_Context_save_fp( __asm__ __volatile__( \ "fldcw %0" \ ::"m"((*(fp_context_pp))->fpucw) \ - :"fpcr" \ + :"memory" \ ); \ __builtin_ia32_ldmxcsr(_Thread_Executing->fp_context->mxcsr); \ } while (0) @@ -634,7 +640,7 @@ void _CPU_Context_restore_fp( : \ :"st","st(1)","st(2)","st(3)", \ "st(4)","st(5)","st(6)","st(7)", \ - "fpsr","fpcr" \ + "fpsr","memory" \ ); \ if ( _Thread_Executing->fp_context ) { \ _CPU_Context_restore_fp(&_Thread_Executing->fp_context); \ |