| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-12-15 | Added support for RISCV32 systems with CLINT/PLIC | Jiri Gaisler | |
| 2020-09-09 | Map RISC-V FPU CSR on host cpu using fenv.h | Jiri Gaisler | |
| 2019-06-11 | Fix C formatting with indent | Jiri Gaisler | |
| 2019-06-11 | Avoid array out of bounds warning on RISC-V | Jiri Gaisler | |
| 2019-05-28 | Made L1 cache optional through --enable-l1cache | Jiri Gaisler | |
| * Removed stale config.h * Updated autoconf script with relevant checks * Re-implemented leon3/grlib timer with less events * Bumped version to 2.15 | |||
| 2019-05-27 | Add emulated L1 cache to SMP configurations | Jiri Gaisler | |
| * Also improve timing accuracy for certain instructions | |||
| 2019-05-14 | Standalone sis - initial commit | Jiri Gaisler | |
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index : sis.git | |
| Clone of master repository. | Charlie & |
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